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Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling
Felice Crupi, Massimo Alioto, Senior Member, IEEE, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Fellow, IEEE, Jrme Mitard, Liesbeth Witters, and Thomas Y. Hoffmann
I. INTRODUCTION WO major technological breakthroughs have enabled the enhancement of the performance and the energy efciency of sub-100-nm CMOS VLSI circuits [1], [2]. The rst one was the introduction of the strain engineering since the 90-nm technology node, which allowed for dramatically boosting the performance thanks to the higher channel mobility. The second one was the introduction of the high-k metal gate stack since the 45-nm technology node, which is highly benecial in terms of energy efciency thanks to the suppression of the gate leakage. In order to sustain the trends indicated by the ITRS roadmap, other technological breakthroughs are expected below the 22-nm technology generation. A possible technological solution is the use of high-mobility material as replacement of Si for the device channel. Germanium-based and III-V materials are currently under extensive investigation by the device community while the circuit and system community is waiting for response. Consequently, the results on high-mobility materials available in the literature focus on the device features and do not provide enough information on the suitability for VLSI implementations. Energy efciency issues are progressively pushing for more aggressive voltage scaling and ner granularity to improve performance-per-watt (e.g., laptop computers, portable media players) [3][5]. Clearly, the energy efciency benets most from ultra-dynamic voltage scaling (UDVS) when performance exhibits a low degradation under a given voltage reduction, whereas dynamic and leakage power exhibit a large reduction [6][8]. In particular, the performance/power reduction obtained with UDVS is strongly dependent on the adopted technology and the design approach at circuit and system level [9], [10]. This means that the assessment of emerging technologies as candidate replacements of Si devices for next-generation VLSI circuits must be carried out under the realistic scenario where UDVS and low-leakage techniques are extensively employed [11]. Recently the same authors proposed a novel evaluation methodology that aims to ll this gap between device characterization and VLSI systems by extracting circuit- and system-level features from pure on-wafer experimental measurements of a newly developed technology. This methodology was applied to Germanium pMOSFETs very recently [12]. This measurement-based methodology permits to perform an early assessment of the technology well before having a complete

AbstractIn this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the rst time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high- /metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe technology, an innovative technological solution is adopted that limits the SiGe material only to the channel region. The resulting SiGe device merges the higher speed of the Ge technology with the lower leakage of the Si technology. Appropriate circuit- and system-level metrics are introduced to identify the advantages offered by SiGe technology in VLSI circuits. Analysis is performed in the context of next-generation VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efciency through aggressive voltage scaling, other than low-leakage techniques. Analysis shows that the SiGe technology has more efcient leakage-delay and dynamic energy-delay trade-offs at nominal supply, compared to Si technology. Moreover, it is shown that the traditional analysis performed at nominal supply actually underestimates the benets of SiGe pMOSFETs, since the speed advantage of SiGe VLSI circuits is further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benet from aggressive voltage scaling signicantly more than Si circuits, thereby making SiGe devices a very promising alternative to Si transistors in next-generation VLSI systems.

Index TermsAggressive voltage scaling, digital circuits, emerging technologies, energy efciency, power-delay trade-off, Silicon-Germanium, VLSI.

Manuscript received July 06, 2010; revised February 02, 2011; accepted June 10, 2011. Date of publication July 22, 2011; date of current version June 14, 2012. F. Crupi is with the Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), Universit della Calabria, 87036 Rende, Italy. M. Alioto is with the Dipartimento di Ingegneria dellInformazione (DII), Universit di Siena, 53100 Siena, Italy, and also with the Berkeley Wireless Research Center, Electrical Engineering and Computer Science Department, University of California, Berkeley, CA 94704-1302 USA (e-mail: malioto@dii. unisi.it; alioto@eecs.berkeley.edu). J. Franco and G. Groeseneken are with the Interuniversity Microelectronics Center (IMEC), 3001 Leuven, Belgium, and also with the Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, 3001 Leuven, Belgium. P. Magnone is with the Advanced Research Center on Electronic Systems for Information and Communication Technologies E. De Castro (ARCES), Universit di Bologna, 40125 Bologna, Italy. B. Kaczer, J. Mitard, L. Witters, and T. Y. Hoffmann are with the Interuniversity Microelectronics Center (IMEC), 3001 Leuven, Belgium. Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TVLSI.2011.2159870

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design kit. This approach does not require 2-D/3-D device simulations, which are not well calibrated for semiconductors different from Si. Our analysis in [12] showed that although VLSI circuits with Ge pMOSFETs overcome their Si counterparts in terms of speed, some technological issues need to be solved especially for reducing the junction leakage. In this paper, we adopt and extend the above approach to buried SiGe channel pMOSFETs [13][18]. An interesting study on the potential advantages of SiGe devices for VLSI circuits based on theoretical simulations has been reported in [19]. However, experimental analysis of nanometer SiGe transistors would be more reliable and hence preferable to simulations, which are based on simplifying assumptions and do not account for process non-idealities. In this paper, the potential of SiGe technology for VLSI logic circuits is explored through an experimental evaluation at 45-nm technology generation. In particular, two main goals will be pursued. The rst is to understand the speed advantage offered by SiGe technology in the context of VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efciency (e.g., UDVS, power gating). The second purpose is to show that the SiGe technology offers an excellent leakage-delay trade-off, since it can merge the higher speed of the Ge technology with the lower leakage of the Si technology. This paper is structured as follows. SiGe pMOSFETs are reviewed in Section II, where details of the fabrication of the considered devices are provided. Various gures of merit for performance at circuit level are introduced in Section III to compare SiGe and Si technologies from a speed perspective. In Section IV, this performance improvement is traded off for lower power consumption, and the efciency of dynamic-energy delay and leakage-delay trade-off is analyzed under the adoption of aggressive voltage scaling. Finally, conclusions are drawn in Section V. II. ADOPTED SIGE TECHNOLOGY AND BASIC PROPERTIES OF SIGE PMOSFETS Devices were fabricated at IMEC using 300 mm (100) Si wafers. Fig. 1(a) and (b) shows the cross-sectional sketch and image of the nal device. A thin compressively strained layer is epitaxially grown onto a relaxed Si buffer. This strain effect is expected to be benecial for the mobility [20]. On top of this SiGe layer, a thin Si cap is grown. A detailed description of the epi-process can be found elsewhere [21], [22]. The Si cap is needed to avoid SiGe oxidation causing an increase of interface defects during gate stack fabrication which starts with a very thin wet chemical oxide. On top of this interfacial layer (IL), 2 nm of are deposited using atomic layer deposition (ALD). Finally a metal gate is deposited. Due to the valence band offset between the SiGe and the Si [see Fig. 1(c)] inversion channel holes are conned in the SiGe layer, which therefore behaves as a quantum well for holes. This causes the Si cap thickness to lower the inversion capacitance as compared to the accumulation capacitance. It is then necessary to report the capacitance-equivalent thickness in inversion , which was estimated to be 1.65 nm. Channel width and physical gate length were 90 and 45 nm, respectively.

Fig. 1. (a) Cross-sectional TEM image of SiGe pMOSFET. (b) Cross-sectional sketch. (c) Band diagram in inversion. Channel holes are conned in the SiGe quantum well due to valence band offset toward the Si layers. The Si cap additionally displaces channel holes, therefore lowering the inversion capacitance.

For comparison purposes, we characterized a second set of standard Si channel devices with identical dimensions and gate stack. was estimated as 1.31 nm for these devices. It is worth to emphasize that, although having the same gate stack, Si devices show a lower as compared to the of the SiGe channel devices: as mentioned above, this is due to the impact of the thin Si cap acting as an additional displacement for holes in the latter case. The device measurements were done at wafer-level using a semiconductor characterization system based on multiple Keithley 2602 instruments. For the typical investigated , the ITRS roadmap [1] indicates that the supply voltages are in the range 1.2 V based on the technology requirements (high-performance or low-power). In this work, we choose the intermediate value 1 V. The SiGe and Si devices have different threshold voltages, 0.147 V and 0.357 V, respectively, as found by applying the maximum transconductance method [23]. Since the threshold voltage in the SiGe process is not optimized and is signicantly different with respect to Si devices, in order to perform a fair comparison, we shifted the I-V curves in such a way to equalize the threshold voltages 0.33 V for both SiGe and Si devices.1 In Fig. 2 we report the drain current as a function of gate voltage overdrive measured in Si and SiGe pMOSFETs at (a) low and (b) high . The on-current achieved for 1 V and 667 mV for the Si (SiGe) device is 684 A m (705 A m), hence at rst glance the on-current advantage of SiGe devices is negligible. However, this result is not representative of practical cases, and a more
1For example, this can be easily done by adjusting the work function of the gate by selecting a proper metal or by inserting a cap layer between the high-k dielectric and the metal gate.

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TABLE I DEVICE PARAMETERS OF SiGe AND Si pMOSFETs

FIGURES

OF

TABLE II MERIT EXPRESSING THE ADVANTAGES OVER Si pMOSFETs

OF

SiGe

Fig. 2. Measured drain current versus gate voltage overdrive in Si and SiGe 50 mV and (b) at 1 V. The on-current impMOSFETs at (a) is strongly reduced at high . Si and SiGe provement observed at low pMOSFETs exhibit the same sub-threshold slope (see insets).

fair performance comparison will be presented in the next section. On the other hand, at low the SiGe on-current improvement is signicantly higher (1.41 ), and reaches 1.78 after normalizing by . This observation suggests a mobility enhancement up to about 80%. It is worth noting that the reduction of the speed advantage at higher voltages is a common property of all high-mobility materials. The physical reason is that at high longitudinal elds the carrier velocity tends to saturate and the speed advantage of high-mobility materials is signicantly reduced. In the following section we will show how the improvement in several speed gures of merit at circuit and system level is actually between the speed improvement at high voltages and that of low voltages. As highlighted in the insets of Fig. 2, SiGe devices exhibit the same sub-threshold slope (SS) values as Si pMOSFETs. It is important to underline that the SiGe pMOSFETs used in this work do not suffer from the high junction leakage of Ge devices reported in [12], thanks to the proposed architecture which limits the use of SiGe material only to the channel layer. Moreover, the drain-induced barrier lowering (DIBL) coefcients of the SiGe and Si technologies are very close as well (see Table I). Note that the slightly higher measured in SiGe pMOSFETs is simply because equalizing the extracted with the maximum transconductance method does not guarantee exactly the same in devices with the same SS, and also because of the strong dependence of on the . From a more pragmatic perspective, since the main leakage parameters (SS and DIBL coefcient) are almost equal for SiGe and Si devices, we conclude that the leakage in SiGe pMOSFETs is actually very similar to that of Si devices. These observations bring us to the conclusion that the proposed buried SiGe pMOSFETs merge the higher speed of the Ge technology with the lower leakage of the Si technology.

As a further advantage, we have recently reported that the proposed SiGe devices exhibit remarkably reduced negativebias temperature instability and lower 1/f noise with respect to their silicon counterparts [17], [18]. III. SPEED POTENTIAL OF VLSI CIRCUITS WITH SIGE PMOSFETS UNDER AGGRESSIVE VOLTAGE SCALING In this section, we evaluate the performance improvement offered by the SiGe pMOSFET for a reference inverter gate (see Section III-A) and for more complex logic gates containing stacked transistors (see Section III-B). In both cases, we assume that the load is dominated by the gate capacitance (i.e., the considered logic gate is driving nearby cells). All comparisons are performed by equalizing the threshold voltage 0.33 V and the supply voltage for both SiGe and Si technologies. The main results are summarized in Table II. A. Analysis of Reference Inverter Gate The speed benets brought by SiGe devices can be intuitively between grasped by inspecting Fig. 3, where the ratio the on-current and gate capacitance of SiGe normalized to the Si counterpart is plotted as a function of voltages and . The normalization of the drain current for the gate capacitance has been simply obtained by multiplying the drain current for the capacitance-equivalent thickness in inversion . From this gure the largest speed improvement (up to 1.91) is observed at low , whereas a signicantly smaller improvement (down to 1.28) is obtained at high . In the following, practical cases where a large

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Fig. 3. Ratio of between SiGe and Si pMOSFETs as a function of the and . The large speed improvement observed at bias voltages, (up to 1.91) is strongly reduced at high (down to 1.28). The speed low and high is due to differences improvement observed at low in the DIBL behavior.

benet can be achieved will be identied and discussed by introducing appropriate gures of merit. An extremely simple gure of merit expressing the speed advantage of SiGe over Si is (1) is dened as the MOSFET current where the on-current when . To better understand the impact of UDVS, the gure of merit in (1) obtained from experimental measurements was plotted in Fig. 4(a) versus . This gure clearly shows that is always greater than one and tends to increase at low voltages, i.e., SiGe circuits have a larger performance advantage when the supply voltage is aggressively scaled. In particular, the speed improvement in (1) is 1.30 at 1 V and 1.41 at 600 mV. It is worth emphasizing that since this speed improvement is a consequence of reducing the longitudinal electric eld (roughly proportional to ), it emerges when we reduce the supply bias for a xed channel length , as in the case of circuits which exploit UDVS techniques. On the other hand, this advantage does not apply to the case of the reduction associated with the technology (i.e., channel length) scaling, because in this case the longitudinal eld is almost the same. The gure of merit in (1) is based on the evaluation of the on-current at maximum voltage, hence it is not necessarily realistic since transistors actually experience large voltage variations during the output transition of a generic logic gate. As a more rigorous measure of speed, let us evaluate the inverter gate delay by using the actual on-current that is delivered by the transistor during the output transition. In particular, assuming that the load is dominated by the input capacitance of the subsequent logic gates, the load capacitance can be expressed as , being the input (gate) capacitance of a reference logic gate (e.g., a minimum inverter) and the equivalent number of driven transistors (it accounts for both the fan-out and the size of the transistors of the loading gates). By modeling the transistor as a current source delivering a current (being the current delivered by a

Fig. 4. Advantage of SiGe pMOSFETs with respect to Si devices in terms of for different (a) on-current, (b) delay time, and (c) rise time as a function of . In all cases, the speed improvement of SiGe numbers of stacked devices and with increasing . As expMOSFETs increases with decreasing is larger than , which is slightly larger than pected, .

minimum-sized transistor, and the driving strength of the considered cell), the gate delay can be expressed as

(2) To fairly compare a generic SiGe and Si logic gate, let us assume the same driving strength in (2), as well as the same fan-out and size of the loading gates (i.e., the same ). Hence, the resulting gure of merit that evaluates the speed advantage of SiGe over Si technology results to

(3) which is plotted in Fig. 4(b) versus . Observe that all parameters in (3) can be derived directly from device measurements, as required by our evaluation approach. As expected from the larger speed advantage of SiGe devices at lower , the value increases at lower supply voltage and is slightly higher than the corresponding value. In particular, SiGe technology offers a 1.3 speed advantage at 1 V and a 1.44 speed improvement at 600

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mV. This means that SiGe technology offers a signicant speed advantage at nominal , and its performance tends to experience a smaller degradation when is scaled down, compared to Si technology. This is a very nice feature of SiGe circuits in the context of next-generation VLSI systems with UDVS, and is again explained by the greater SiGe mobility enhancement at low longitudinal elds. As a further interesting aspect related to the performance of VLSI circuits that is traditionally neglected, let us compare the rise time of SiGe and Si inverters. This comparison gives information on the speed improvement in the output transition of a logic gate. For example, the rise time is very important in the case of local clock buffers (i.e., driving the clock of a clock domain), since their rise time denes the local clock slope, which strongly impacts the energy-delay trade-off in clock domains [24]. To comparatively evaluate the rise time of SiGe and Si circuits, let us resort to a procedure that is similar to that used to derive (3), which leads to the following gure of merit expressing the advantage of SiGe over Si (4) where it was considered that the transistor current determines the output transition from 10% to 90% of the supply voltage. for the reference tech(4) is plotted in Fig. 4(c) versus nologies. From this gure, the rise time benets from the adoption of SiGe technology even more than the gate delay. This can be intuitively explained by considering that the rise time is affected more by currents at low voltages, since the output voltages varies up to 90% of , instead of 50%. More quantitatively, SiGe technology exhibits a rise time improvement by 1.45 at 1 V, and an even better improvement is achieved at lower voltages, reaching a remarkable 1.56 at 600 mV. This means that in general SiGe inverters have signicantly sharper transitions compared to Si counterparts, other than having a faster response (i.e., lower delay). In turn, sharper output edges in SiGe circuits keep the delay of subsequent gates and their short-circuit power smaller, other than permitting to downsize buffers for a targeted signal slope (thereby reducing their dynamic and leakage consumption, which is benecial in the local distribution of the clock within a clock domain [24]). B. Extension to Complex Gates In general, transistor stacking in complex gates leads to a degradation of the on-current. Since the proposed SiGe pMOSFETs show the same leakage behavior (in terms of SS and DIBL) of their Si counterparts, the following comparative analysis is focused on the on-current degradation associated with the transistor stacking. Since stacked transistors were not available for direct measurements, we applied an appropriate numerical procedure which allows for extracting the bias point of the stacked transistors from measurements of as a function of , , and on a single pMOSFET [12]. As shown in Fig. 4(a), a signicantly lower degradation associated with the transistor stacking is observed in SiGe pMOSFETs. In particular, the speed improvement at 1 V is 1.30, 1.50,

and 1.62 for a number of stacked transistors 1, 2, and 3, respectively. This improvement is clearly a consequence of the reduction in when a larger number of stacked transistors is adopted. An even larger advantage is obtained by considering the joint effect of bias supply voltage reduction and transistor stacking. For example, the speed improvement reaches 1.70 at 600 mV and . As shown in Figs. 4(b) and (c), this advantage further increases if we consider the gures of merit and , instead of the simplistic gure of merit . For example, the reaches a remarkable 1.74 at 600 mV and , i.e., SiGe technology has a 74% speed improvement over Si technology. IV. ENERGY/POWER-DELAY TRADE-OFF IN SIGE VLSI CIRCUITS UNDER AGGRESSIVE VOLTAGE SCALING In Section III, it was shown that SiGe circuits exhibit a signicant speed advantage over Si circuits at same threshold voltage and supply voltage. In this section, this performance improvement is traded off for lower consumption, and SiGe and Si leakage are compared at iso performance in the context of systems with aggressive voltage scaling. The resulting advantage in terms of dynamic and leakage consumption is discussed in Sections IV-A and IV-B, respectively. The main results are summarized in Table II. A. Dynamic Energy-Delay Trade-Off and Voltage Scaling Let us consider the case where the performance improvement offered by SiGe technology is traded off for lower power consumption by reducing the SiGe supply voltage to achieve the same gate delay as the Si counterpart, assuming both technologies have the same threshold voltage as in Section III. The resulting supply voltage of the SiGe circuit leading to the same gate delay as the Si counterpart powered by voltage (i.e., such that ) is plotted in Fig. 5. As expected, from this gure the SiGe circuit voltage is typically 2030% lower than at same performance (slightly higher for circuits with a higher number of stacked transistors). More in detail, the SiGe voltage reduction tends to be smaller when is closer to the threshold voltage, since the delay becomes more sensitive to voltage reductions. The above discussed SiGe voltage reduction at iso-performance is clearly benecial in terms of dynamic energy. More specically, assuming again that the capacitance at the output of an inverter is dominated by the gate capacitance, the dynamic power can be expressed as . Similarly to the derivation of (3), let us adopt the gure of merit that expresses the dynamic power at iso-performance (or energy) advantage of SiGe compared to Si (5) where is the resulting supply voltage of the SiGe circuits matching the same delay as the Si counterpart powered with a supply . As shown in Fig. 6, SiGe technology allows a remarkable dynamic power saving that increases by increasing . More quantitatively, the dynamic energy is reduced by a factor 1.64 (1.71) at 600 mV and 1.98 (2.21)

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Fig. 5. Supply voltage of SiGe pMOSFETs required to match the gate delay of the Si counterpart as a function of supply voltage of Si pMOSFETs for dif. The SiGe supply voltage reduction ferent numbers of stacked devices increases when increasing and .

Fig. 7. Advantage of SiGe in terms of leakage power versus Si supply voltage (SiGe supply set to match performance).

merit that evaluates the leakage power reduction of SiGe over Si technology results to (6) Assuming the scenario where SiGe and Si devices have the same threshold as in Section III and the SiGe supply is scaled to match the Si performance (as discussed at the beginning of Section IV-A), the resulting gure of merit in (6) is plotted in Fig. 7. From this gure, SiGe technology allows for a considerable reduction of leakage power, which is even larger than the dynamic power saving and ranges from 1.65 to 3.36 when ranges from 600 mV to 1.2 V. This reduction is in part due to the leakage reduction resulting from the voltage reduction through the DIBL effect [i.e., the factor in (6)], and in part to the voltage reduction itself [i.e., the factor in (6)]. More specically, the ratio ranges from 1.45 to 2.55 (from 1.14 to 1.32), hence the leakage power reduction is mainly due to the leakage current reduction (thanks to DIBL effect) rather than the voltage reduction itself. Observe that the leakage power reduction in Fig. 7 increases by increasing for the same reasons that were discussed in the previous subsection. The above results permit to evaluate the intrinsic advantage in terms of leakage of SiGe technology in VLSI circuits, as no low-leakage technique was accounted for. However, practical applications always require the adoption of techniques to keep leakage under control. In particular power gating is the most popular technique, since it is effective and can be easily integrated in automated design ows [5]. In power gating schemes, a sleep transistor with high threshold is introduced to cut off a circuit from its power rail during the standby mode [5]. To compare the effectiveness of this technique in SiGe and Si circuits, we made two assumptions. First, the (higher) threshold of the sleep transistor was set so that the intrinsic leakage of the sleep transistor is lower than that of transistors within logic gates by a decade (i.e., the threshold voltage of the sleep transistor is increased by a value corresponding to the subthreshold slope in V/dec, as compared to transistors in logic gates with standard threshold). Second, the width of the sleep transistor was sized to keep its maximum voltage drop (which degrades the effective supply voltage seen by logic gates) in active mode to 5% of .

Fig. 6. Advantage of SiGe in terms of dynamic energy versus Si supply voltage (SiGe supply set to match performance) for different numbers of stacked devices .

at 1 V for . The stronger reduction at high supply voltages could appear contradictory to the higher improvement observed at lower supply voltage. However, this trend can be explained by considering again that the delay becomes more sensitive to voltage reductions when the voltage is reduced. Anyway, the above results clearly show that SiGe circuits benet from aggressive voltage scaling much more than Si counterparts, as . This considerable improvement in the energy efciency is highly benecial in todays and future systems-on-chip operating in a power limited regime [25]. As additional benet of the reduced supply voltage of SiGe circuits, a signicant improvement in their reliability is expected [17]. It is worth noting that a 4- to 6-fold reduction in the dynamic power of SiGe devices was reported in a previous study based on theoretical simulations [19]. This higher value could be ascribed to the higher bias voltage of 2.5 V used in [19]. B. Leakage-Delay Tradeoff and Voltage Scaling The reduced supply voltage enabled by SiGe circuits at iso-performance can also provide a signicant reduction in leakage power. In general, the leakage power in a technology is meaningfully expressed by where is the subthreshold leakage current of a minimum-sized inverter, evaluated at and . The resulting gure of

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Fig. 8. Leakage reduction when sleep transistors are used to drive 100 . inactive pMOSFETs as a function of the simultaneously active gates SiGe devices allow a larger leakage reduction (by a factor 1.4) with respect to their Si counterparts.

Clearly, the maximum voltage drop depends on the current that is drawn by the logic gates, which is in turn set by the maximum number of logic gates that switch simultaneously. Intuitively, power gating is expected to be more effective in SiGe circuits, as compared to Si counterparts. Indeed, SiGe sleep transistors have a signicantly greater driving capability compared to Si counterparts, especially considering that their source-drain voltage is quite low (a few percentage points of ). Hence, SiGe sleep transistors can be made smaller compared to Si counterparts under the same voltage drop requirement, thereby reducing the overall leakage. To achieve quantitative results, we assumed for simplicity that a sleep transistor is connected to 100 minimum-sized inverters (with width ). Then, we repeated the sleep transistor sizing and leakage calculations by progressively varying the number of simultaneously switching gates from 10 to 50. In each case, the procedure described in [12] was adopted to evaluate leakage. Analysis showed that must be 5.9 (8) times larger than to keep the voltage drop on the SiGe (Si) sleep transistor below the 5% of . The smaller area of SiGe sleep transistors is justied by the above qualitative considerations. The resulting leakage reduction offered by SiGe compared with Si technology is plotted in Fig. 8 versus . From this gure, power gating in SiGe circuits is more effective in reducing leakage by a factor 1.4 with respect to Si devices, and this advantage is basically independent of . This advantage adds up to the considerably lower intrinsic leakage power of SiGe technology that was discussed above. V. CONCLUSION AND REMARKS In this work, we have analyzed the potential of high-mobility Silicon-Germanium (SiGe) pMOSFETs from the perspective of VLSI logic circuits exploiting aggressive dynamic voltage scaling. The study is based on experimental measurements performed on 45-nm SiGe pMOSFETs with a high- /metal gate stack having capacitance-equivalent thickness in inversion of 1.65 nm and, for comparison purposes, also on 45-nm Si pMOSFETs with identical gate stack. Thanks to an innovative technological solution that limits the SiGe material only to the channel region, the proposed buried SiGe pMOSFETs exhibit the same leakage as their Si counterparts, thus overcoming the

main problem of conventional Ge pMOSFETs which suffer from excessively high junction leakage [12]. This study brings us to two main conclusions. The rst one is that by evaluating the speed performance at the maximum supply voltage, as is typically done in the early assessment of a new technology, the benets of SiGe pMOSFETs are strongly underestimated. Indeed, SiGe technology offers a 30% speed improvement at nominal voltage, and an even higher advantage at lower supply voltages (44% at 600 mV). Hence, SiGe VLSI circuits benet from ultra-dynamic voltage scaling much more than Si circuits. This is a key advantage from the perspective of next-generation VLSI systems with aggressive dynamic voltage scaling. It is worth noting that the higher speed advantage at lower voltages is a common property of all high-mobility materials. The reason is that at high longitudinal elds the carrier velocity tends to saturate and the speed advantages of high-mobility materials are signicantly reduced. Furthermore, SiGe buffers generate much sharper edges (by up to 56%), which is benecial from both the performance and consumption point of view (for example, this is very useful for local clock buffers). Interestingly, SiGe pMOSFETs show a lower on-current degradation when considering staked transistors. Therefore, an even larger advantage is obtained by considering the joint effect of bias supply voltage reduction and transistor stacking. For example, the speed improvement reaches 1.74 at 600 mV and . From a design perspective, this means that synthesis tools will tend to use high fan-in SiGe standard cells more frequently than Si technology. As a consequence, the composition of SiGe standard cell libraries is expected to be different from Si libraries, as higher fan-in cells must be included to take full advantage of the above feature. The more frequent adoption of high fan-in cells is well known to be advantageous from an energy efciency point of view [26]. The second conclusion is that SiGe technology offers a remarkably better power-delay trade-off for VLSI circuits with respect to their Si counterparts. In addition to the above-mentioned SiGe speed advantages obtained at similar leakage conditions, it was shown that SiGe technology exhibits a signicant power saving at iso-performance by appropriately reducing the SiGe supply voltage. For example, the dynamic (static) power saving is 1.98 (2.95 ) at 1 V. As a further interesting feature, leakage suppression through power gating with SiGe pMOSFETs is more effective than in Si circuits by a factor 1.4, as the former technology tends to reduce the size of sleep transistors under the same requirements. To our knowledge, the reported advantages of the buried SiGe pMOSFETs for VLSI logic circuits overcome the ones reported for other high-mobility technologies (like Ge technology), which suffer of excessive leakage penalty, thus suggesting that SiGe pMOSFET is a promising candidate for the next generations of CMOS VLSI circuits. REFERENCES
[1] International Technology Roadmap for Semiconductors, [Online]. Available: http://public.itrs.net [2] H.-S. P. Wong, Beyond the conventional transistor, IBM J. Res. Develop., vol. 46, no. 2/3, pp. 133168, 2002.

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[3] A. Chandrakasan, W. Bowhill, and F. E. Fox, Design of High-Performance Microprocessor Circuits. New York: IEEE Press, 2001. [4] A. Chandrakasan et al., Technologies for ultradynamic voltage scaling, Proc. IEEE, vol. 98, no. 2, pp. 191212, Feb. 2010. [5] S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies. New York: Springer, 2006. [6] B. Calhoun and A. Chandrakasan, Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering, IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 238245, Jan. 2006. [7] M. E. Sinangil, N. Verma, and A. Chandrakasan, A recongurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS, IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 31633173, Nov. 2009. [8] M.-E. Hwang, A. Raychowdhury;, K. Keejong, and K. Roy, A 8 FIR lter in 85 mV 40 nW process-tolerant subthreshold 8 130 nm technology, in Proc. IEEE Symp. VLSI Circuits, 2007, pp. 154155. [9] Z. Bo, D. Blaauw, D. Sylvester, and K. Flautner, Theoretical and practical limits of dynamic voltage scaling, in Proc. DAC, 2004, pp. 868873. [10] M.-E. Hwang, T. Cakici, and K. Roy, Process tolerant adaptive -ratio modulation for ultra-dynamic voltage scaling, in Proc. DATE, 2007, pp. 16. [11] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, Leakage-delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 2, pp. 232245, Feb. 2010. [12] P. Magnone, F. Crupi, M. Alioto, B. Kaczer, and B. De Jaeger, Understanding the potential and the limits of Germanium pMOSFETs for VLSI circuits from experimental measurements, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 10.1109/TVLSI.2010.2053226 . [13] N. Collaert, P. Verheyen, K. De Meyer, R. Loo, and M. Caymax, Highperformance strained Si/SiGe pMOS devices with multiple quantum wells, IEEE Trans. Nanotechnol., vol. 1, no. 4, pp. 190194, Dec. 2002. [14] N. Collaert, P. Verheyen, K. De Meyer, R. Loo, and M. Caymax, Inuence of the Ge-concentration and RTA on the device performance ofstrained Si/SiGe pMOS devices, in Proc. Eur. Solid-State Device Res. Conf., 2002, pp. 263266. [15] P. Majhi, P. Kalra, R. Harris, K. J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B. J. Cho, S. Banerjee, W. Tsai, H. Tseng, and R. Jammy, Demonstration of high-performance PMOSFETs using quantum wells with high- /metal-gate stacks, IEEE Electron Device Lett., vol. 29, no. 9, pp. 99101, Sep. 2008. [16] S. H. Lee, P. Majhi, J. Oh, B. Sassman, C. Young, A. Bowonder, W.-Y. Loh, K.-J. Choi, B.-J. Cho, H.-D. Lee, P. Kirsch, H. R. Harris, W. Tsai, S. Datta, H.-H. Tseng, S. K. Banerjee, and R. Jammy, Demonstration pMOSFETs with CHANNELS, of , and controlled Short Channel Effects HIGh (SCEs), IEEE Electron Device Lett., vol. 29, no. 9, pp. 10171020, Sep. 2008. [17] J. Franco, B. Kaczer, M. Cho, G. Eneman, and G. Groeseneken, Improvements of NBTI reliability in SiGe p-FETs, in Proc. Int. Reliab. Phys. Symp., 2010, pp. 10821085. [18] J. Franco, B. Kaczer, G. Eneman, J. Mitard, A. Stesmans, V. Afanasev, T. Kauerauf, P. J. Roussel, M. Toledano-Luque, M. Cho, R. Degraeve, T. Grasser, L.-. Ragnarsson, L. Witters, J. Tseng, S. Takeoka, W.-E. Wang, T. Y. Hoffmann, and G. Groeseneken, 6 EOT Si0.45Ge0.55 : Meeting the pMOSFET with optimized reliability NBTI lifetime target at ultra-thin EOT, in IEDM Tech. Dig., 2010, pp. 7073. [19] A. Sadek, K. Ismail, M. A. Armstrong, D. A. Antoniadis, and F. Stern, Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors, IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 12241232, Aug. 1996. [20] C. Claeys, E. Simoen, S. Put, G. Giusi, and F. Crupi, Impact strain engineering on gate stack quality and reliability, Solid-State Electron., vol. 52, pp. 11151126, 2008. [21] R. Loo, C. Walczyk, P. Verheyen, R. Rooyackers, F. E. Leys, G. Eneman, D. Shamiryan, P. P. Absil, T. Delande, A. Moussa, H. Bender, C. Drijbooms, L. Geenen, M. Caymax, J. W. Weijtmans, R. Wise, V. Machkaoutsan, P. Tomasini, C. Arena, J. McCormack, S. Passefort, H. Sorada, A. Inoue, B. C. Lee, S. Hyun, S. Jakschik, and S. Godny, Selective epitaxy of Si/SiGe to improve pMOS devices by recessed source/drain and/or buried SiGe channels, ECS Trans., vol. 3, no. 7, pp. 453465, 2006.

[22] A. Hikavyy, R. Loo, L. Witters, S. Takeoka, J. Geypen, B. Brijs, C. Merckling, M. Caymax, and J. Dekoster, SiGe SEG growth for buried channel p-MOS devices, ECS Trans., vol. 25, no. 7, pp. 201210, 2009. [23] D. K. Schroder, Semiconductor Material and Device Characterization. New York: Wiley, 1998. [24] M. Alioto, E. Consoli, and G. Palumbo, Flip-op energy/performance versus clock slope and impact on the clock network design, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 6, pp. 12731286, Jun. 2010. [25] B. Nikolic, Design in the power-limited scaling regime, IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 7183, Jan. 2008. [26] Low-Voltage/Low-Power Integrated Circuits and Systems, E. SnchezSinencio and A. G. Andreou, Eds. Piscataway, NJ: IEEE Press, 1999. Felice Crupi received the M.S. degree in electronic engineering from the University of Messina, Messina, Italy, in 1997 and the Ph.D. degree from the University of Firenze, Firenze, Italy, in 2001. Since 2002, he has been with the Dipartimento di Elettronica, Informatica e Sistemistica, Universit della Calabria, Rende, Italy, as an Associate Professor of electronics. Since 1998, he has been a repeat Visiting Scientist with the Interuniversity Micro-Electronics Center (IMEC), Leuven, Belgium. In 2000, he was a Visiting Scientist with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. His main research interests include reliability of CMOS devices, modeling and simulation of CMOS devices, electrical characterization techniques for solid state electronic devices, the design of ultra low noise electronic instrumentation and the design of extremely low power CMOS circuits. He has authored and coauthored over 70 papers published in peer-reviewed journals and over 50 papers published in international conference proceedings. His publications have been cited more than 700 times and his h-index is equal to 14 (Scopuss source). Prof. Crupi serves or served as a technical program committe member of the IEEE International Electron Devices Meeting (IEDM), and the IEEE International Reliability Physics Symposium (IRPS). He has been the Coordinator of international research projects in the eld of semiconductor devices and circuits. Massimo Alioto (M01SM07) was born in Brescia, Italy, in 1972. He received the Laurea degree in electronics engineering and the Ph.D. degree in electrical engineering from the University of Catania, Catania, Italy, in 1997 and 2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dellInformazione (DII), the University of Siena, Siena, Italy, as a Research Associate and in the same year as an Assistant Professor. In 2005, he was appointed Associate Professor of Electronics, and was engaged in the same faculty in 2006. In the summer of 2007, he was a Visiting Professor at EPFL, Lausanne, Switzerland. In 20092011, he held a Visiting Professor position with BWRC, UCBerkeley, Berkeley, CA, investigating on next-generation ultra-low power circuits and wireless nodes. In 2011, he also holds a Visiting Professor position with University of Michigan, investigating on technique for resiliency in near-threshold processors and ultra-low power circuits. Since 2001 he has been teaching undergraduate and graduate courses on advanced VLSI digital design, microelectronics and basic electronics. He has authored or co-authored 170 publications on journals (60, mostly IEEE Transactions) and conference proceedings. Two of them are among the most downloaded TVLSI papers in 2007 (respectively, 10th and 13th). He is co-author of the book Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include ultra-low power VLSI circuits and wireless nodes, sub- W cryptographic circuits, ultra-low standby power SRAMs, highly efcient on-chip power converters for sub- W operation, modeling/design of variability-tolerant low-leakage VLSI CMOS circuits, circuit techniques for emerging technologies. He is the director of the Electronics Lab at University of Siena (site of Arezzo). Prof. Alioto is a member of the HiPEAC Network of Excellence. He is the Chair of the VLSI Systems and Applications Technical Committee of the IEEE Circuits and Systems Society, for which he was also Distinguished Lecturer in 2009-2010 and member of the DLP Coordinating Committee in 20112012. He is regularly invited to give talks and tutorials to academic institutions, conferences, and companies throughout the world. He serves or

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has served as a member of various conference technical program committees (ISCAS, ICCD, PATMOS, ICM, ECCTD, CSIE) and Track Chair (ISCAS, ICCD, ICECS, ICM). He was Technical Program Chair of the conference ICM 2010. He serves as Associate Editor of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, as well as of the Microelectronics Journal, the IntegrationThe VLSI journal, the Journal of Circuits, Systems, and Computers, the Journal of Low Power Electronics and Applications and the ACM Transactions on Design Automation of Electronic Systems. He was Guest Editor of the Special Issue Advances in Oscillator Analysis and Design of the Journal of Circuits, Systems, and Computers (2010), and Technical Program Chair for the ICM 2010 Conference.

Jacopo Franco received the B.Sc. and M.Sc. degrees in electronic engineering from the University of Calabria, Calabria, Italy, in 2005 and 2008, respectively. He is currently pursuing the Ph.D. degree in the reliability group of imec and at the Katholieke Universiteit Leuven, Leuven, Belgium, on the topic Interface stability and reliability of Ge and III-V transistors for future CMOS applications. His M.Sc. thesis was developed at imec, Leuven, Belgium, and it is related to reliability issues in advanced Silicon and Germanium MOSFETs. He has authored or co-authored over 30 publications. Mr. Franco was a recipient of the IEEE SISC Ed Nicollian Award for the Best Student Paper in 2009.

Guido Groeseneken (F05) received the M.Sc. degree and the Ph.D. degree in applied sciences from the KU Leuven, Belgium, in 1980 and 1986, respectively. In 1987, he joined the R&D Laboratory, IMEC, Leuven, Belgium. He is responsible for research in reliability physics for deep submicrometer CMOS technologies and in nanotechnology for post-CMOS applications. From October 2005 until April 2007, he was responsible for the Post CMOS Nanotechnology program within IMECs core partner research program. Since 2001, he is a Professor with the KU Leuven, where he is Program Director of the Master in Nanoscience and Nanotechnology and coordinating a European Erasmus Mundus Master Program in nanoscience and nanotechnology. He has made contributions to the elds of non-volatile semiconductor memory devices and technology, reliability physics of VLSI-technology, hot carrier effects in MOSFETs, time-dependent dielectric breakdown of oxides, Negative-Bias-Temperature Instability effects, ESD-protection and -testing, plasma processing induced damage, electrical characterization of semiconductors and characterization and reliability of high k dielectrics. Recently he has also interest in such as carbon nanotubes for interconnect applications, tunnel FETs for alternative nanowire devices, etc. Dr. Groeseneken became an IMEC Fellow in 2007. He has served as a technical program committee member of several international scientic conferences, such as IEDM, ESSDERC, IRPS, SISC, and EOS/ESD Symposium. He has authored or co-authored over 500 publications in international scientic journals and in international conference proceedings, 6 book chapters, and 10 patents in his elds of expertise. Jrme Mitard received the Ph.D. degree in microelectronic engineering from the Polytechnic University School of Marseille, Marseille, France, in 2003. For three years, he acted as an STMicroelectronics assignee with Commissariat Energie AtomiqueLaboratoire dlectronique et de technologie de linformation, Grenoble, France, where he was deeply involved in the electrical characterization of hafnium-based dielectrics with metal gate for sub-70-nm complementary metaloxidesemiconductor (CMOS) technologies. After his Ph.D. in microelectronics at Micro and Nanotechnologies Campus Center, Grenoble, France, he joined the Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium, as a device researcher, where he is currently working on the integration of high-mobility substrates for the sub-22-nm CMOS node. Liesbeth Witters received the B.Sc. and M.Sc. degrees in chemical engineering from Katholieke Universiteit Leuven, Leuven, Belgium and ENSPM, Paris, France in 1992 and 1993, respectively. From 1994 to 1995, she did graduate research work at the Civil Engineering Department, University of California, Irvine. In 1995, she joined Rockwell Semiconductor Systems, later Conexant, in Newport Beach, CA, where she worked as a CMP Process Development Engineer. In 2001, she joined IMEC, Leuven, Belgium, as a BiCMOS Process Integration Engineer. Since 2004 she has been working on different applications in the CMOS Process Integration Department. Thomas Y. Hoffmann received the Ph.D. degree from Lille University, Villeneuve dAscq, Lille, France, in 2000. He joined Intel Corporations Research and Development Group, Hillsboro, OR, as a Technology Computer-Aided Design Engineer for sub-90-nm technologies. In 2004, he moved to Intels Technology Development Group as a Device Engineer for 45-nm process development. In 2005, he joined Interuniversity Microelectronics Center, Leuven, Belgium, to lead the electrical characterization group for advanced silicon technologies. In 2009, he became the Director of the Front-End-of-Line Logic and Dynamic Random Access Memory Devices Research Program. He has authored or coauthored approximately 50 technical papers for publication in journals and presentations at conferences.

Paolo Magnone received the B.S. and M.S. degrees in electronic engineering from the University of Calabria, Rende, Italy, in 2003 and 2005, respectively, and the Ph.D. degree in electronic engineering from the University of Reggio Calabria, Italy, in 2009. In the period 20062008, he joined for one year the Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium, within the Advanced PROcess Technologies for Horizontal Integration Project (Marie Curie Actions), where he worked on parameters extraction and matching analysis of FinFET devices. He was a Postdoctoral Researcher with the University of Calabria from 2009 to 2010. He is currently with the ARCES Center, University of Bologna. His research interests include the electrical characterization, electrothermal simulation and modeling of semiconductor devices, and the numerical simulation of photovoltaic silicon solar cells.

Ben Kaczer received the M.S. degree in physical electronics from Charles University, Prague, Czech Republic, in 1992 and the M.S. and Ph.D. degrees in physics from The Ohio State University, Columbus, in 1996 and 1998, respectively. He is a Senior Reliability Scientist with IMEC, Leuven, Belgium. In 1998, he joined the reliability group of IMEC, Leuven, Belgium, where his activities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric lms, planar and multiple-gate FETs, circuits, and characterization of Ge/III-V and MIM devices. He has authored or co-authored over 250 journal and conference papers. Dr. Kaczer received the OSU Presidential Fellowship and support from Texas Instruments, Inc. for his Ph.D. research on the ballistic-electron emission microscopy of SiO2 and SiC lms. He was a recipient of three Best and one Outstanding Paper Awards at IRPS and the Best Paper Award at IPFA. He has presented invited papers and tutorials at several international conferences. He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, and WoDiM Conferences. He is currently serving on the IEEE T. Electron Dev. Editorial Board.