Rungta College of Engineering and Technology, Bhilai

Department of Electronics and Telecommunication Engineering

Course File (Theory + Lab)

Name of Subject Subject Code Semester Section Discipline Academic Year

Digital Electronic Circuits 328414(28) [T], 328422(28) [P] 4th A Electronics and Telecommunication 2012-2013

Name of ProfessorProf. Heena Parveen, Lecturer, Department of Electronics and Telecommunication Engineering,

Contact No. & Mail IdContact No. 0788-6666666 (O) heenaparveen08@gmail.com

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

Department of Electronics and Telecommunication Engineering

1. Programe Education Objectives (PEOs)I.

II.

III.

The Graduates of the programe will have Strong foundation in mathematics, basic sciences and engineering fundamentals to successfully compete for various entry level positions or pursue higher studies in Electronics Engineering and/or allied fields. The Graduates of the programe will have contemporary knowledge and lifelong learning skill, familiarity with modern hardware and software tools and practices in Electronics and related domain. The Graduates of the programe will possess the required skills to perceive successively the engineering profession including communication skill, working efficiently in multidisciplinary teams, understanding of ethical and environmental issues.

2. Programe Outcomes (POs)

An ability to apply knowledge of Mathematics, Science, and Engineering. An ability to design and conduct experiments as well as analyze and interpret data. An ability to design a system, component, or process to meet desired needs. An ability to function on multidisciplinary teams. An ability to identify, formulates, and solves engineering problems. An understanding of professional and ethical responsibility. An ability to communicate effectively. The broad education necessary to understand the impact of engineering solutions in a global/social context i) A recognition of the need for and an ability to engage in life-long learning j) Knowledge of contemporary issues. k) An ability to use the techniques, skills and modern engineering tools necessary for engineering practice. a) b) c) d) e) f) g) h)

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

Course Syllabus
UNIT I: CODES Binary codes: Introduction & usefulness, Weighted & Non-weighted codes, Sequential codes, self complementing codes, Cyclic codes, 8-4-2-1 BCD code, Excess-3 code, Gray code: Binary to Gray and Gray to binary code conversion, Error detecting code, Error correcting code, 7-bit Hamming code, ASCII code, EBCDIC code. Realization of Boolean Expressions: Reduction of Boolean expressions using laws, theorems and axioms of Boolean Algebra, Boolean expressions and logic diagram, Converting AND/OR/Invert logic to NAND/NOR logic, SOP and POS Forms and their Realization.

UNITII: MINIMIZATION TECHNIQUES Expansion of a Boolean expression to SOP form, Expansion of a Boolean expression to POS form, Two, Three & Four variable K-Map: Mapping and minimization of SOP and POS expressions. Completely and Incompletely Specified Functions - Concept of Don't Care Terms, Quine Mc Clusky Method.

UNIT-III: COMBINATIONAL CIRCUITS Adder & Subtractor: Half adder, Full adder, half Subtractor, Full Subtractor, Parallel Binary adder, Look Ahead carry adder, Serial adder, BCD adder. Code converter, Parity bit generator/Checker, Comparator. Decoder: 3-line to 8-line decoder, 8-4-2-1 BCD to Decimal decoder, BCD to Seven segment decoder. Encoder: Octal to binary and Decimal to BCD encoder. Multiplexer: 2-input multiplexer, 4-input multiplexer, 16-input multiplexer. Demultiplexer: 1-line to 4-line & 1-line to 8-line de-multiplexer, Multiplexer as Universal Logic Function Generator, Programmed Array Logic (PAL), PLA and PLD.

UNITIV: SEQUENTIAL CIRCUITS Flip-Flops & Timing Circuit: S-R Latch; Gated S-R Latch; D Latch; J-K flip-Flop; T Flip-Flip: Edge Triggered SR, D, J-K and T Flips-Flops; Master - Slave Flip-Flops; Direct Preset and Clear Inputs. Shift Registers: PIPO, SIPO, PISO, SISO, Bi-Directional Shift Registers; Universal Shift register. Counter: Asynchronous Counter: Ripple Counters; Design of asynchronous counters, Effects of propagation delay in Ripple counters, Synchronous Counters: 4-bit synchronous up counter, 4-bit synchronous down counter, Design of synchronous counters, Ring counter, Johnson counter, Pulse train generators using counter, Design of Sequence Generators; Digital Clock using Counters.

UNITV: DIGITAL LOGIC FAMILIES Introduction : Simple Diode Gating and Transistor Inverter; Basic Concepts of RTL and DTL; TTL: Open collector gates, TTL subfamilies, IIL, ECL; MOS Logic: CMOS Logic, Dynamic MOS Logic, Interfacing: TTL to ECL, ECL to TTL, TTL to CMOS, CMOS to TTL, Comparison among various logic families, Manufacturers specification.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

Textbook Recommended: 1. Digital Logic and Computer Design M. Morris Mano. 2. Fundamentals of Digital Circuits A. Anand Kumar, PHI Reference Book Recommended: 1. Digital Fundamentals: Floyd & Jain, Pearson Education.

2. Digital Circuits & Design- Salivahanan, Vikas Publication.

Digital Electronic Circuits (Lab) - 328422(28)

List of Experiments to be performed
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. To Verify The Properties of NOR & NAND Gates As Universal Building Block. Realization of Boolean Expression Using NAND Or NOR Gates. To Construct X- OR Gate Using Only NAND Or NOR Gates Only. To Construct A Half Adder Circuit. And Logic Gates And Verify its Truth table. To Construct A Full Adder Circuit. And Verify its truth table (Using Two X-OR And 3 NAND Gates). To Construct A Half Subtractor Circuit. By Using Basic Gates And Verify its truth table. To Construct a Full Subtractor Circuit by Using Basic Gates and Verify its truth table. To Construct A Circuit of 4 -Bit Parity Checker & Verify its truth table. To Design a Comparator Circuit & Verify its truth table. To Construct A RS Flip Flop Using Basic & Universal Gates (NOT,NOR & NAND). To Verify The Operation of A Clocked S-R Flip Flop And J. K. Flip Flop. To Construct a T & D Flip Flop Using J K.Flip Flop and Verify Its Operations & truth table. To Verify The Operation of A Synchronous Decade Counter.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

Time TableClass Schedule (3L+1T+4P)Days/Periods Monday Tuesday Wednesday Thursday Friday Saturday 1 (9:40 10:30) 2 (10:30 11:20) 3 (11:40 12:30) P L T L L P P P T 4 (12:30 01:20) 5 (02:00 02:50) 6 (02:50 03:40) 7 (03:40 04:30)

L- Lecture

T- Tutorial

P- Practical

i)

Course Educational Objective- The Course Educational Objectives are:

(1) The students of the programme will have contemporary knowledge about Digital Electronics and lifelong learning skills familiarity with modern hardware and software tools and practices used in Electronics and Telecommunication related domain. (2) The students of the programme will get knowledge about Digital Electronics and the required interfacing skills in embedded systems and working efficiently in multidisciplinary teams for its applications in various fields.

ii) Once the student has successfully complete this course, he/she will be able to answer the following questions or perform following activities: The Course Outcomes are: (a) An ability to apply the basic knowledge of science and Digital Electronics in Electronics and Telecommunication Engineering. (b) An ability to design and conduct experiments, as well as to analyze and interpret data with the help of Digital Electronics. (c) An ability to design a system, component or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability and sustainability of Telecommunication Engineering. (d) An ability to function on multidisciplinary teams. (k) An ability to use the techniques, skills and modern engineering tools necessary for engineering practice.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

iii) Mapping of Course Objectives and Course Outcomes: Course Educational Objectives a
I II X X X X

Course Outcomes b c d k
X X

iv) Mapping of Course Contents with Course Education Objective (CEOs) and Course Outcomes (COs): Unit No. I Unit 1 Unit 2 Unit 3 Unit 4 Unit 5 v) Adopted Grading System: Modes Mid Term Exam Pre-Semester Exam Assignment Teacher Assessment Percentage Covered 40% 40% 10% 10% Date of Performance 18.02.13 20.02.13 12.04.13 18.04.13
X X X X X

CEOs II
X X X

Course Outcomes a
X X X X X

b
X X X

k
X

X X

X X

X X X

Note- All the examinations are compulsory. The homework is scheduled to be due on the specified dates. No homework will be accepted after the due date.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

vi) Instructional Schedule (Lecture): Instructional Schedule (Lecture) Subject- Digital Electronic Circuits Code- 328414 (28) Semester 4th Discipline- Electronics & Telecommunication S. No. Lecture No. Date of Topic to be Covered Delivery
UNIT-1 : CODES

Remarks if any

1 2 3 4 5 6

1 2 3 4 5 6

02/01/13 04/01/13 05/01/13 09/01/13 11/01/13 12/01/13

Introduction & usefulness, Types of codes Types of codes Gray code : Binary to Gray & Gray to Binary code conversion Error Detecting Code, error correcting code (7-bit hamming code) Realization of expressions, Boolean expressions & Logic diagram Converting AND/OR/INVERT logic to NAND/NOR logic SOP & POS forms and their realization
UNIT-2 : MINIMIZATION TECHNIQUES

7 8 9 10 11 12 13 14

7 8 9 10 11 12 15 14

16/01/13 18/01/13 19/01/13 23/01/13 25/01/13 30/01/13 01/02/13 02/02/13

Topic related to Lab Experiment No. 1, 2 and 3 Assignment 1 due

Expansion of a Boolean expression to SOP form & POS form K-map K-map Concept of dont care terms Quine Mc-Clusky method Quine Mc-Clusky method
UNIT-3 : COMBINATIONAL CIRCUITS

Assignment 2 due Topic related to Lab Experiment No. 4, 5, 6 and 7

Adder & Subtractor

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

06/02/13 08/02/13 09/02/13 13/02/13 15/02/13 16/02/13 20/02/13 22/02/13 23/02/13 27/02/13 01/03/13 02/03/13 06/03/13 08/03/13 09/03/13

Adder & Subtractor, Parallel binary adder Look ahead carry adder Serial adder BCD adder Code converter Parity bit generator/checker, Comparator Decoder & Encoder Multiplexer De-multiplexer PLD PLD
UNIT-4 : SEQUENTIAL CIRCUITS

Topic related to Lab Experiment No. 8 and 9

Assignment 3 due

Latch Flip-flop types Flip-flop types Flip-flop types

Topic related to Lab Experiment No. 10, 11 and 12

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

Instructional Schedule (Lecture) Subject- Digital Electronic Circuits Code- 328414 (28) Semester 4th Discipline- Electronics & Telecommunication S. No. Lecture No. Date of Topic to be Covered Delivery 30 30 13/03/13 Shift registers & its types 31 31 15/03/13 Types of shift registers 32 32 16/03/13 Asynchronous counter & its design 33 33 20/03/13 Asynchronous counter & its design 34 34 22/03/13 Synchronous counter & its design 35 36 37 38 39 40 41 35 36 37 38 39 40 41 23/03/13 29/03/13 30/03/13 03/04/13 05/04/13 06/04/13 10/04/13 Ring & Johnson counter Design of sequence generators UNIT-5 : DIGITAL LOGIC FAMILIES Introduction, Fabrication & packaging process of digital ICs. RTL,DTL TTL, TTL subfamilies IIL, ECL MOS Logic, Interfacing

Remarks if any

Topic related to Lab Experiment No. 13 Assignment 4 due Topic Beyond Syllabus

Assignment 5 due

vii) Instructional Schedule (Tutorial): Instructional Schedule (Tutorial) Subject- Digital Electronic Circuits Code- 328414 (28) Semester 4th Discipline- Electronics & Telecommunication S. No. Date of Date of Topic to be Covered Delivery Delivery (Batch 1) (Batch 2) 1 02/01/13 03/01/13 Numerical + Doubt Clearing 2 09/01/13 10/01/13 Numerical + Doubt Clearing 3 16/01/13 17/01/13 Solving Previous Year Question Papers 4 23/01/13 24/01/13 Numerical + Doubt Clearing 5 30/01/13 31/01/13 Numerical + Doubt Clearing 6 06/02/13 07/02/13 Solving Previous Year Question Papers 7 13/02/13 14/02/13 Numerical + Doubt Clearing 8 20/02/13 21/02/13 Numerical + Doubt Clearing 9 27/02/13 28/02/13 Solving Previous Year Question Papers 10 06/03/13 07/03/13 Numerical + Doubt Clearing 11 13/03/13 14/03/13 Numerical + Doubt Clearing 12 20/03/13 21/03/13 Solving Previous Year Question Papers 13 03/04/13 28/03/13 Numerical + Doubt Clearing 14 10/04/13 04/04/13 Solving Previous Year Question Papers

Remarks if any

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

Asignment addressing POs, and Blooms Taxonomy Level: S. No Assignment No. 1 Remarks PO addressed Blooms Taxonomy Level

1.

Questions related to codes, Boolean Algebra and Boolean expression realization

a, b, k

2.

Questions related to Minimization Techniques Questions related to designing of combinational circuits

3.

a, b, c, d, k

4.

Questions related to flip flop and counters

a, b, c, k

5.

Questions related to functioning of different ICs and comparison among them

a, d, k

Cognitive Domain- Leve1, Level-2,Level-3 (Remember, Understanding, Application) Cognitive Domain-Level2,Level-3 (Understanding, Application) Cognitive Domain- Level1, Level-2,Level-5 (Remember, Understanding, Creativity) Cognitive Domain- Level1, Level-2,Level-5 (Remember, Understanding, Creativity) Cognitive Domain- Level1, Level-2,Level-4, Level5 (Remember, Understanding, Analysis, Creativity)

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

viii) Instructional Schedule (Laboratory): INSTRUCTIONAL SCHEDULE (PRACTICAL) Subject- Digital Electronic Circuits Lab Code- 328422 (28) Semester 4th Discipline- Electronics & Telecommunication S. No. Experiment Date of Experiment Experiment to be Performed No. Batch I Batch II
1 1 02/01/13 03/01/13 To Verify The Properties of NOR & NAND Gates As Universal Building Block. Realization of Boolean Expression Using NAND Or NOR Gates. To Construct X- OR Gate Using Only NAND Or NOR Gates Only. To Construct A Half Adder Circuit. And Logic Gates And Verify its Truth table. To Construct A Full Adder Circuit. And Verify its truth table (Using Two X-OR And 3 NAND Gates). To Construct A Half Subtractor Circuit. By Using Basic Gates And Verify its truth table. To Construct a Full Subtractor Circuit by Using Basic Gates and Verify its truth table. To Construct A Circuit of 4 -Bit Parity Checker & Verify its truth table. To Design a Comparator Circuit & Verify its truth table. To Construct A RS Flip Flop Using Basic & Universal Gates (NOT, NOR & NAND). To Verify The Operation of A Clocked S-R Flip Flop And J. K. Flip Flop. To Construct a T & D Flip Flop Using J K Flip Flop and Verify Its Operations & truth table. To Verify The Operation of A Synchronous Decade Counter.

Remarks if any
Related to Unit-1

Related to Unit-1

05/01/13

08/01/13

Related to Unit-1

09/01/13

10/01/13

Related to Unit-3

12/01/13

15/01/13

Related to Unit-3

16/01/13

17/01/13

Related to Unit-3

19/01/13

22/01/13

Related to Unit-3

23/01/13

24/01/13

Related to Unit-3

29/01/13

30/01/13

Related to Unit-3

31/01/13

02/02/13

Related to Unit-4

10

10

05/02/13

06/02/13

Related to Unit-4

11

11

07/02/13

09/02/13

Related to Unit-4

12

12

12/02/13

13/02/13

Related to Unit-4

13

13

14/02/13

16/02/13

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

ix) Mapping of Course Educational Objectives and Course Outcomes for Laboratory Experiments:

Experiment No. 1

Experiment to be performed

To Verify The Properties of NOR & NAND Gates As Universal Building Block. Realization of Boolean Expression Using NAND Or NOR Gates. To Construct X- OR Gate Using Only NAND Or NOR Gates Only. To Construct A Half Adder Circuit. And Logic Gates And Verify its Truth table. To Construct A Full Adder Circuit. And Verify its truth table (Using Two X-OR And 3 NAND Gates). To Construct A Half Subtractor Circuit. By Using Basic Gates And Verify its truth table. To Construct a Full Subtractor Circuit by Using Basic Gates and Verify its truth table. To Construct A Circuit of 4 -Bit Parity Checker & Verify its truth table. To Design a Comparator Circuit & Verify its truth table. To Construct A RS Flip Flop Using Basic & Universal Gates (NOT, NOR & NAND). To Verify The Operation of A Clocked S-R Flip Flop And J. K. Flip Flop. To Construct a T & D Flip Flop Using J K Flip Flop and Verify Its Operations & truth table. To Verify The Operation of A Synchronous Decade Counter.

CEOs Covered I II X X X X X X X X

COs Achieved a X X X X X b X X X X X X X c X X d k X

X X X X X X X X X X X

X X X X X X X X

X X X X X X X X X X X X

X X

10

11

12

13

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

x) Teaching plan (Unit Wise):

UNIT PLAN UNIT : 1 UNIT CONTENTS: Binary codes: Introduction & usefulness, Weighted & Non-weighted codes, Sequential codes, self complementing codes, Cyclic codes, 8-4-2-1 BCD code, Excess-3 code, Gray code: Binary to Gray and Gray to binary code conversion, Error detecting code, Error correcting code, 7-bit Hamming code, ASCII code, EBCDIC code. Realization of Boolean Expressions: Reduction of Boolean expressions using laws, theorems and axioms of Boolean Algebra, Boolean expressions and logic diagram, Converting AND/OR/Invert logic to NAND/NOR logic, SOP and POS Forms and their Realization. Unit Objectives: Broad Objectives of the unit are: 1. Gaining Knowledge about the Codes 2. Code Conversion 3. Boolean Algebra & realization of Boolean Expression 4. SOP & POS form By fulfilling the objective the student will satisfy POs (a), (b) and (k) and first three levels of Blooms Taxonomy Cognitive Domain i.e. Remember, Understand and Application. Once the student has completed this unit he/she will be able to answer following questions/perform the following activities: 1. Different types of codes used in digital circuits & their conversions. 2. Difference between Ordinary Algebra & Boolean Algebra. 3. Employ Boolean algebra to describe the function of logic circuits. 4. Circuits from Boolean Expressions. With the above POs (a), (b) and (k) is expected to be achieved. Methodology: This unit will be taught by providing basic the information regarding digital electronics which includes its introduction, various binary codes and Boolean algebra. Related laboratory experiments as per the curriculum To Verify The Properties of NOR & NAND Gates As Universal Building Block. Realization of Boolean Expression Using NAND Or NOR Gates. To Construct X- OR Gate Using Only NAND Or NOR Gates Only.
Assignment 1:

1. 2. 3. 1.

Simplify the Boolean Expressions and draw the logic diagram: xyz + xyz + xyz + xyz + xyz+ xyz + xyz 2. Explain with examples how hamming code is useful for detecting and correcting errors in digital communication system. 3. Explain and state principle of duality. 4. Implement the following function by using only NOR gate. F = a(b + cd)+ bc 5. Using Boolean Algebra, show that AB+ABD+ABD+(ACD)+ABC=(A+BC)+CD The above assignment is designed to address PO (a), (b) and (k) and level (1), (2) and (3) of Blooms Taxonomy of Cognitive
Domain

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

UNIT PLAN UNIT : 2 UNIT CONTENTS: Expansion of a Boolean expression to SOP form, Expansion of a Boolean expression to POS form, Two, Three & Four variable K-Map: Mapping and minimization of SOP and POS expressions. Completely and Incompletely Specified Functions - Concept of Don't Care Terms, Quine Mc Clusky Method. Unit Objectives: Broad Objectives of the unit are: 1. Expansion of Boolean Expression to SOP & POS form 2. Minimization Using K-Maps & Quine Mc Clusky Method 3. Incompletely Specified Functions By fulfilling the objective the student will satisfy PO (a) and two levels of Blooms Taxonomy Cognitive Domain i.e. Understand and Application. Once the student has completed this unit he/she will be able to answer following questions/perform the following activities: 1. Understand the minimization techniques of Boolean Expression 2. Solve questions on K-Map and Quine Mc-Clusky method With the above PO (a) is expected to be achieved Methodology: This unit will be covered by explaining how Boolean functions can be simplified in order to achieve economical gate implementations. Related laboratory experiments as per the curriculum No laboratory experiments.
Assignment 2:

Minimize the logic function by using K-map. Y= M (0,1,3,5,6,7,10,14,15) 3. Why is it essential to use minimization techniques before designing any digital circuit? Differentiate between expansion in SOP form and POS form. 4. Reduce the following function using K-map. F=m(1,5,6,12,13,14)+d(2,4) 5. Using the Quine Mc-Clusky method, solve the following functions. F(w,x,y,z)=m(0,1,5,7,8,10,14,15) F(A,B,C,D)=m(0,2,3,6,7,8,9,10,13) 6. (a) Differentiate between combinational and sequential circuits. (b) Simplify the expression. F=xy+xy+xy The above assignment is designed to address PO (a) and level (2) and (3) of Blooms Taxonomy of Cognitive Domain.

1.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

UNIT PLAN UNIT : 3 UNIT CONTENTS: Adder & Subtractor: Half adder, Full adder, half Subtractor, Full Subtractor, Parallel Binary adder, Look Ahead carry adder, Serial adder, BCD adder. Code converter, Parity bit generator/Checker, Comparator. Decoder: 3-line to 8-line decoder, 8-4-2-1 BCD to Decimal decoder, BCD to Seven segment decoder. Encoder: Octal to binary and Decimal to BCD encoder. Multiplexer: 2-input multiplexer, 4-input multiplexer, 16-input multiplexer Demultiplexer: 1-line to 4-line & 1-line to 8-line de-multiplexer, Multiplexer as Universal Logic Function Generator, Programmed Array Logic (PAL), PLA and PLD. Unit Objectives: Broad Objectives of the unit are: 1. Adder & Subtractor 2. Parity bit generator/Checker 3. Comparator 4. Decoder & Encoder 5. Multiplexer & De-multiplexer 6. Knowledge of Programmable Logic Devices By fulfilling the objective the student will satisfy POs (a), (b), (c), (d) and (k) and three levels of Blooms Taxonomy Cognitive Domain i.e. Remember, Understand and Creativity. Once the student has completed this unit he/she will be able to answer following questions/perform the following activities: 1. Designing combinational logic circuits. 2. Implementation of combinational circuits using decoders, Multiplexers and PLA. 3. Understand the function of PLDs. With the above POs (a), (b), (c), (d) and (k) is expected to be achieved Methodology: This unit will utilize the concept built in previous units and formulate various systematic designs and procedural analysis of combinational circuits. PLDs and their usefulness in the design of complex combinational circuits will also be discussed. Related laboratory experiments as per the curriculum 1. 2. 3. 4. To construct and verify Half Adder and Full Adder Circuit with its truth table. To construct and verify Half Subtractor and Full Subtractor Circuit with its truth table. To Construct A Circuit of 4 -Bit Parity Checker & Verify its truth table. To Design a Comparator Circuit & Verify its truth table.
Assignment 3:

Design a 4-bit BCD adder. Design a 4-bit comparator circuit. Construct a 4x16 decoder using 3x8decoder. Describer operation of PLA. Explain the operation of 4-bit carry look ahead adder circuit. What are its merits? The above assignment is designed to address PO (a), (b), (c), (d) and (k) and level (1), (2) and (5) of Blooms Taxonomy
of Cognitive Domain.

1. 2. 3. 4. 5.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

UNIT PLAN UNIT : 4 UNIT CONTENTS: Flip-Flops & Timing Circuit: S-R Latch; Gated S-R Latch; D Latch; J-K flip-Flop; T Flip-Flip: Edge Triggered SR, D, J-K and T Flips-Flops; Master - Slave Flip-Flops; Direct Preset and Clear Inputs. Shift Registers: PIPO, SIPO, PISO, SISO, Bi-Directional Shift Registers; Universal Shift register. Counter: Asynchronous Counter: Ripple Counters; Design of asynchronous counters, Effects of propagation delay in Ripple counters, Synchronous Counters: 4-bit synchronous up counter, 4-bit synchronous down counter, Design of synchronous counters, Ring counter, Johnson counter, Pulse train generators using counter, Design of Sequence Generators; Digital Clock using Counters. Unit Objectives: Broad Objectives of the unit are: 1. Latches 2. Clock Signals and Clocked Flip-Flops 3. Data transfer using shift registers 4. Counters By fulfilling the objective the student will satisfy POs (a), (b), (c) and (k) and three levels of Blooms Taxonomy Cognitive Domain i.e. Remember, Understand and Creativity. Once the student has completed this unit he/she will be able to answer following questions/perform the following activities: 1. Understand and construct various flip flops. 2. Transfer binary information. 3. Designing of counters. With the above POs (a), (b), (c) and (k) is expected to be achieved Methodology: This unit proceeds with explaining latches, various types of flip flops and the way they are triggered. Different shift registers, counters and their designing will also be covered in this unit. Related laboratory experiments as per the curriculum 1. 2. 3. 4. To Construct A RS Flip Flop Using Basic & Universal Gates (NOT, NOR & NAND). To Verify The Operation of A Clocked S-R Flip Flop And J. K. Flip Flop. To Construct a T & D Flip Flop Using J K Flip Flop and Verify Its Operations & truth table. To Verify The Operation of A Synchronous Decade Counter. Assignment 4: Design mod-10 asynchronous counter. Design mod-6 synchronous counter. What is race around condition for J-K flip flop? How it can be avoided in master slave flip flop? Draw & describe the working of PISO shift register. Explain how a number can be shifted in and out from such registers. 5. Do conversion of S-R flip flop to J-K flip flop. The above assignment is designed to address PO (a), (b), (c) and (k) and level (1), (2) and (5) of Blooms Taxonomy of
Cognitive Domain.

1. 2. 3. 4.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

UNIT PLAN UNIT : 5 UNIT CONTENTS: Introduction : Simple Diode Gating and Transistor Inverter; Basic Concepts of RTL and DTL; TTL: Open collector gates, TTL subfamilies, IIL, ECL; MOS Logic: CMOS Logic, Dynamic MOS Logic, Interfacing: TTL to ECL, ECL to TTL, TTL to CMOS, CMOS to TTL, Comparison among various logic families, Manufacturers specification. Unit Objectives: Broad Objectives of the unit are: 1. Knowledge of various Logic Families 2. Interfacing Logic Families 3. Comparison among various logic families characteristics By fulfilling the objective the student will satisfy POs (a), (d) and (k) and four levels of Blooms Taxonomy Cognitive Domain i.e. Remember, Understand, Analysis and Creativity. . Once the student has completed this unit he/she will be able to answer following questions/perform the following activities: Analyzing various logic families in digital circuits, and evaluating their performance by measuring propagation delay, noise margins, and fan-out. With the above POs (a), (d) and (k) is expected to be achieved Methodology: This unit will be taught by presenting the basic electronic circuits in each IC digital logic family and analyzing their electrical operation. Related laboratory experiments as per the curriculum No laboratory experiments. Reading Material to be recommended/required beyond syllabus to cover latest technological advancements related to the topic Fabrication & packaging process of digital ICs. Assignment 5: Draw the circuit diagram of two input NAND gate using TTL logic & explain. Design inverter by using CMOS logic and explain. Explain characteristics of digital ICs. Define the following parameters. a) Noise margin b) Propagation delay c) Power dissipation d) Speed power product e) Threshold voltage f) Fan in & Fan out 5. Give comparison among various logic families. The above assignment is designed to address PO (a), (d) and (k) and level (1), (2), (4) and (5) of Blooms Taxonomy of 1. 2. 3. 4.
Cognitive Domain.

1.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

CEO # addressed 1, 2 1 1, 2 1, 2 1

Related PEO # the CEO addresses 1, 2 1 1, 2 1, 2 1

Unit Title

Knowledge

Skill

Attitude & Values

Codes Minimization Techniques Combinational Circuits Sequential Circuits Digital Logic Families

X X X X X

X X

CO # addressed a, b, k A a, b, c, d, k a, b, c, k a, d, k

Related PO # the CO addresses a, b, k a a, b, c, d, k a, b, c, k a, d, k

Unit Title

Cognitive Domain (level #) 1, 2, 3 2, 3 1, 2, 5 1, 2, 5 1, 2, 4, 5

Psychomotor Domain (Skills) level #

Affective Domain (Level #)

Codes Minimization Techniques Combinational Circuits Sequential Circuits Digital Logic Families

xi) Mapping of Mid-term and Final Examination with PEOs, POs, CEOs and COs: Examination I Mid Term Examination Final Examination Examination I Mid Term Examination Final Examination
X X X X

CEOs II
X X

Course Outcomes a
X X

c
X X

d
X

k
X X

PEOs II
X X

Programme Outcomes a
X X

c
X X

d
X

k
X X

The one set of mid-term examination paper is included in Annexure 1(a) and its model solution is included in Annexure 1(b). The one set of final-examination paper is included in Annexure 2(a) and its model solution is included in Annexure 2(b).

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

xii) Mapping of Assignments with CEOs and COs: A series of homework questions are provided as the course proceeds as mentioned in the unit plan. The mapping with CEOs and COs of each homework collectively is given below.

Assignment No. I Assignment 1 Assignment 2 Assignment 3 Assignment 4 Assignment 5 xiii) University Question Papers:
X X X X X

CEOs II
X X X

COs a
X X X X X X X X X X X X X X

b
X

k
X

A complete set of 3 year question papers of university exams is provided in Annexure 3.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

xiv) Mapping of Course contents with PEOs and POs (Theory): Mapping Instructional Schedule (Lecture) with PEOs and Pos
Subject- Digital Electronic Circuits Code- 328414 (28) Semester 4th Discipline- Electronics & Telecommunication S Syllabus Covered No. Re 1 2 3 4 5 6 7 UNIT-1 : CODES Introduction & usefulness, Types of codes Types of codes Gray code : Binary to Gray & Gray to Binary code conversion Error Detecting Code, error correcting code (7-bit hamming code) Realization of expression, Boolean expressions & Logic diagram Converting AND/OR/INVERT logic to NAND/NOR logic SOP & POS forms and their realization UNIT-2 : MINIMIZATION TECHNIQUES Expansion of a Boolean expression to SOP form & POS form K-map K-map Concept of dont care terms Quine Mc-Clusky method Quine Mc-Clusky method UNIT-3 : COMBINATIONAL CIRCUITS Adder & Subtractor Adder & Subtractor, Parallel binary adder Look ahead carry adder Serial adder BCD adder Code converter Parity bit generator/checker, Comparator Decoder & Encoder Multiplexer De-multiplexer PLD PLD UNIT-4 : SEQUENTIAL CIRCUITS Latch Flip-flop types Flip-flop types Flip-flop types Shift registers & its types Types of shift registers Asynchronous counter & its design Asynchronous counter & its design Synchronous counter & its design Ring & Johnson counter Design of sequence generators X X Un X X X X X X X X X

Blooms Level Ap An Cr Ev I X X X X X

PEOs II X X X X X X III a X X X X X b c D e

POs f g h i j k X X X X X X

X X X X

8 9 10 11 12 13

X X X X X X

X X X X X X

X X X X X X

X X X X X X

X X X X X X

14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

X X X X X X X X X X X X X X X X X X X X X X

X X X X X X X X X X X X X X X X X X X X X X X

X X X X X X X X X X

X X X X X X X X X X X X X X X X X X X X X X X

X X

X X X X

X X X X X X X X X X X X X X X X X X X X X X X

X X

X X X X X X X X X

X X X X X X X X X

X X X X X X X X X

X X X X X X X

X X X X X X

X X X

X X X X X X X X X X

X X X X X X X X X

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

Mapping Instructional Schedule (Lecture) with PEOs and Pos

Subject- Digital Electronic Circuits Code- 328414 (28) Semester 4th Discipline- Electronics & Telecommunication S No. Syllabus Covered Re UNIT-5 : DIGITAL LOGIC FAMILIES 37 Un

Blooms Level Ap An Cr Ev I

PEOs II III a b c D e

POs f g h i j k

38 39 40 41

Introduction, Fabrication & packaging process of digital ICs. RTL,DTL TTL, TTL subfamilies IIL, ECL MOS logic, Interfacing

X X X X

X X X X

X X X X

X X X X

X X X

X X X

Re- Remember

Un- Understanding

Ap- Application

An- Analysis

Cr- Creativity

Ev- Evaluation

Mapping Instructional Schedule (Tutorial) with PEOs and Pos

Subject- Digital Electronic Circuits Code- 328414 (28) Semester 4th Discipline- Electronics & Telecommunication S No. Syllabus Covered 1 2 3 4 5 Re X X X X X Un X X X X X

Blooms Level Ap X X X X X X An X X Cr X X X X X Ev I X X X X X

PEOs II X X X X X III a X X X X X b c X X X X X D X X X X X e

POs f G h i j k X X X X X

Solving Previous Year Question Papers (Apr. May. 2009) Solving Previous Year Question Papers (Apr. May 2010) Solving Previous Year Question Papers (Nov. Dec 2010) Solving Previous Year Question Papers (Apr. May. 2011) Solving Previous Year Question Papers (Nov. Dec. 2011) Re- Remember

Un- Understanding

Ap- Application

An- Analysis

Cr- Creativity

Ev- Evaluation

Mapping Assignment with PEOs and Pos

Subject- Digital Electronic Circuits Code- 328414 (28) Semester 4th Discipline- Electronics & Telecommunication S No. Syllabus Covered 1 2 3 4 5 Assignment 1 Assignment 2 Assignment 3 Assignment 4 Assignment 5 Re X X X X Un X X X X X

Blooms Level Ap X X An Cr Ev I X X X X X

PEOs II X X X III a X X X X X b X X X c D e

POs f G h i j k X X X X

X X X

X X

X X

Re- Remember

Un- Understanding

Ap- Application

An- Analysis

Cr- Creativity

Ev- Evaluation

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

Mapping Instructional Schedule (Laboratory) with PEOs and POs

Subject- Digital Electronic Circuits Lab Code- 328422 (28) Semester 4th Discipline- Electronics & Telecommunication S No. Name of Experiment To Verify The Properties of NOR & NAND Gates As Universal Building Block. Realization of Boolean Expression Using NAND Or NOR Gates. To Construct X- OR Gate Using Only NAND Or NOR Gates Only. To Construct A Half Adder Circuit. And Logic Gates And Verify its Truth table. To Construct A Full Adder Circuit. And Verify its truth table (Using Two X-OR And 3 NAND Gates). To Construct A Half Subtractor Circuit. By Using Basic Gates And Verify its truth table. To Construct a Full Subtractor Circuit by Using Basic Gates and Verify its truth table. To Construct A Circuit of 4 -Bit Parity Checker & Verify its truth table. To Design a Comparator Circuit & Verify its truth table. To Construct A RS Flip Flop Using Basic & Universal Gates (NOT,NOR & NAND). To Verify The Operation of A Clocked S-R Flip Flop And J. K. Flip Flop. To Construct a T & D Flip Flop Using J K Flip Flop and Verify Its Operations & truth table. To Verify The Operation of A Synchronous Decade Counter. X X Re X Un X

Blooms Level Ap An Cr Ev I X

PEOs II X III a X b X c X D e

POs f G h i j k X

10

11

12

13

Re- Remember

Un- Understanding

Ap- Application

An- Analysis

Cr- Creativity

Ev- Evaluation

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

xv) Rubrics for Assessment of Course Outcomes: The course outcomes will be assessed based on the following rubrics as course proceeds as per unit plan and instructional schedule. Course feedback will be taken at regular intervals during the semester. Levels
Able to understand the concept and importance of Number System and Codes in Digital Logic Design

Exemplary
Student knows the significance of various codes and number system. Also, he/ she can easily employ Boolean algebra to describe the function of logic circuits. Students know the mapping and minimization of SOP and POS expression; and the concept of completely and incompletely specified functions. Students successfully comprehend the knowledge of Combinational logic circuits and also programmable logic devices. Students successfully comprehend the knowledge of Sequential logic circuits

Competent
Students have knowledge about various gates and implementation of switching function using basic and universal gates.

Developing
Students are capable of realizing the Boolean expression by using various postulates and axioms of Boolean algebra. Students are able to simplify the given expression by at least one of the methods.

Novice
Students can distinguish between different codes and number system. Also, he/she is able to answer questions based on that.

Points

Expansion methods and different minimization techniques of Boolean Expression

Students can minimize the Boolean expression by any of the given techniques.

Students can identify SOP and POS expression; and can at least expand it into minterms and maxterms.

Able to study different combinational circuits and its designing using logic gates

Students understand and can design different combinational circuits.

Students know some of the combinational circuits and are able to design to them.

He/ she can at least differentiate between combinational and sequential circuits.

Able to study different Sequential circuits and its designing using logic gates.

Students understand and can design different flip flops and counters.

Students can describe the functioning of different flip flops, counters and registers.

Students can identify different types of flip flops and counters

Able to gain knowledge of Digital logic families and its comparison considering various factors Overall Performance Point Required

Students understand the need of ICs and have complete knowledge about their families.

Exemplary

Students know the functioning and characteristics of digital logic families. Also he/she is able to interface different logic families. Competent

Students can differentiate among different logic families depending upon their important parameters or properties. Developing

Students are able to understand the electrical operation of some of the digital logic families because of the prior knowledge of basic electronics. Novice

Total

31-40

21-30

11-20

1-10

Department of Electronics and Telecommunication Engineering, RCET, Bhilai

xvi) Rubrics for Assessment at the end of Course: Level Mid-Term Exam Final Exam Assignment Teacher Assessment Exemplary Competent Developing Novice

The above assessment is carried out on a class of 60 students. 75% students are expected to clear the university examination in this subject after the declaration of results.

Prepared ByProf. Heena Parveen, Lecturer, Department of Electronics and Telecommunication Engineering, Rungta College of Engineering and Technology, Bhilai.

Department of Electronics and Telecommunication Engineering, RCET, Bhilai