Introduction to Cadence Opus

Digital HDL design Logic simulation (NCVerilog / NCVHDL)

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Introduction
In the next few pages, you will become familiar with the NC-Verilog logic simulator interface. The presentation that follows lets you experiment with the simulation of the digital circuits.

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Overview
The Cadence NC-Verilog simulator is a digital logic simulator that combines the high-performance of native compiled code simulation with the accuracy, flexibility, and debugging capabilities of the event-driven simulation. In a Verilog/VHDL configuration, both the Verilog and VHDL compilers are used to generate code for the Verilog and VHDL portions of the design, respectively. During an elaboration process (similar to the linking used in computer programming), the Verilog and VHDL code segments are combined into a single code stream. This single executable code is then directly executed by the host processor (simulator).

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

HDL simulation flow

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Short Verilog syntax summary

The basic structure of a Verilog description
`timescale ns/ps module name(p1, p2, p3, ... pn); input p1, p2; input [msb1 : lsb1] p3; output p4, p5; output [msb2 : lsb2] p6; ... ... Body of the module ... ... endmodule

The basic unit of a Verilog description is the module, delimited by the keywords module and endmodule

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simple Verilog behavioral example

A simple example - RS Latch
`timescale 1ns/10ps module rsl1(q, qn, preset, clear); output q, qn; input preset, clear; wire preset, clear; reg q, qn; always @(preset or qn) #1 q = !(qn && preset); always @(clear or q) #1 qn= !(q && clear); endmodule

In the body of the module the input and output ports, registers, wires have to be declared The identifiers of the registers and wires can be used as output and input ports of the module, respectively

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simple Verilog behavioral example

The simple example - RS Latch The timescale determines the `timescale 1ns/10ps period of the time between two module rsl1(q, qn, preset, clear); steps for the simulator output q, qn;
input preset, clear; wire preset, clear; reg q, qn; always @(preset or qn) #1 q = !(qn && preset); always @(clear or q) #1 qn= !(q && clear); endmodule

always (condition) #n what to do If there are any changes on the input ports and the condition is true then the procedure will be executed In this example both always procedures have unit delay (in this case 10ns)

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simple Verilog RTL example

The simple example - RS Latch
`timescale 1ns/10ps module rsl2(q, qn, preset, clear); output q, qn; input preset, clear; wire preset, clear; wire q, qn; // declare two nand gates // with unit delay nand #1 g1(q, qn, preset), g2(qn, q, clear); endmodule

The other possibility to describe a structure is using built-in generic gates (RT level description) wires have to be declared as connecting elements between the parts of the model In this example two nand gates are defined having unit delay

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Generating testbench
If the model of a circuit (or a function) has been constructed then the next step is verifying it by simulation. For this purpose a testbench is needed, which contains an instance of the model and provides the stimuli (input test signal sequence). The testbench forms the external world for the model to be tested. The driving signals have to be generated here as well as the outputs of the model have to be received and, if necessary, processed.

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Generating testbench
The simple example - RS Latch testbench
`timescale 1ns/10ps module rslx_test; wire q, qn; reg preset, clear; parameter d = 10; rsl1 latch(q, qn, preset, clear); initial begin preset = 0; clear = 1; #d preset = 1; #d clear = 0; #d clear = 1; end endmodule

Declaration part of two output wires and two input variables (registers) Create an instance of the RS-Latch modul (instance call) Initial procedure initial begin runs only once end

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Starting the Verilog GUI

Make a middle click at an empty place of the screen and the Engineering Tools popup window opens. Make a left click on the Simulators Verilog/VHDL

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Starting the Verilog GUI

A new UNIX shell comes up and asks for the Verilog home directory, where the Verilog source files will be stored If this directory doesnt exist, it will be created automatically (the default name is NCHDL) If you first run the Verilog tool the program asks if you want Multiple Step or Single Step procedure. Choose Multiple Step item in that dialog box
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Starting the Verilog GUI

The multiple step process flow contains: Compilation - it is analogous to that of computer programs. Each module is taken one by one and translated into an internal format (such as object files in computers) Elaboration - it does some kind of linking the modules with each other to form a single code stream per unit Simulation of the elaborated objects

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Setting your environment

First determine the working directory In the menubar left click FileSet Design Directory

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Setting your environment

Click the Create cds.lib File

Click Save button

Select the 3rd checkbox, and press OK

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Setting your environment

The default Work Library name automatically appears, and in the main window directory structures can be seen:

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Generating HDL description

The next step is to start writing the Verilog source code(s) First at all the text editor has to be selected Select Edit Preferences

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Generating HDL description

The Editor Command can be changed for textedit %F or gvim %F Then press OK button

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Generating HDL description

Next, create a new directory for HDL sources

Enter the name of the directory (e.g. sources) then press OK.
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Generating HDL description

Click FileEdit New File menu item in the main window It shows the actual directory, in most cases it is the recently specified Verilog home directory The contents of the directory are shown here Change directory to sources (double click at sources), then specify a Verilog filename (e.g.: alu.v) then click the Save button and the text editor opens

The file name of the Verilog source can be entered here

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Generating HDL description

In the text editor the Verilog source can be entered To save the code right click at File -> Save When finished close the window

`timescale 1ns/10ps module rsl1(q, qn, preset, clear); output q, qn; input preset, clear; wire preset, clear; reg q, qn; always @(preset or qn) #1 q = !(qn && preset); always @(clear or q) #1 qn= !(q && clear); endmodule

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Compiling Verilog sources

To compile the sources click on the VLOG icon or Select ToolsVerilog Compiler menu itemu Compiling the Verilog sources generates the new modules in the module window as subentries of worklib

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Elaborating the compiled module(s)

Select the highest hierarchical level module of the testbench CLICK on the Elaborate button or Select the ToolsElaborator menu item
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Elaborating the compiled module(s)

At the first elaboration select the ToolsElaborator menu item which invokes the Elaborate dialog box Check Access Visibility and set it to All !!! Then press OK button

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simulating the code stream

After elaboration the Snapshots folder has to be opened in the module panel Select the snapshot of your testbench and click on the Simulate button or Select ToolsSimulate menu item
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simulating the code stream

The ncsim simulator window opens Left click Select Signals in the menu bar In the source code all selected signals become highlighted

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simulating the code stream

Left click the Waveform button After a while the waveform window appears Click the big play button to run the simulation

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simulating the code stream

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simulating the code stream

In the waveform window at the upper left corner of the waveform pane there is a small red flag of the cursors. It can be dragged by the left and the middle mouse button. In the narrow pane between the signal list and the waveform the signal values can be read, at the simulation time indicated by the cursor TimeA. For a simple zoom facility hold down the right mouse button on the waveform and a zoom menu appears

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simulating the code stream

Displaying internal signals
By clicking right of the Subscopes box at the small button with the black triangle a dropdown list appears showing the internal modules of the simulated system Selecting one of them the actual source code text appears in the source code pane.
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Simulating the code stream

Displaying internal signals

If all the signals of the internal module are needed to display, then they can be selected by left clicking at Select->Signals

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study I
Arithmetic Logic Unit (ALU) The core of a central processing unit, CPU; performs a set of arithmetic and logic micro operations. Generate a behavioral Verilog description of an ALU.
Sel[4:0] Sel[1:0] Sel[2] Sel[4:3]

A[7:0] B[7:0]

Logic Unit

Logic Unit [7:0]

MUX

ALU_noShift[7:0]

Shifter

Arith Unit [7:0]

Carryin

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study I
Arithmetic Logic Unit (ALU) It has n encoded inputs for selecting the operation to be performed
S4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 S3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 S2 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 S1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 S0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 0 Cin 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 Operation Y <= A Y <= A + 1 Y <= A + B Y <= A +B + 1 Y <= A + Bbar Y <= A + Bbar + 1 Y <= A - 1 Y <= A Y <= A and B Y <= A or B Y <= A xor B Y <= Abar Y <= A Y <= shl A Y <= shr A Y <= 0 Function Transfer A Increment A Addition Add with carry A plus 1's complement of B Subtraction Decrement A Transfer A AND OR XOR Complement A Transfer A Shift left A Shift right A Transfer 0's Implementation block Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Arithmetic Unit Logic Unit Logic Unit Logic Unit Logic Unit Shifter Unit Shifter Unit Shifter Unit Shifter Unit

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study I
Arithmetic Logic Unit (ALU) First define the ports and registers:
`timescale 1ns/10ps module ALU (Sel, CarryIn, A, B, Y); input [4:0] Sel; input CarryIn; input [7:0] A, B; output [7:0] Y; reg [7:0] Y; reg [7:0] LogicUnit, ArithUnit, ALU_NoShift; always @(Sel or A or B or CarryIn) begin the descriptions of different units come here end endmodule
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study I
Arithmetic Logic Unit (ALU) the operations: Logic Unit Arithmetic Unit
case ({Sel[1:0]}) 2'b00 : LogicUnit = A & B; 2'b01 : LogicUnit = A | B; 2'b10 : LogicUnit = A ^ B; 2'b11 : LogicUnit = ~A; default : LogicUnit = 8'bX; endcase case ({Sel[1:0], CarryIn}) 3'b000 : ArithUnit = A; 3'b001 : ArithUnit = A + 1; 3'b010 : ArithUnit = A + B; 3'b011 : ArithUnit = A + B + 1; 3'b100 : ArithUnit = A + ~B; 3'b101 : ArithUnit = A - B; 3'b110 : ArithUnit = A - 1; 3'b111 : ArithUnit = A; default : ArithUnit = 8'bX; endcase

Do not forget to type { and } !!!

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study I
Arithmetic Logic Unit (ALU) the operations: Multiplexer unit Shifter unit
if (Sel[2]) ALU_NoShift = LogicUnit; else ALU_NoShift = ArithUnit; case ({Sel[4:3]}) 2'b00 : Y = ALU_NoShift; 2'b01 : Y = ALU_NoShift << 1; 2'b10 : Y = ALU_NoShift >> 1; 2'b11 : Y = 8'b0; default : Y = 8'bX; endcase

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study I
Arithmetic Logic Unit (ALU) Testbench
`timescale 1ns/10ps module TESTGEN_ALU; reg [4:0] Sel; reg CarryIn; reg [7:0] A,B; wire [7:0] Y; integer i; ALU ALU(Sel, CarryIn, A, B, Y); initial begin Sel = 5'b00000; A = 8'h33; B = 8'hcc; CarryIn = 0; // Test Arithmetic Unit for (i=0; i<4; i=i+1) #10 Sel[1:0] = Sel[1:0] + 2'b01; #10 CarryIn = 1; for (i=0; i<4; i=i+1) #10 Sel[1:0] = Sel[1:0] + 2'b01; #10 CarryIn = 0; // Test Logic Unit #10 Sel[2] = 1; for (i=0; i<4; i=i+1) #10 Sel[1:0] = Sel[1:0] + 2'b01; #10 Sel[2] = 0; // Test Shift operations for (i=0; i<4; i=i+1) #10 Sel[4:3] = Sel[4:3] + 2'b01; end endmodule

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study I
In this exercise you have to do these steps: Create the ALU verilog source Create the ALU testbench Check the arithmetic unit Check the logic unit Check the shifter unit

Compile, elaborate and simulate Check the operation of the ALU

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
Central Processor Unit (CPU) The design of a processor is a complex scenario. Multimillion instruction processors (MIPS), complex instruction set processors (CISC), reduced instruction set processors (RISC) are all models that are used in different applications. The HDL description you will be working with is a simple processor that does 4 simple mathematical functions. The circuit implements addition, incrementing, complementing and XOR.

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
There are five modules used in this exercise: alu.v reg8.v count5.v decode.v cpu.v Contains the mathematical operations Works as the random access memory (RAM) Works as a program counter Controls the flow of data through a state machine Top-level design

The Verilog description of all models are completed. The intention of this lab is creating a testbench and simulating the top level design (CPU).

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
The schematic of the CPU

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
The operation of the CPU The CPU begins to operate on the positive edge of the reset. At each positive edge of the clock the state of the CPU changes. There are 8 states per instruction cycle. On reset signal the counter of the CPU resets, and sets pcout (address of instructions) to 00h this is the address of the first instruction. The value of the PC register is incremented in each instruction cycle. The ALU executes an instruction (which one is determined by opcode) when it is enabled (en_alu = 1).
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

module decode(ld_acc, mem_rd, mem_wr, inc_pc, ld_pc, ld_ir, sel_dat, en_alu, sel_adr, opcode, zero, clk, rst); always @(posedge clk or negedge rst) begin if (!rst) state = 3'b000; else case (state) 3'b000: state = 3'b001; 3'b001: state = 3'b011; 3'b011: state = 3'b010; 3'b010: state = 3'b110; 3'b110: state = 3'b111; 3'b111: state = 3'b101; 3'b101: state = 3'b100; 3'b100: state = 3'b000; endcase end .

Case study II
se Re t

The decode module determines the operation of the CPU in different states and determines the order of the states (Gray counter). 1

0 4 5

3 2

The cycle of states 7 6

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
In the testbench, imagine, there is a RAM connected to the CPU. Operand A is stored in the RAM at the address 08h, the operand B is stored at the address 09h. The instructions are stored from the address 00h.
clock / 1 reset / 1 memrd / 1 memwr / 1 address/ 5 dataout / 8 datain / 8 1111 0000 0100 A operand 0101 B operand

CPU

RAM

testbench
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
The instruction word format (8 bit) ooo | aaaaa MSB (3 bit) the operation code LSB (5 bit) the address of the operand, they are stored in the instruction register (IR) after being read from the memory Example: 100 | 01001 (89h) Memory read (dataIn F0h) from 09h Generate accumulator XOR dataIn (04h)

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
case (state) 3'b000: {inc_pc, ld_acc, ld_pc,mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} = 9'b000000001

State 0 set the address to pcout

3'b001: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} = 9'b000011001;

State 1 read from memory, and load the instruction to the IR State 3 stop reading from the memory State 2 increment PC

3'b011: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} = 9'b000000001; 3'b010: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} = 9'b100000001; 3'b110: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} = 9'b000000000;

State 6 set the address to IR (for read operand from the memory)

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
3'b111: case (opcode)

State 7 depends on the opcode

Opcode 7 - enable ALU, load IR address to PC register (simple goto)

3'b111: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} = 9'b001000010; 3'b010, 3'b100, 3'b101: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} = 9'b000010010;

Opcode 2,4,5 enable ALU, enable mem_rd

3'b000: begin {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000000010; Opcode 0 enable ALU end default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000000010; endcase Opcode 1,3,6 enable ALU

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
3'b101: case (opcode)

State 5 depends on the opcode

Opcode 1 enable sel_dat

3'b001: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000000100; 3'b010, 3'b100, 3'b101: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b010000000; 3'b000: begin {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000000100; end Opcode 0 enable sel_dat default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000000100; Opcode 3,6,7 enable sel_dat endcase
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Opcode 2,4,5 enable ld_acc (Load to accumulator)

Case study II
3'b100: case (opcode)

State 4 depends on the opcode

3'b110: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000100100;

Opcode 6 enable sel_dat, mem_wr

3'b010, 3'b100, 3'b101: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000000000;

Opcode 2,4,5 disable all

3'b000: begin {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000000100; Opcode 0 enable sel_dat end default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} = 9'b000000100;

Opcode 3,6,7 enable sel_dat

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study II
In this exercise you have to do these steps: Create the CPU testbench Read two operands from the memory (from the 16h and 17h address) Generate A and B Write the result to the 1Ch address

Compile, elaborate and simulate Check the operation of CPU

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Delay backannotation
In the next few pages, you will become familiar with the verilog backannotation interface. The presentation that follows lets you experiment with the simulation of the correct physical delays.

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Delay backannotation
Standard Delay File (SDF) After the Verilog RTL description is synthesised by any Physical Synthesis (e.g. Cadence PKS) or backannotated by any Physical Design Tool (e.g. Silicon Ensemble) the real constraints of the physical design are computed and stored in an SDF file. The SDF file contains the pre-calculated or the real delays of each net (RC) and the delays of each block (gates). This file can be loaded into the Verilog Simulator Environment, so the pre-calculated or real, accurate timing rule violations can be viewed and checked.
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Delay backannotation
To enable the SDF elaborating: Select ToolsElaborator menu item and Click on Advanced Options button, then the Elaborator Advanced Options windows appears

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Delay backannotation
Select Verilog Perfomance tab, and check in Delay Modes and select path mode

Select PLI tab, and check in Enable delay annotation at simulation time
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Delay backannotation
Select Annotation and check in Specify delay types and select Maximum mode. Check in, too, Use worst case...

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Delay backannotation

The Verilog RTL source simulation result, without using SDF file (the 0.1ns - the default delay of the gates - can be seen)
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Delay backannotation
timescale 1ns/10ps module test_alu; reg clk, ena, rst; wire [7:0] aluout; parameter half_cyc = 100; alu alu(aluout, zero, opcode, data, accum, clk, ena, rst); initial $sdf_annotate("alu_rtl.sdf",alu); initial begin Add to the testbench source initial the instruction . use SDF in the elaboration and in the simulation: end endmodule

to

$sdf_annotate(sdf_file_name.sdf,module_name) Should be the first initial before the other initials !!!
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Delay backannotation

The Verilog RTL source simulation result with using the SDF file (the 1.4ns - the delays of the nets and the gates)
Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory

Case study III

In this exercise you have to do these steps: Use the previously generated CPU testbench Compile, elaborate and simulate using the delay file Check the operation of the CPU Compare the delays with the original ones

Budapest University of Technology & Economy Department of Electron Devices, CAD Laboratory