CONTENTS

Abstract Acknowledgement Certificate CHAPTER NO. 1. 2. 2.1 2.2 2.3 3. 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 4. 4.1 CHAPTER Introduction Motivation For 3D ICs Interconnect Limited VLSI Performance Physical Limitations Of Cu Interconnects System On-A- Chip (SoC) Design 3D Architecture Advantages of 3D Architecture 3D ICs v/s 3D Packaging Manufacturing Technologies Beam Re-crystallization Silicon Epitaxial Growth Processed Wafer Bonding Solid Phase Crystallization (SPC) Through Silicon Vias (TSVs) Bonding Techniques PAGE NO. 1 3 3 3 4 9 11 11 12 12 13 14 15 17 24 i ii iii

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3D IC Packaging Technology 5.1 5.2 5.3 5.4 Types Of 3D Packages Estimating 2D and 3D Chip Area Two Active Layer 3D Circuit Performances Optimization of interconnect distribution Challenges For 3D Integration Thermal issues in 3D ICs Reliability issues in 3D ICs Thermal Awareness In 3D IC 3D ICs and Integrated Circuit Security Benefits & Applications Of 3D ICs 7.1 7.2 Benefits Applications Conclusion References

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6. 6.1 6.2 6.3 6.4 7.