CPS 104 Computer Organization and Programming Lecture-8 : Instruction Set Architecture

Jan. 28, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

CPS104 Lec-8.1

GK Spring 2004

Instruction Set Architecture

Application Operating System Compiler CPU Firmware

Software Interface Between HW and SW

Instruction Set Architecture, Memory, I/O

Memory I/O system Digital Design

Circuit Design

Hardware

CPS104 Lec-8.2

GK Spring 2004

Levels of Representation
temp = v[k]; High Level Language Program Compiler Assembly Language Program Assembler Machine Language Program
0000 1010 1100 0101 1001 1111 0110 1000

v[k] = v[k+1]; v[k+1] = temp;

lw $15, lw $16, sw$16, sw$15,

1100 0101 1010 0000
Rd Mux RegWr 5 busW 32 Clk Rs 5 5

0($2) 4($2) 0($2) 4($2)

1010 0000 0101 1100 1111 1001 1000 0110
ALUctr MemtoReg busA 32

0110 1000 1111 1001

Rt

0101 1100 0000 1010

1000 0110 1001 1111

Machine Interpretation Control Signal Specification

CPS104 Lec-8.3

RegDst

Dont Care (Rt)

Rw Ra Rb 32 32-bit Registers

ALU

Mux

busB 32

32 MemWr WrEn Adr

32

Mux

Extender

imm16

32 ALUSrc

16

Data In 32 Clk

Data Memory

ExtOp

GK Spring 2004

Computer Architecture?
. . . the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, 1964

SOFTWARE

CPS104 Lec-8.4

GK Spring 2004

Requirements for ISA

#include <iostream.h> main() { int *a = new int[100]; int *p = a; int k; for (k = 0; k < 100; k++) { *p = k; p++; } cout << "entry 3 = " << a[3] << endl; }

What primitive operations do we need? (i.e., What should be implemented in hardware?)

CPS104 Lec-8.5

GK Spring 2004

Design Space of ISA Five Primary Dimensions

Operations Number of explicit operands Operand Storage Memory Address Type & Size of Operands add, sub, mul, . . . How is it specified? ( 0, 1, 2, 3 ) Where besides memory? How is memory location specified? byte, int, float, vector, . . . How is it specified? How is it specified? How are they determined? Fixed or variable? Wide?

Other Aspects
Successor instruction Conditions Encoding Parallelism

CPS104 Lec-8.6

GK Spring 2004

Basic ISA Classes Accumulator:

1 address 1+x address add A addx A acc acc + mem[A] acc acc + mem[A + x]

Stack:
0 address add tos tos + next (JAVA VM)

General Purpose Register:

2 address 3 address add A B add A B C A A + B AB+C

Load/Store:
3 address add Ra Rb Rc load Ra Rb store Ra Rb Ra Rb + Rc Ra mem[Rb] mem[Rb] Ra
GK Spring 2004

CPS104 Lec-8.7

Accumulator
Instruction set: Accumulator is implicit operand one explicit operand add, sub, mult, div, . . . clear Example: a*b - (a+c*b) clear 0 add c 2 mult b 6 a 4 add a 10 b 3 time st tmp 10 c 2 tmp clear 0 add a 4 mult b 12 sub tmp 2 9 instructions

CPS104 Lec-8.8

GK Spring 2004

Stack Machines
Instruction set: add, sub, mult, div . . . Top of stack (TOS) and TOS+1 are implicit push A, pop A TOS is implicit operand, one explicit operand Example: a*b - (a+c*b) push a time push b mult C -+* C*B B A B +* A A*B push a A A*B A*B A C A A*B A A*B push c A*B push b mult add + * sub * a b a 9 instructions

CPS104 Lec-8.9

GK Spring 2004

2-address ISA

Instruction set: Two explicit operands, one implicit add, sub, mult, div, one source operand is also destination add a,b a <- a + b Example: a*b - (a+c*b)

add tmp1, b mult tmp1, c add tmp1, a add tmp2, b mult tmp2, a sub tmp2, tmp1 6 instructions

tmp1, tmp2 3, ? 6, ? 10, ? 10, 3 10, 12 10, 2

a b c tmp1 tmp2

4 3 2

CPS104 Lec-8.10

GK Spring 2004

3-address ISA

Instruction set: Three explicit operands, ZERO implicit add, sub, mult, div, add a,b,c a <- b + c

Example: a*b - (a+c*b)

mult tmp1, b, c add tmp1, tmp1, a mult tmp2, a, b sub tmp2, tmp2, tmp1 4 instructions tmp1, tmp2 6, ? 10, ? 10, 12 10, 2

a b c tmp1 tmp2

4 3 2

CPS104 Lec-8.11

GK Spring 2004

Adding Registers to an ISA

A place to hold values that can be named within the instruction Like memory, but much smaller Byte Address Data u 32-128 locations 0 00110110 1 00001100 How many bits to specify a register?
2 3 4

r0

2n-1-4 2n-1

r31

CPS104 Lec-8.12

GK Spring 2004

3-address General Purpose Register ISA

Instruction set: Three explicit operands, ZERO implicit add, sub, mult, div, add a,b,c a <- b + c

Example: a*b - (a+c*b)

mult r1, b, c add r1, r1, a mult r2, a, b sub r2, r2, r1 4 instructions r1, r2 6, ? 10, ? 10, 12 10, 2

a b c

4 3 2

CPS104 Lec-8.13

GK Spring 2004

LOAD / STORE ISA

Instruction set: add, sub, mult, div, only on operands in registers ld, st, to move data from and to memory, only

way to access memory

Example: a*b - (a+c*b)
ld r1, c ld r2, b mult r1, r1, r2 ld r3, a add r1, r1, r3 mult r2, r2, r3 sub r3, r2, r1 7 instructions
CPS104 Lec-8.14

r1, r2, r3 2, ?, ? 2, 3, ? 6, 3, ? 6, 3, 4 10, 3, 4 10, 12, 4 10, 12, 2

a b c

4 3 2

GK Spring 2004

Using Registers to Access Memory

Registers can hold memory addresses

Given int x; int *p; p = &x; *p = *p + 8; Instructions ld r1, p ld r2, r1 add r2, r2, 0x8 st r1, r2

// r1 <- mem[p] // r2 <- mem[r1] // increment x by 8 // mem[r1] <- r2

x 0x26cf0

...

p 0x26d00 0x26cbf0

Many different ways to address operands u not all Instruction sets include all modes

CPS104 Lec-8.15

GK Spring 2004

Making Instructions Machine Readable

So far, still too abstract u add r1, r2, r3 Need to specify instructions in machine readable form Bunch of Bits Instructions are bits with well defined fields u Like a floating point number has different fields Instruction Format u Establishes a mapping from instruction to binary values u Which bit positions correspond to which parts of the instruction (operation, operands, etc.)

CPS104 Lec-8.16

GK Spring 2004

A "Typical" RISC

32-bit fixed format instruction (3 formats) 32 64-bit GPR (R0 contains zero) 3-address, reg-reg arithmetic instruction Single address mode for load/store: base + displacement u no indirection
see: SPARC, MIPS, MC88100, AMD2900, i960, i860 PARISC, PowerPC, DEC Alpha, Clipper, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3

CPS104 Lec-8.17

GK Spring 2004

Example: MIPS
Register-Register
31 26 25 21 20 16 15 11 10 6 5 0

Op

Rs1

Rs2

Rd

Opx

Register-Immediate
31 26 25 21 20 16 15 0

Op Branch
31

Rs1
26 25 21 20

Rd
16 15

immediate

Op Jump / Call
31

Rs1

Rs2/Opx

immediate

26 25

Op
CPS104 Lec-8.18

target

GK Spring 2004

A Program
#include <iostream.h> main() { int *a = new int[100]; int *p = a; int k; for (k = 0; k < 100; k++) { *p = k; p++; }

2n-1
Stack

.cc file

bits
Data

Text
cout << "entry 3 = " << a[3] << endl; }
add r,s1,s2

0
CPS104 Lec-8.19

Reserved

GK Spring 2004

Stored Program Computer

Instructions: a fixed set of built-in operations Instructions and data are stored in the (same) computer memory Fetch Execute Cycle
while (true){ fetch instruction execute instruction }

CPS104 Lec-8.20

GK Spring 2004

What Must be Specified?

Instruction Fetch Instruction Decode Operand Fetch Execute Result Store

Next Instruction
CPS104 Lec-8.21

Instruction Format u how do we tell what operation to perform? Location of operands and result u where other than memory? u how many explicit operands? u how are memory operands located? u which can or cannot be in memory? Data type and Size Operations u what are supported Successor instruction u jumps, conditions, branches fetch-decode-execute is implicit!
GK Spring 2004

MIPS ISA Categories

Arithmetic u add, sub, mul, etc Logical u and, or, shift Data Transfer u load, store u MIPS is LOAD/STORE architecture Conditional Branch
u

implement if,

for, while statements

Unconditional Jump u support function calls (procedure or methods calls)

CPS104 Lec-8.22

GK Spring 2004

MIPS Instruction Set Architecture

3-Address Load Store Architecture. Register and Immediate addressing modes for operations. Immediate and Displacement addressing for Loads and Stores. Examples: add $1, $2, $3 # $1 = $2 + $3 addi $1, $1, 4 # $1 = $1 + 4 lw sw lui addi $1, 100 ($2) $1, 100 ($2) $1, 100 $1, $3, 100 # # # # $1 = Memory[$2 + 100] Memory[$2 + 100] = $1 $1 = 100 << 16 $1 = $3 + 100

CPS104 Lec-8.23

GK Spring 2004

MIPS Integer Registers

Registers: fast memory, Integral partr0 of the CPU. r1 Programmable storage 2 32 bytes 31 x 32-bit GPRs (R0 = 0) 32 x 32-bit FP regs (paired DP) 32-bit HI, LO, PC r31

PC lo hi

CPS104 Lec-8.24

GK Spring 2004

MIPS Instruction Formats

R-type: Register-Register
31 26 25 21 20 16 15 11 10 6 5 0

Op

Rs

Rt

Rd

shamt

func

I-type: Register-Immediate
31 26 25 21 20 16 15 0

Op

Rs

Rt

immediate

J-type: Jump / Call

31 26 25 0

Op

target

Terminology Op = opcode Rs, Rt, Rd = register specifier

CPS104 Lec-8.25
GK Spring 2004

R Type:
31 26 25 21 20

<OP> rd, rs, rt

16 15 11 10 6 5 0

Op op rs rt rd shmt func

Rs

Rt

Rd

shmt

func

a 6-bit operation code. a 5-bit source register. a 5-bit target (source) register. a 5-bit destination register. a 5-bit shift amount. a 6-bit function field.

Operand Addressing: Register direct Example: ADD $1, $2, $3

op rs rt rd

# $1 = $2 + $3
shmt func

000000
CPS104 Lec-8.26

00010

00011 00001 00000

100000
GK Spring 2004

I-Type <op> rt, rs, immediate

31 26 25 21 20 16 15 0

Op

Rs

Rt

Immediate

Immediate: 16 bit value Operand Addressing: Register Direct and Immediate

Add Immediate Example addi $1, $2, -100 # $1 = $2 + (-100)

op rs rt immediate

001000

00010

00001

1111 1111 1001 1100

Rt becomes the destination register!

CPS104 Lec-8.27

GK Spring 2004

I-Type <op> rt, rs, immediate

31 26 25 21 20 16 15 0

Op

Rs Register

Rt

Immediate Memory

+
Register

Base+index
Load Word Example lw $1, 100($2)
op rs

# $1 = Mem[$2+100]
rt immediate

010011

00010

00001

0000 0000 0110 0100

CPS104 Lec-8.28

GK Spring 2004

Successor Instruction
Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction
CPS104 Lec-8.29
GK Spring 2004

main() { int x,y,same; // $0 == 0 always x = 43; // addi $1, $0, y = 2; // addi $2, $0, same = 0; // addi $3, $0, if (x == y) same = 1; // execute only if x // addi $3, $0, 1 }

43 2 0 == y

The Program Counter

Special register (pc) that points to instructions Contains memory address (like a pointer) Instruction fetch is
u

inst = mem[pc]

To fetch next sequential instruction pc

u

= pc + ?

Size of instruction?

CPS104 Lec-8.30

GK Spring 2004

The Program Counter

x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 same = 0; // addi $3, $0, 0 if (x == y) same = 1; // addi $3, $0, 1 execute if x == y

PC 0x10000 0x10004 0x10008 0x1000c

0x10000 0x10004 0x10008 0x1000c

addi addi addi addi

$1, $2, $3, $3,

$0, $0, $0, $0,

43 2 0 1

Clearly, this is not correct We cannot always execute both 0x10008 and 0x1000c
CPS104 Lec-8.31
GK Spring 2004

I-Type <op> rt, rs, immediate

31 26 25 21 20 16 15 0

Op

Rs PC

Rt

Immediate Memory

+
4

PC relative addressing Branch Not Equal Example bne $1, $2, 100 # If ($1!= $2) goto [PC+4+100] +4 because by default we increment for sequential u more detailed discussion later in semester

op

rs

rt

immediate

000101

00001

00010

0000 0000 0110 0100

CPS104 Lec-8.32

GK Spring 2004

The Program Counter

x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 if (x == y) same = 1; // addi $3, $0, $1 execute if x == y

PC 0x10000 0x10004 0x10008 0x1000c 0x10010

0x10000 0x10004 0x10008 0x1000c 0x10010

addi $1, $0, 43 addi $2, $0, 2 addi $3, $0, 0 bne $1, $2, 4 addi $3, $0, 1

Understand branches

CPS104 Lec-8.33

GK Spring 2004

Successor Instruction
Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction
CPS104 Lec-8.34
GK Spring 2004

int equal(int a1, int a2) { int tsame; tsame = 0; if (a1 == a2) tsame = 1; // only if a1 == a2 return(tsame); } main() { int x,y,same; // r0 == 0 always x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 same = equal(x,y); // need to call function // other computation }

The Program Counter

Branches are limited to 16 bit immediate Big programs?

x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 same = equal(x,y);

0x10000 addi $1, $0, 43 0x10004 addi $2, $0, 2 0x10008 go execute equal

0x30408 addi $3, $0, 0 0x3040c beq $1, $2, 8 0x30410 addi $3, $0, 1
return $3

CPS104 Lec-8.35

GK Spring 2004