Manas Lahon

154/10 3 Floor, 1 A Main,8 Block, Koramangala, Bangalore

rd st th

E-mail: manas.lahon@gmail.com
http://in.linkedin.com/pub/manas-lahon/6/860/21b Phone: +91-9739-722938

Areas of Interests: Non-Volatile Memory Systems, Computer Architecture, SOC Design. Education:
Birla Institute of Technology and Science(BITS)- Pilani,India
Bachelor of Engineering (Honors) Electrical and Electronics, 2008 GPA: 8.24/10

Salt Brook Academy, Assam, India

Intermediate Board of Secondary School Education 12th Grade Exams, 2004 Marks Obtained: 89.4 %, 2nd in the state in order of merit among 35000 students.

Professional Experience:
Cadence Design Systems, Bangalore
Lead Design Engineer, Design IP Group 2011 - present
Drove the design and implementation of control path block for ONFi and Toggle protocol compliant NAND Flash controller IP from initial architecture to micro-architecture and RTL development phase. Achieved approximate gate count reduction by 30% and 27% performance improvement from earlier implementation. Worked in close conjunction with Verification team for devising verification strategy for a fully functionally verified IP with excellent coverage metrics. Thus delivered and further also assisted clients with bring up and integration of the Industrys highest performance, most feature-rich, and most flexible NAND Flash IP. Architectural exploration of data compression, de-duplication and wear leveling in hardware for a SSD controller.

Senior Design Engineer, Design IP Group

2009 2011

Successfully executed the RTL design and verification effort for a Debug module for a SSD platform at the system level which provides post silicon debug utilities to software at the transaction boundary. DMA controller design and RTL implementation.

Design Engineer, Design IP Group

2008 2009

System Verilog based verification environment development as per AVM guidelines for NAND Flash controller IP. Maintained regression tests, wrote test cases and debugged scenarios. Designed bridge modules for AXI and AHB to Cadence proprietary SOC bus interface. Integrated these into existing IP and functionally verified full IP logic.

Indrion Technologies, Bangalore

Research Intern Jan 2008 - July 2008 Study in the field of wireless sensor network processing, existing WSN processors and technologies pertaining to extensible processors. Comparative study of various extensible processor benchmarks and architecture. Creation of an application benchmarks for WSN along with source codes. Profiling of applications to assist estimation of energy per instruction, number of memory accesses, and number of peripheral accesses. Custom instruction generation and addition.

Patents and Publications:

United States patent Application No. 13/628,982 Filed on 27 Sept, 2012
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System and Method for transfer of data between memories with Dynamic error recovery.
A system and method are provided for ensuring reliable data transfers by automatically recovering from uncorrectable errors detected in data traversing throughout a system and being retrieved from an unreliable intermediate data buffer between a first memory and a secondary slower memory. Additionally, measures to compensate for the use of unreliable or error-prone components and interconnects, such as, for example, SRAM memory as temporary buffer are provided. Further, measures to detect and correct errors whatever the type- injected or occurring at any stage throughout traversal of the system are provided. Defensive Publication (in process for VLSI-SoC Conference,2013)

Intelligent scheduling and arbitration of device commands in a NAND Flash Controller for maximum performance in a multi-package/multi-channel NAND Flash memory system.

Academic Projects:
Hardware Implementation of Digital Image Watermarking Algorithm
Jan,2007 April,2007 An FPGA chip was designed to calculate the Discrete Wavelet Transform (DWT) of an image. This design was further used to implement a DWT-based algorithm capable of embedding a watermark into images and video clips, as well as detect its presence, in real-time. FPGA capable of detecting the presence of a specific watermark in a video clip, which has a minimum of 25 frames per second, in real-time. Supervisor: Dr. Shikha Tripathi, BITS-Pilani June,2007-Dec 2007 Literature research into leakage current, causes and effects as scaling and technology progresses. Results obtained experimentally on various parameters of HfO2 using laser ellipsometer were analyzed to study the feasibility of using HfO2 as a possible high k di-electric Supervisor: Dr. Ashutosh Srivastava, BITS-Pilani (currently visiting faculty at Yale University,USA)

Leakage Current in CMOS: A Study of High-K dielectrics

Skillset:
Digital Logic Design and Micro-architecture design. Languages - Verilog, Perl, C, System Verilog. Verification methodologies - AVM,UVM OS- Linux, MS-DOS, Windows Tools - Questa, Modelsim, Cadence IUS, RTL Compiler Synthesis, HAL, Conformal CDC, LEC, Atrenta Spyglass CDC ,Lint ,Synopsys DC Interface protocols - AHB, AXI, DFI, NAND Flash memories ONFI 3.0, 2.3, 2.2, 2.1, Toggle 1.0, 2.0.

Awards and Achievements:

Multiple Employee Achievement Awards at Cadence Design Systems, India. Recipient of North Eastern Council-India Fellowship for the term 2004-2008 awarded to 15 students every year across 7 states. Received Merit cum Need scholarship, BITS-Pilani for all the semesters for good academics. th Secured highest marks in Maths and Physics in 12 grade among 60,000 students across the state. Awarded the Prestigious Assam Academy of Mathematics Gold medal-2004