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Hardware design in high-performance applications such as communications, wireless infrastructure, servers, broadcast video, and test and measurement equipment is becoming increasingly complex as systems integrate more functionality and require ever-increasing levels of performance. This trend extends to the board-level clock tree that provides reference timing for the system. A one size fits all strategy does not apply when it comes to clock tree design. Optimizing the clock tree to meet both performance and cost requirements depends on a number of factors, including the system architecture, integrated circuit (IC) timing requirements (frequencies, signal formats, etc.) and the jitter requirements of the end application.
synchronous Ethernet and HD SDI video transmission. These applications require transmitters and receivers to operate at the same frequency. Synchronizing all SerDes reference clocks to a highly accurate network reference clock (e.g., Stratum 3 or GPS) guarantees synchronization across all nodes. In these applications, low-bandwidth PLL-based clocks provide wander and jitter filtering (jitter cleaning) to ensure that network-level synchronization is maintained. In networking line card PLL applications, specialized jitter attenuating clocks or discrete PLLs with voltage-controlled oscillators (VCOs) are the preferred clock solution for SerDes clocking. For optimal performance, a jitter attenuating clock should be placed at the end of the clock tree, directly driving the SerDes device. Clock generators and buffers can be used to provide other system references.
Free-Running Clock Trees
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PLL
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1-2 reference clocks
XO + Clock Buffer
Low jitter clock fanout Single frequency
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Clock Jitter
Clock jitter is a critical specification for timing components because excessive clock jitter can compromise system performance. There are three common types of clock jitter, and, depending on the application, one type of jitter will be more important than another. Cycle-to-cycle jitter measures the maximum change in clock period between any two adjacent clock cycles, typically measured over 1,000 clock cycles. Period jitter is the maximum deviation in clock period with respect to an ideal period over a large number of cycles (10,000 clock cycles typical). Both cycle-to-cycle jitter and period jitter are useful in calculating setup and hold timing margins in digital systems, and are often figures of merit for CPU and SoC devices. Phase jitter is the figure of merit for high-speed SerDes applications. It is a ratio of noise power to signal power calculated by integrating the clock single sideband phase noise across a range of frequencies offset from a carrier signal. Phase jitter is especially critical in FPGA and high-speed SerDes clocking applications in which excessive phase jitter can degrade the bit error rate of the high-speed serial interface. During clock tree design and component selection, it is important to evaluate devices based on maximum jitter performance. Typical jitter specifications do not guarantee device performance over all conditions, including process, voltage, temperature and frequency variation. Maximum jitter provides a more comprehensive specification inclusive of these additional factors. In addition, take special care to review jitter test conditions on timing device data sheets. Clock jitter performance varies across a wide range of conditions including device configuration, operating frequency,
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signal format, input clock slew rate, power supply and power supply noise. Look for devices that fully specify jitter test conditions since they guarantee operation over a wider operating range.
Gl i tchl es s s wi tchi ng between cl ocks a t Integra ted l oop fi l ter di fferent frequenci es Cl ock di vi s i on Synchronous output cl ock di s a bl e Hi tl es s s wi tchi ng Hol dover
Note: This equation can be applied to calculating total period jitter and phase jitter, assuming the jitter distributions are Gaussian and uncorrelated. The equation should not be applied to cycle-to-cycle jitter, which is expressed as a peak jitter number and not RMS. Silicon Laboratories, Inc. Rev 1.0 3
() = 1 2 + 2 2 + + 2
Component jitter can be estimated using data sheet jitter specifications or calculated from phase noise data. Silicon Labs offers an easy-to-use utility for converting clock phase noise to jitter. See http://www.silabs.com/support/Pages/phase-noise-jitter-calculator.aspx for more details. Be sure to use maximum jitter specifications to generate a conservative estimate of total clock tree jitter.
125 MHz
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Format Select (LVPECL, LVDS, CML, HCSL, CMOS) 5 x 125 MHz 3.3V LVPECL VDDO 5 x 125 MHz 2.5V LVDS VDDO Format Select (LVPECL, LVDS, CML, HCSL, CMOS)
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Silicon Labs offers one of the industrys broadest portfolios of frequency flexible clock generators, clock buffers, jitter cleaning clocks and XO/VCXOs. Through this comprehensive offering, Silicon Labs provides the industrys highest performance and most highly integrated clock tree solutions. ###
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. Patent: www.silabs.com/patent-notice 2012, Silicon Laboratories Inc. ClockBuilder, DSPLL, Ember, EZMac, EZRadio, EZRadioPRO, EZLink, ISOmodem, Precision32, ProSLIC, QuickSense, Silicon Laboratories and the Silicon Labs logo are trademarks or registered trademarks of Silicon Laboratories Inc. ARM and Cortex-M3 are trademarks or registered trademarks of ARM Holdings. ZigBee is a registered trademark of ZigBee Alliance, Inc. All other product or service names are the property of their respective owners.
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