AAYAM13 Presents

Introduction to Verilog Hardware Description Language

Hardware Description Language (HDL)

Basic idea is a programming language to describe hardware Initial purpose was to allow abstract design and simulation

Design could be verified then implemented in hardware

Now Synthesis tools allow direct implementation from HDL code.

Large improvement in designer productivity

Purpose of HDL:
1.

2. 3. 4.

Describe the circuit in algorithmic level (like c) and in gate-level (e.g. And gate) Simulation Synthesis Words are better than pictures

What HDL is NOT

HDL is not a programming language (HDL is a description language) HDL is not highly abstract, e.g., implement the DSP algorithm y(n) = 0.75y(n-1) + 0.3x(n) (HDL is at the RTL level (register transfer))

Aug 9, 2001

FPGA System Design with Verilog

Synthesizable Subset

Verilog (and VHDL) began life as simulation and modeling tools Hardware synthesis developed during the 1990s Need to use a subset of Verilog and specific coding styles to allow synthesis tool to infer correct (and realizable) hardware

Aug 9, 2001

FPGA System Design with Verilog

Synthesizable Subset
Use this to write testbenches for behavioral simulation Verilog

Synthesizable Verilog Use this to make hardware

Aug 9, 2001

FPGA System Design with Verilog

Most Likely Learning Hurdle

May try to write HDL code as if it will eventually be executed by some mysterious processor device in the FPGA Code is written sequentially (like a program), but you are simply writing descriptions of the various hardware entities in your system

Aug 9, 2001

FPGA System Design with Verilog

Design Methodologies:
1. Top Down Approach 2. Bottom Up Approach

Modern Project Methodology

Always inst1 inst2 inst3
Synthesis

Place and Route

clb 1
clb 2

Verilog Basics

helloWorld.v
module helloWorld ; initial begin $display ("Hello World!!!"); $finish; end endmodule System calls.
Modules are the unit building-blocks (components) Verilog uses to describe an entire hardware system. Modules are (for us) of three types: behavioral, dataflow, gate-level. We ignore the switch-level in this course. This module is behavioral. Behavioral modules contain code in procedural blocks.

This is a procedural block. There are two types of procedural blocks: initial and always. More than one statement must be put in a begin-end group.

Modeling Structures: Modules

Module
Input X Circuit Wire

Y
Z

Output O

Points to remember about modules in Verilog:

All code is contained in modules A module can invoke other modules Modules cannot be contained in another module

Module declaration
Input X Y Z

Module
Circuit Wire Output O

Module name module sample (X,Y,Z,O); input X,Y,Z; output O; // Describe the circuit using logic symbols assign O = (X^Y)&Z; endmodule

Typical Module Components Diagram

Module name, Port list (optional, if there are ports) Port declarations Parameter list Declaration of variables (wires, reg, integer etc.) Instantiation of inner (lower-level) modules Structural statements (i.e., assign and gates) Procedural blocks (i.e., always and initial blocks) Tasks and functions endmodule declaration

Modeling Structure: Ports

Module Ports

Similar to pins on a chip Provide a way to communicate with outside world Ports can be input, output or inout
Module AND (i0, i1, o); input i0, i1; output o; i0 o i1

endmodule

Modeling Structure: Instances

Module instances

Verilog models consist of a hierarchy of module instances In C++ speak: modules are classes and instances are objects
AND3

i0 i1 i2 o

Module AND3 (i0, i1, i2, o); input i0, i1, i2; output 0; wire temp; AND a0 (temp,i0,i1)); AND a1 (o,i2,temp); endmodule

Port Connection

Connect module port by order list

FA1 fa1(c_o, sum, a, b, c_i);

Connect module port by name (Recommended)

Usage: .PortName (NetName)

FA1 fa2(.A(a), .B(b), .CO(c_o), .CI(c_i), .S(sum));

System Tasks

$monitor

$monitor ($time,"%d %d %d",address,sinout,cosout); Displays the values of the argument list whenever any of the arguments change except $time. $display ("%d %d %d",address,sinout,cosout); Prints out the current values of the signals in the argument list $finish Terminate the simulation

$display

$finish

System Tasks

$display examples:

$display(Hello Verilog World!);

Output: Hello Verilog World!

$display($time);
Output: 230

reg [0:40] virtual_addr; $display(At time %d virtual address is %h, $time, virtual_addr);
Output: At time 200 virtual address is 1fe000001c

System Tasks

$monitor Examples:
initial begin $monitor($time, Value of signals clock=%b, reset=%b, clock, reset); end

Output: 0 value of signals clock=0, reset=1 5 value of signals clock=1, reset=1 10 value of signals clock=0, reset=0

Lexicography

Comments:
// Comment

Two Types:

/* These comments extend

over multiple lines. Good

for commenting out code */

Character Set:

0123456789ABCD..YZabcd...yz_$ Cannot start with a number or $

Number Representation

Format: <size><base_format><number> <size> - decimal specification of bits count

Default: unsized and machine-dependent but at least 32 bits

<base_format> - ' followed by arithmetic base of number

d or D decimal (default if no base format given) h or H hexadecimal o or O octal b or B binary

Number Representation

Format: <size><base_format><number> <number> - value given in base of base format

_ can be used for reading clarity x and z are automatically extended

Number Representation

Examples:

6b010_111 8b0110 4bx01 16H3AB 24 5O36 16Hx 8hz

gives 010111 gives 00000110 gives xx01 gives 0000001110101011 gives 00011000 gives 11110 gives xxxxxxxxxxxxxxxx gives zzzzzzzz

Data Types

Nets and Registers Vectors Integer, Real, and Time Register Data Types Arrays Memories Parameters Strings

Value Set in Verilog

4-value logic system in Verilog :
0

Nets

Used to represent connections between HW elements

Values continuously driven on nets

Default: One-bit values

Keyword: wire

unless declared as vectors For trireg, default is x wire a; wire b, c; wire d=1b0;

Default value: z

Examples

Registers

Registers represent data storage elements

Retain value until next assignment NOTE: this is not a hardware register or flipflop Keyword: reg Default value: x Example:
reg reset; initial begin reset = 1b1; #100 reset=1b0; end

Vectors

Net and register data types can be declared as vectors (multiple bit widths) Syntax:

wire/reg [msb_index : lsb_index] data_id;

Example
wire a; wire [7:0] bus; wire [31:0] busA, busB, busC; reg clock; reg [0:40] virtual_addr;

Vectors (contd)

Consider
wire [7:0] bus; wire [31:0] busA, busB, busC; reg [0:40] virtual_addr;

Access to bits or parts of a vector is possible:

busA[7] bus[2:0] // three least-significant bits of bus // bus[0:2] is illegal. virtual_addr[0:1] /* two most-significant bits * of virtual_addr */

Integer, Real, and Time Register Data Types

Integer

Keyword: integer Very similar to a vector of reg

integer variables are signed numbers reg vectors are unsigned numbers Designer can also specify a width:
integer [7:0] tmp;

Bit width: implementation-dependent (at least 32-bits)

Examples:
integer counter; initial counter = -1;

Integer, Real, and Time Register Data Types (contd)

Real

Keyword: real Values:

Default value: 0 Decimal notation: 12.24 Scientific notation: 3e6 (=3x106)

Cannot have range declaration Example:

real delta; initial begin delta=4e10; delta=2.13; end integer i; initial i = delta; // i gets the value 2 (rounded value of 2.13)

Integer, Real, and Time Register Data Types (contd)

Time

Used to store values of simulation time Keyword: time Bit width: implementation-dependent (at least 64) $time system function gives current simulation time Example:
time save_sim_time; initial save_sim_time = $time;

Arrays

Syntax:
<data_type> <var_name>[start_idx : end_idx];

Allowed in reg, integer, time, real and vector register data types.
Examples:
integer count[0:7]; reg bool[31:0]; time chk_point[1:100]; reg [4:0] port_id[0:7]; integer matrix[4:0][4:0]; // two dimensional array count[5] chk_point[100] port_id[3]

Note the difference between vectors and arrays

Data Types ~ summary

Data Values: Wire

Synthesizes into wires Used in structural code

module sample (a,b,c,d); input a,b; output c,d; wire [7:0] b; reg c,d; integer k;

0,1,x,z

Reg
May synthesize into latches, flip-flops or wires Used in procedural code

Integer Input, Output, inout

32-bit integer used as indexes

Defines ports of a module (wire by default)

Variable Declaration

Declaring a net
wire [<range>] <net_name> [<net_name>*]; Range is specified as [MSb:LSb]. Default is one bit wide

Declaring a register
reg [<range>] <reg_name> [<reg_name>*];

Declaring memory
reg [<range>] <memory_name> [<start_addr> : <end_addr>];

Examples
reg r; // 1-bit reg variable wire w1, w2; // 2 1-bit wire variable reg [7:0] vreg; // 8-bit register reg [7:0] memory [0:1023]; a 1 KB memory

Ports and Data Types

Correct data types for ports

Module

Register/net

net input

register/net
output

net

net

inout
net

Operators

Arithmetic:

*,+,-, /,%

Relational
Bit-wise Operators

<,<=,>,>=,==, !=
Not: ~ XOR: ^ And : & 5b11001 & 5b01101 ==> 5b01001 OR: | XNOR: ~^ or ^~

reg [3:0] a, b, c, d; wire[7:0] x,y,z; parameter n =4; c = a + b; d = a *n;

If(x==y) d = 1; else d =0;

d = a ~^ b; if ((x>=y) && (z)) a=1; else a = !x;

Logical Operators

Returns 1or 0, treats all nonzero as 1

! : Not && : AND || : OR
27 && -3 ==> 1

Operators

Reduction Operators:

Unary operations returns single-bit values & : and | :or ~& : nand ~| : nor ^ : xor ~^ :xnor

module sample (a, b, c, d); input [2:0] a, b; output [2;0] c, d; wire z,y; assign z = ~| a; c = a * b; If(a==b) d = 1; else d =0; d = a ~^ b; if ((a>=b) && (z)) y=1; else y = !x;

Shift Operators Concatenation Operator

Shift Left: << Shift right: >>

{ } (concatenation) { n{item} } (n fold replication of an item)

Conditional Operator Implements if-then-else statement

(cond) ? (result if cond true) : (result if cond false)

assign d << 2; //shift left twice assign {carry, d} = a + b; assign c = {2{carry},2{1b0}}; // c = {carry,carry,0,0}
assign c= (inc==2)? a+1:a-1;

Net Concatenation
Module B
Module A
3o7 Representations {b[3:0],c[2:0]} {a,b[3:0],w,3b101} {4{w}} {b,{3{a,b}}} Meanings
{b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]} {a,b[3] ,b[2] ,b[1] ,b[0],w,1b1,1b0,1b1} {w,w,w,w} {b,a,b,a,b,a,b}

Module C

Gate Level Modelling

Logic circuit can be described using basic logic gates. The module is a text description of the circuit layout. Verilog has all the standard gates

and, or, xor, not,

nand nor xnor buf

Primatives

The standard logic gates are Verilog system primatives. It is possible to specify new user-defined primatives (UDPs). UDPs are specified by there truth-table. UDPs may only have one output.

Using a Primative

A Primative by itself is not a module. To use it (e.g. for testing), it needs to be instantiated in a module. Its not necessary to explicitly give a name while instantiating a primitive. e.g. and (op,in1,in2); not (op,in);

Example: Simple Circuit Diagram

Circuit to code

module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y, C); or g3(x,e,y); endmodule

Input signals

In order to simulate a circuit the input signals need to be known so as to generate an output signal. The input signals are often called the circuit stimulus. An HDL module is written to provide the circuit stimulus. This is known as a testbench.

Testbench

The testbench module includes the module to be tested. There are no input or output ports for the testbench. The inputs to the test circuit are defined with reg and the outputs with wire. The input values are specified with the keyword initial A sequence of values can be specified between begin and end.

Stimulus module for simple circuit

module stimcrct; reg A,B,C; wire x,y; Smpl_circuit cwd(A,B,C,x,y); initial begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; B = 1'b1; C = 1'b1; #100 $finish; end endmodule

Case Study: Full Adder

Ci 0 0

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Co 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

Co

Full Adder S

Ci

0 0 1 1 1 1

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Case Study: Full Adder

Co = AB + BCi + CiA
A B B Ci Ci A

Co

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Case Study: Full Adder

sum = a b ci
a b c sum

a b c

sum

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Case Study: Full Adder

Full Adder Connection

Instance ins_c from FA_co Instance ins_s from FA_sum

full adder carry out connection co

a b b c c a

a b c

sum connection sum

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2 to 1 multiplexer

Write the Verilog description for 2 to 1 multiplexer.

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