2012 IEEE Symposium on Wireless Technology and Applications (ISWTA), September 23-26, 2012, Bandung, Indonesia

High Efficiency CMOS Class E Power Amplifier Using 0.13 m Technology

S.A.Z Murad, M.F Ahamd, M. Mohamad Shahimin, R.C Ismail and K.L Cheng
School of Microelectronic Engineering, Universiti Malaysia Perlis, Kampus Pauh Putra, 02600 Arau, Perlis, Malaysia sohiful@unimap.edu.my
AbstractThis paper presents the design of a 2.4-GHz CMOS Class E power amplifier (PA) for wireless applications in Silterra 0.13-m CMOS technology. The Class E PA proposed in this paper is a single-stage PA in a cascode topology in order to minimize the device stress problem. All transistors are arranged in parallel to decrease on-resistance for high efficiency with onchip input and output impedance matching. The simulation results indicate that the PA delivers 11.9 dBm output power and 53% power added efficiency (PAE) with 1.3-V power supply into a 50- load. The chip layout is 0.27 mm. Keywords-component; Class E; power amplifier; Silterra; output power; power added efficiency

R.Sapawi
Department of Electronics, Faculty of Engineering, Universiti Malaysia Sarawak, 94300 Kota Samarahan, Sarawak, Malaysia srohana2000@yahoo.com

stresses MOS devices. Safe device operating conditions can be guaranteed by decreasing supply voltage is usually less than the maximum available, at the price of efficiency degradation [1,5]. Cascode configurations have been used to overcome the device stress problem in MOS devices [1]. Most CMOS PAs that are published choose differential topology to obtain high linearity watt range [6]. Since the components driven by the PA and the antenna input are still single-ended, such a topology still requires off-chip baluns for converting signals from single-ended to differential and vice versa [7]. Therefore, fully integrated CMOS chip is difficult to realize. However, on-chip baluns can be integrated in differential topology for converting signals, but the design becomes complicated and increased the chip size [1],[8]. This paper describes a 2.4 GHz Class E single-stage PA designed using Silterra 0.13-m CMOS process. The proposed design employed cascode topology to increase breakdown voltage and the power stage transistors are arranged in parallel to decrease the switch on-resistance. This method helps to reduce the losses thus increase efficiency. II. CIRCUIT DESIGN The complete schematic of the proposed Class E PA singlestage cascode topology is shown in Fig. 1. Cin and Lin are part of the on-chip input matching. Rb is a bias resistance for M1.

I.

INTRODUCTION

Recently, wireless systems demand a low cost, compact, power efficient, high integration and reliable consumers devices. In addition, more and more signal processing is done in CMOS and high levels of integration are desired for reducing a cost and achieving compact systems. Hence, the wireless transceivers need to merge as many components as possible in a single chip using low cost technology. Therefore, there is a demand in utilizing CMOS PAs in a single chip transceiver called system on chip (SoC). However, as the down-scaling of MOS devices continues, the CMOS PA is not the optimum technology of choice due to the problem such as low oxide breakdown voltage, low current drive capability, substrate coupling, low quality and high tolerances of on-chip passives [1][2]. Although a lot of researches have been conducted recently to realize fully integration of PAs into SoC, unfortunately it is still a major challenge [3], particularly when designing in GHz frequencies range. In CMOS, Class E PA is the most favored candidates among all classes of switching mode power amplifiers (Class D & Class F) due to their circuit simplicity and excellent PAE [4]. High PAE is important because PAs typically dominate the power consumption in a wireless transmitters system. However, the linearity is very poor due to the switching nature, thus the systems with the constant envelope modulation scheme such as FSK (or FM) are most suitable for switchedmode amplifiers. Furthermore, signal swing in a Class E PA can be two or three times the supply voltage that seriously

Figure 1. Complete schematic of the proposed single-stage Class E PA.

978-1-4673-2210-2/12/$31.00 2012 IEEE

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2012 IEEE Symposium on Wireless Technology and Applications (ISWTA), September 23-26, 2012, Bandung, Indonesia

The power stage is implemented by cascode topology consists of common-source (CS) amplifier, M1 and commonre is employed for gate (CG) amplifier, M2. A cascode structur improving the breakdown voltage. The maximum m voltage between the drain and source of M1 and M2 M is 1.3 V, so the drains of M2 to ground can sustain about 2.6 6 V. This topology significantly improves the breakdown volt tage. Cshunt is a shunt capacitor calculated using the equation n in [9]. However, the calculated value does not include the par rasitic capacitor of M1 and M2, the optimization is needed to achieve high h on-resistance can efficiency and high output power. The switch be minimized by increasing the size of a switch transistor. Thus, to optimize the performance of the power stage altogether, thirteen transistors in parallel for CS and nine A devices have a transistors in parallel for CG were selected. All maximum width of 10 m and minimum le ength of 0.13 m. The gate of M1 is biased at 0.5 V, M2 is biased through resistor R, and the Vdd for M2 is 1.3 V. The design load network for the output stage is based on the selected Vdd, frequency, and the wanted output power. The d using equation in values of Cshunt, Ls, and Cs were calculated [9]. Ls and Cs is a series resonant network is designed based on 1 at frequency 2.4 2 GHz. The finite the equation of DC inductance Ldc is 6 nH connecting the CG C drain to the DC supply connection. s output matching The last part of the proposed design is using L-matching network. This network co onsists of inductor Lo and capacitor Co is employed due to its circuit simplicity. r reflection The impedance matching is important in reducing power loss and delivering as much as poss sible power to the load [12]. This matching network is caref fully optimized to ensure that the optimization resistance [4] is converted to 50 e output matching standard load at RF output terminal. The elements can be derived using equations in [1 12]. III. SIMULATION RESULT TS The circuit design of the Class E si ingle-stage PA is simulated using Mentor Graphics simulator using u Silterra 0.13m CMOS process. Fig. 2 shows the simul lated drain voltage and current waveform of the power stage. Class E operation rlapping with each wherein the voltage and current are not over other can be observed. On the other hand d, the voltage and current are not maximum level at the same e time, that is; the power dissipation or the product of drain cu urrent and voltage are minimized. Therefore, high efficiency can n be obtained. The minimum voltage is non-zero because of th he transistors onresistance. Fig. 3 shows the simulation result for the output power I can be seen that (Pout) and PAE versus input power (Pin). It the maximum output power is 11.9 dBm with h 53% PAE for an input power of 0 dBm. The output power is increasing i with the input power, however the PAE is decrease ed when the input power beyond 0 dBm. The degradation of PAE P is due to the parasitics effects.

14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00

Current Pout e Voltage

60.00 50.00 30.00 20.00 10.00 0.00 PAE (%) 60 50 40 30 20 10 0 PAE (%) 10 60 50
Pout PAE

Pout (dBm)

40.00

2 2.1 2.2 2.3 2.4 2 2.6 2.7 2.8 Frequen ncy 2.5 (GHz)
Figure 2. Transient response for drain current and drain voltage of M2.

14 12 10 Pout (dBm) 8 6 4 2 0 -20 -15 -10 -5 0 Pin n (dBm) 5

Pout PAE

Figure 3. Output power and a PAE versus input power.

The output power and PA AE versus supply voltage are shown in Fig. 4, the output power changes approximately proportional to Vdd, from 9 dB Bm to 14 dBm when the supply voltage is swept from 1.0 V to o 1.6 V. It can be noted that the output power can be controlle ed through the supply voltage. Finally, Fig. 5 shows the simu ulated output power and PAE of the PA as a function of freque ency when the input power is 0 dBm. The output power an nd PAE are not significantly changing between the frequen ncies' ranges of 2.352.45 GHz. Therefore, this PA obtains 100 MHz bandwidth. 16 14 12 10 8 6 4 2 0 1.0 1.1 1.2 .3 1. 1.4

40 PAE (%) 30 20 10 0

Pout (dBm)

1.5

1.6

V (V) Vdd
Figure 4. Output power an nd PAE versus supply voltage.

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2012 IEEE Symposium on Wireless Technology and Applications (ISWTA), September 23-26, 2012, Bandung, Indonesia

TABLE I.

PERFORMANCE SUMMARY OF CMOS POWER AMPLIFIER [10] 0.13 CMOS 2.4 3.3 19.2 27.8 0.37 1.85 [11] 0.09 CMOS 2.55 2.5 20.1 43.6 N/A [12] 0.18 CMOS 2.4 1.8 21.09 57 N/A [13]* 0.13 CMOS 1.4-1.8 2.5 19.5 43 3 15 [14] 0.18 SiGe 2.4 2.0 22.4 33.4 2.6** 26 This work 0.13 CMOS 2.4 1.3 11.9 53.0 0.35 1.45

12 10 Pout (dBm) 8 6 4 2 0 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Frequency (GHz) Pout PAE

60 50 PAE (%) 40 30 20 10 0

Reference Technology (m) Frequency (GHz) Vdd (V) Pout (dBm) PAE (%) Chip size (mm) Cost (USD) /100 dies

Figure 5. Output power and PAE as a function of frequency.

*Post-layout simulation results ** Estimation from the layout.

Table 1 shows the comparison of performances of the previously reported Class E PA and this work. The proposed design obtains good efficiency with the smaller chip size when compare with the previous work. The layout of the proposed Class E PA is presented in Fig. 6. The chip area, including the pads is 0.84 mm 0.42 mm; this layout is going to tape out for fabrication.

ACKNOWLEDGMENT The authors wish to express their appreciation to the support and contributions from those who assist in this research especially Universiti Malaysia Perlis (UniMAP) for providing the incentive short term research grant (9009-00002) and FRGS grant (9003-00301) that enabled the production of this article.

REFERENCES
[1] A.Mazzanti, L.Larcher,R.Brama & F.Svelto, Analysis of reliability and power efficiency in cascode class-E PAs, IEEE Journal of Solid-State Circuits, vol. 41, no.5, pp. 1222-1229, May 2006. [2] Tirdad Sowlati & Domine M.W. Leenaerts,A 2.4 GHz 0.18um CMOS self-biased cascode PA, IEEE Journal of Solid State Circuit, vol.38, no. 8, pp. 1318-1324, August 2003. [3] Hafez Found, Abdel-Hali Zekry and Khalid Fawzy, Self-Biased 0.13m CMOS 2.4-GHz Class E Cascode Power Amplifier, 26th National Radio Science Conference (NRSC 2009), 17-19 March, 2009. [4] Sohiful Anuar Zainol Murad, Ramesh K. Pokharel, Haruichi Kanaya, Keiji Yoshida and Oleg Nizhnik, A 2.4-GHz 0.18-m CMOS Class E single-ended switching power amplifier with a self-biased cascode, Int. J. Electronic. Commun. (AEU), vol. 64, pp. 813-818, 2010. [5] K.L.R. Mertens and M.S.J. Steyaert, A 700 MHz 1-W Fully differential CMOS Class E Power Amplifier, IEEE Journal of Solid State Circuits vol. 37, pp. 137-141, 2003. [6] Riccardo Brama, Luca Larcher, Andrea Mazzanti & Francesco Svelto, A 30.5 dBm 40% PAE CMOS class E PA with integrated balun for RF applications, IEEE Journal of Solid-State Circuits, vol. 43, no. 8, August 2008. [7] Tang Tat Hung & Mourad N.El-Gamal, Class E PA for RF applications, Proc. of the 2003 Int. Symposium on Circuits and Systems, ISCAS '03, vol.1, pp. I-449 - I-452, 25-28 May 2003. [8] P. Reynaert and M.S.J Steyaert,A 2.45-GHz 0.13-m CMOS PA with parallel amplification, IEEE Journal Of Solid-State Circuits, vol. 42, no. 3, pp. 551-562, March 2007. [9] Phairoj Leungvongsakorn and Apinunt Thanachayanont. A 0.1-W CMOS Class-E Power Amplifier for Bluetooth Applications. TENCON IEEE Conference on Convergent Technology for Asia-Pacific Region 2003. p. 1348-51. [10] S.A.Z Murad, R.K Pokharel, H. Kanaya and K. Yoshida, A 2.4 GHz 0.18-m CMOS Class E single-ended power amplifier without sipral inductors, IEEE 2010 10th Topical Meeting on Silicon Monolithic

Figure 6. Layout of the proposed Class E PA on 0.13-m CMOS tehcnology.

IV.

CONCLUSION

In this paper, a 2.4 GHz single stage Class E PA with parallel transistors for wireless applications in the Silterra 0.13m CMOS process is presented. The proposed topology employed cascode structure to overcome the device stress problem of submicron CMOS transistors and both the input, and the output matching network have been designed on-chip. The use of parallel transistors helps to decrease the onresistance switching thus the high efficiency can be obtained. The simulation results show that the proposed PA can deliver 11.9 dBm output power with the maximum PAE of 53%. Besides, it has very low supply voltage. The proposed PA can be used for wireless communication systems such as Bluetooth's mobile phone and integratable with other RF transceivers.

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Integrated Circuits in RF Systems (SIRF 2010), pp. 25-28, 11-13 Jan, 2010. [11] Danish Kalim, Denis Erguvan and Renato Negra, Study on CMOS Class-E power amplifiers for LTE applications, German Microwave Conference, pp. 186-189, 15-17 March 2010. [12] Reza Meshkin, Alireza Saberkari, Mohammad Niaboli-Guilani, A Novel 2.4 GHz CMOS Class-EPower Amplifier with Efficient Power Control for Wireless Communcations, 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 599-602, 12-15 Dec. 2010.

[13] H. R. Khan, A. Raheem Qureshi, Q. Wahab, A Fully Integrated Class-E Power Amplifier in 0.13um CMOS Technology, IEEE 9th International New Circuits and Systems Conference (NEWCAS), pp. 410-413, 26-29 June 2011. [14] Su Jie, et al, A 2.4 GHz High Efficient Monolithic Class E Power Amplifier, Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 271 - 274, 22-24 Sept. 2010.

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