27/12/12

Shift Register

Shift Register
Well, not just a shift register. This month's model is used to highlight the creation of parameterisable components and the modelling of bidirectional ports. The bidirectional port is modelled as a separate block from the main shifter function as a conditional continuous assignment. Notice that the high impedance state is modelled as {Length{1'bz}} rather than the more obvious Length'bz. This is because a parameter cannot be used as the vector w idth in Verilog. Ho hum! How ever, 'bz is quite legal... The shifter function is modelled as a clocked alw ays block The >> operator is used to present more succinct code than using concatenation w ould allow . The Length parameter is used to parameterise the Data bidirectional port and the Reg register. Note that Reg is legitimate as a reg object name as Verilog is case-sensitive. But Reg is not a good name for a reg object, a better name w ould be shift_reg, perhaps. So, one shift register. Parameterisable. Bidirectional. And synthesisable. Your mission, should you choose to accept it, is to modify the Verilog code to create a completely parameterisable, bidirectional shift register. Yes, bidirectional shift (shift left, as w ell as shift right) in addition to bidirectional I/O. This Web page w ill NOT self-destruct in five seconds! You are w elcome to use the source code w e provide but you must keep the copyright notice w ith the code (see the Notices page for details). / /S h i f t e r / / / /+ + / /| C o p y r i g h t1 9 9 6D O U L O S | / /| L i b r a r y :S e q u e n t i a l | / /| d e s i g n e r:J o h nA y n s l e y | / /+ + m o d u l eS h i f t e r( C l k ,E N ,W R ,R D ,S I ,S O ,D a t a ) ; / /s y n o p s y st e m p l a t e p a r a m e t e rL e n g t h=1 ; i n p u tC l k ,E N ,W R ,R D ,S I ; o u t p u tS O ; i n o u t[ L e n g t h 1 : 0 ]D a t a ; r e gS O ; r e g[ L e n g t h 1 : 0 ]R e g ; a s s i g nD a t a=! R D?R e g:{ L e n g t h { 1 ' b z } } ; a l w a y s@ ( p o s e d g eC l k ) i f( ! E N ) b e g i n S O< =R e g [ 0 ] ; R e g=R e g> >1 ; R e g [ L e n g t h 1 ]=S I ; e n d e l s ei f( ! W R ) R e g=D a t a ;
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Shift Register

a l w a y s@ ( W Ro rE N ) i f( ! W R&! E N ) $ d i s p l a y ( " E r r o r ,W ra n dE nb o t ha c t i v e " ) ; e n d m o d u l e To dow nload the Verilog source code for this month's Model of the Month, click here. Your e-mail comments are w elcome - send email Copyright 1995-2002 Doulos Copyright 2005-2012 Doulos. All rights reserved.

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