27/12/12

Simple RAM Model

Simple RAM Model

This month, a simple RAM model, w ritten in Verilog. Follow ing on from last month's introduction to parameterisation, the RAM model presented here is parameterisable in terms of memory depth and w ordlength. Memory depth is parameterised using the AddressSize parameter, w hilst WordSize is used to parameterise the w ordlength. The declaration, r e g[ W o r d S i z e 1 : 0 ]M e m[ 0 : 1 < < A d d r e s s S i z e ] ; defines the size of the memory block. Note the use of the << operator to provide a convenient mechanism for implementing 2N; there is no exponentiation operator in Verilog as there is in VHDL. Just like the shift register model from November, the parameterisable bidirectional port is modelled as a conditional assignment. This assignment effectively models the read process from the RAM. The first alw ays block models the w rite process. The second provides a simple simultaneous read-w rite check. Note that it is not possible address individual bits in the memory block using tw o-dimensional addressing as in VHDL. In Verilog, you need to create a temporary reg object for the memory w ord and then access a bit or a bit-select from that temporary reg object. Oh, yes. How about a timing diagram?

You are w elcome to use the source code w e provide but you must keep the copyright notice w ith the code (see the Notices page for details). / /R A MM o d e l / / / /+ + / /| C o p y r i g h t1 9 9 6D O U L O S | / /| L i b r a r y :M e m o r y | / /| d e s i g n e r:J o h nA y n s l e y | / /+ + m o d u l eR a m C h i p( A d d r e s s ,D a t a ,C S ,W E ,O E ) ; p a r a m e t e rA d d r e s s S i z e=1 ; p a r a m e t e rW o r d S i z e=1 ;
www.doulos.com/knowhow/verilog_designers_guide/models/simple_ram_model/

27/12/12

Simple RAM Model

i n p u t[ A d d r e s s S i z e 1 : 0 ]A d d r e s s ; i n o u t[ W o r d S i z e 1 : 0 ]D a t a ; i n p u tC S ,W E ,O E ; r e g[ W o r d S i z e 1 : 0 ]M e m[ 0 : 1 < < A d d r e s s S i z e ] ; a s s i g nD a t a=( ! C S& &! O E )?M e m [ A d d r e s s ]:{ W o r d S i z e { 1 ' b z } } ; a l w a y s@ ( C So rW E ) i f( ! C S& &! W E ) M e m [ A d d r e s s ]=D a t a ; a l w a y s@ ( W Eo rO E ) i f( ! W E& &! O E ) $ d i s p l a y ( " O p e r a t i o n a le r r o ri nR a m C h i p :O Ea n dW Eb o t ha c t i v e " ) ; e n d m o d u l e To dow nload the Verilog source code for this month's Model of the Month, click here. Your e-mail comments are w elcome - send email Copyright 1995-2002 Doulos Copyright 2005-2012 Doulos. All rights reserved.

www.doulos.com/knowhow/verilog_designers_guide/models/simple_ram_model/

2/2