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8 bit x 8 bit Pipelined Multiplier

8-bit x 8-bit Pipelined Multiplier

Briefly interrupting the Built-in Self Test (BIST) theme, this month w e present a synthesizable model of an 8-bit x 8-bit pipelined multiplier in Verilog. Although the design is synthesizable as is, a synthesis tool w ith a re-timing capability is required in order to create a pipelined multiplier w ith the pipeline registers evenly distributed throughout the design. You can of course remove the p i p e l i n e _ s t a g e salw ays block and use the u n _ p i p e l i n e d _ o u t p u tassignment. You are w elcome to use the source code w e provide but you must keep the copyright notice w ith the code (see the Notices page for details). ` t i m e s c a l e1 n s / 1 p s m o d u l em u l t _ p i p e d _ 8 x 8 _ 2 s C( a ,b ,c l k ,r e s e t ,y ) ; i n p u t [ 7 : 0 ]a , b ; i n p u tc l k , r e s e t ; o u t p u t [ 1 5 : 0 ]y ; / / / /F u n c t i o n :a l w a y s@p o s e d g ec l k / / y ( t = 0 )=a ( t 8 )*b ( t 8 ) / / / /S i m u l a t i o n :P A S S E D / /S y n t h e s i s :N e e d sr e t i m i n gf e a t u r ei n / / s y n t h e s i st o o l / / / / r e g [ 7 : 0 ]a R [ 8 : 0 ] ; r e g [ 7 : 0 ]b R [ 8 : 0 ] ; r e g [ 1 5 : 0 ]y R [ 8 : 0 ] ; a l w a y s@( p o s e d g ec l k )/ /p i p e l i n e _ s t a g e s b e g i n a R [ 7 ]=a R [ 6 ] ;/ /p i p e l i n es t a t e m e n t s b R [ 7 ]=b R [ 6 ] ; y R [ 7 ]=y R [ 6 ] ; a R [ 6 ]=a R [ 5 ] ; b R [ 6 ]=b R [ 5 ] ; y R [ 6 ]=y R [ 5 ] ; a R [ 5 ]=a R [ 4 ] ; b R [ 5 ]=b R [ 4 ] ; y R [ 5 ]=y R [ 4 ] ; a R [ 4 ]=a R [ 3 ] ; b R [ 4 ]=b R [ 3 ] ; y R [ 4 ]=y R [ 3 ] ; a R [ 3 ]=a R [ 2 ] ; b R [ 3 ]=b R [ 2 ] ;
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8 bit x 8 bit Pipelined Multiplier

y R [ 3 ]=y R [ 2 ] ; a R [ 2 ]=a R [ 1 ] ; b R [ 2 ]=b R [ 1 ] ; y R [ 2 ]=y R [ 1 ] ; a R [ 1 ]=a R [ 0 ] ; b R [ 1 ]=b R [ 0 ] ; y R [ 1 ]=y R [ 0 ] ; / /m u l t i p l yr e s u l t( a * b )a p p e a r sa f t e r+ c l k a R [ 0 ]=a ; b R [ 0 ]=b ; y R [ 0 ]=m u l t i p l y _ 8 x 8 _ 2 s C( a R [ 0 ] , b R [ 0 ] ) ; e n d f u n c t i o n [ 1 5 : 0 ]m u l t i p l y _ 8 x 8 _ 2 s C ; i n p u t [ 7 : 0 ]a , b ; r e g [ 7 : 0 ]a _ m a g , b _ m a g ; r e g [ 1 4 : 0 ]y _ m a g ; r e g [ 1 4 : 0 ]y _ n e g ; b e g i n c a s e( a [ 7 ] ) 0 :a _ m a g=a [ 6 : 0 ] ; 1 :a _ m a g=1 2 8-a [ 6 : 0 ] ; / /m a x ( a _ m a g )=1 2 8 ,t h u s8b i t s e n d c a s e c a s e( b [ 7 ] ) 0 :b _ m a g=b [ 6 : 0 ] ; 1 :b _ m a g=1 2 8-b [ 6 : 0 ] ; e n d c a s e y _ m a g=a _ m a g*b _ m a g ; / /m a x ( y _ m a g )=1 6 3 8 4 ,t h u s1 5b i t s i f( ( a [ 7 ]^b [ 7 ] )&( y _ m a g! =0 ) )/ /i f( a*b )i sv eA N Dn o n z e r o b e g i n / /y _ m a g> = 1 ,< =1 6 2 5 6 ,t h u sn e e do n l y1 4b i t s y _ n e g=3 2 7 6 8-y _ m a g [ 1 3 : 0 ] ; / /m a x ( y _ n e g )=3 2 7 6 7 ,t h u sn e e d1 5b i t s m u l t i p l y _ 8 x 8 _ 2 s C={ 1 ' b 1 , y _ n e g } ; e n d e l s e m u l t i p l y _ 8 x 8 _ 2 s C=y _ m a g ; e n d e n d f u n c t i o n / / a s s i g ny=m u l t i p l y _ 8 x 8 _ 2 s C( a , b ) ;/ /u n _ p i p e l i n e d _ o u t p u t a s s i g ny=y R [ 7 ] ; e n d m o d u l e Here is a skeleton testbench architecture that can be used for testing purposes. ` t i m e s c a l e1 n s / 1 p s m o d u l em u l t _ p i p e d _ 8 x 8 _ 2 s C _ t b ; r e gc l o c k ,r e s e t ;/ /r e s e t=a c t i v eH I G H r e g[ 7 : 0 ]a _ i n ,b _ i n ; w i r e[ 1 5 : 0 ]y _ o u t ; / /s t i m u l u s / /r e s p o n s ec h e c k i n g / /D U T m u l t _ p i p e d _ 8 x 8 _ 2 s CD U T( a _ i n ,b _ i n ,c l o c k ,r e s e t ,y _ o u t ) ; e n d m o d u l e

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8 bit x 8 bit Pipelined Multiplier

To dow nload the Verilog source code for this month's Model of the Month, click here. Your e-mail comments are w elcome - send email Copyright 1995-2002 Doulos Copyright 2005-2012 Doulos. All rights reserved.

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