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Synthesizing Latches

Synthesizing Latches
In the last section, if statements w ere used to describe simple combinational logic circuits. Synthesizing the Verilog code produced multiplexing circuits, although the exact implementation depends upon the synthesis tool used and the target architecture of the device. As w ell as enabling the creation of multiplexers, if statements can also be used to implement tristate buffers and transparent latches. In this article w e w ill look at how transparent latches are synthesized from if statements and how to avoid the inadvertent creation of latches w hen you meant to create combinational logic circuits from Verilog code containing if statements.

If Statements
In the processes that have been coded up so far, if-else statements rather than simple if statements have been used. Let's use a simple if statement rather than an if-else statement in an example you have already seen: r e gs e l ,a ,b ;

a l w a y s@( s e lo rao rb ) b e g i n:i f _ e l s e i f( s e l= =1 ) f=a ; e l s e f=b ; e n d becomes... r e gs e l ,a ,b ;

a l w a y s@( s e lo rao rb ) b e g i n:p u r e _ i f f=b ; i f( s e l= =1 ) f=a ; e n d

Note that the behaviour being described is the same. In the p u r e _ i falw ays block, finitially gets b . Only if s e lis active HIGH does fget a . This is perhaps a slightly odd w ay to describe a multiplexing circuit but it is accepted by all synthesis tools. Synthesis tools expect to create circuits responding to binary values. As far as a synthesis tool is concerned if s e lis 1 ais routed through to f . If sel is not 1 it must be 0 and thus sel being 0 leaves f being driven by the initial assignment from b.
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Let's lose the b input to the alw ays block so that w e have: r e gs e l ,a ;

a l w a y s@( s e l ,a ) b e g i n:l a t c h i n g _ i f i f( s e l= =1 ) f=a ; e n d

Incomplete Assignment
Now analyze the behaviour of the code. If s e lis 1, fgets a . But w hat happens w hen s e lis 0? Well, very simply, nothing! fdoes not and can not change. When s e lis fixed at 0, w e can change aas much as w e like, fw ill not be assigned the value of a . If w e suppose that an if statement synthesises to a multiplexer, then w e must be able to configure the multiplexer such that fonly gets the value of aw hen s e lis 1. This can be achieved by feeding back the multiplexer foutput back to the 0 input; in hardw are terms this is a transparent latch and this is exactly the hardw are synthesized by a synthesis tool given this Verilog code.

If the target architecture does not contain transparent latches the synthesis tool w ill generate multiplexer circuits that employ combinational feedback in order to mimic the latching behaviour required. Now , this is very w ell but w hat's really happening here? One minute if statements create multiplexers, the next they create latches. Well, it's not the if statements, but the process as a w hole that counts. If it is possible to execute an alw ays block w ithout assigning a value to a signal in that alw ays block, the reg variable w ill be implemented as a transparent latch. This is know n as incomplete assignment. Golden Rule 2: To synthesize combinational logic using an always block, all variables must be assigned under all conditions.

Simplifying code analysis

Suppose you are creating an alw ays block to describe combinational logic. This alw ays block consists of nested if-else statements as follow s: r e gf ,g ; a l w a y s@( s e lo rs e l _ 2o rs e l _ 3o rao rb ) b e g i n i f( s e l= =1 ) b e g i n f=a ; i f( s e l _ 2= =1 ) g=~a ; e l s e b e g i n g=~b ; i f( s e l _ 3= =1 ) g=a^b ; e n d e n d e l s e b e g i n i f( s e l _ 2= =1 ) g=a&b ; e l s e i f( s e l _ 3= =1 ) g=~ ( a&b ) ; / /o o p s !n oe l s e
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Synthesizing Latches

/ /e l s e / / g=. . . f=b ; e n d e n d Will you get transparent latches on the f and g outputs? Not easy is it? If you look carefully you w ill see that in fact, g is latched w hen sel is 0, sel_2 is 0 and sel_3 is 0. The oops!' comment should help you to see w here the complete assignment is NOT made.

Default Assignment
Fortunately, it is possible to save yourself the bother of scouring through the alw ays block code to locate possible incomplete assignments by setting variables to default values at the start of the alw ays block. Using this approach you may get undesired functionality if you have missed out an assignment (w hich should be easy to fix) as opposed to unw anted transparent latches. For our current example, a l w a y s@( s e lo rs e l _ 2o rs e l _ 3o rao rb ) b e g i n / /d e f a u l tv a l u e sa s s i g n e dt of ,g f=b ; g=a&b ; i f( s e l= =1 ) b e g i n f=a ; i f( s e l _ 2= =1 ) g=~a ; e l s e b e g i n g=~b ; i f( s e l _ 3= =1 ) g=a^b ; e n d e n d e l s e i f( s e l _ 2= =1 ) g=a&b ; e l s e i f( s e l _ 3= =1 ) g=~ ( a&b ) ; e n d Prev Copyright 2005-2012 Doulos. All rights reserved.

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