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Verilog Tutorial: Harsha Perla

Verilog Loop Statements

Loop statements are used to control repeated execution of one or more statements. There are 4 types of looping stetements in Verilog: f o r e v e rs t a t e m e n t ;

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r e p e a t ( e x p r e s s i o n )s t a t e m e n t ; w h i l e ( e x p r e s s i o n )s t a t e m e n t ; f o r ( i n i t i a l _ a s s i g n m e n t ;e x p r e s s i o n ; s t e p _ a s s i g n m e n t )s t a t e m e n t ; We can combine more than one statements using b e g i n-e n dblock in an looping instruction. Looping statements should be used within a procedural block. forever Loop:

The forever instruction continuously repeats the statement that follows it. Therefore, it should be used with procedural timing controls (otherwise it hangs the simulation). Consider this example:
i n i t i a l b e g i n c l k=0 ; f o r e v e r# 5c l k=~ c l k ; e n d

repeat Loop: Repeats the following instruction for specified times. The number of executions is set by the expression or constant value. If expression evaluates to high impedance or un-known, then statement will not be executed.
i n i t i a l b e g i n x=0 ; r e p e a t (1 6) b e g i n # 2$ d i s p l a y ( " y =" ,y ) ; x=x+1 ; e n d e n d

while Loop: while loop repeats the statement until the expression returns true. If starts with false value, high impedance or unknown value, statement will not be executed.
i n i t i a l b e g i n x=0 ; w h i l e (x< =1 0) b e g i n # 2$ d i s p l a y ( " y =" ,y ) ; x=x+1 ;

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x=x+1 ; e n d e n d

for Loop: Executes initial_assignment once when the loop starts, Executes the statement or statement group as long as the expression evaluates as true and executes the step_assignment at the end of each pass through the loop. f o r ( i n i t i a l _ a s s i g n m e n t ;e x p r e s s i o n ;s t e p _ a s s i g n m e n t )s t a t e m e n t ; Syntax is similar to C language except that b e g i n e n dis used instead of { }to combine more than one statements. Remember that we don't have ++ operator in Verilog. f o r (i=0 ;i< =1 0 ;i + +) m e m [ i ]=0 ;

Prev. : if-else statements Verilog: Table of Contents Ch: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Next: Coding styles: Multiplexer example
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