Chapter 1

INTRODUCTION
Before I introduce you about VLSI I would like to tell you what IC (integrated circuit) is? A chip where many circuit components and the wiring that connects them are manufactured simultaneously is called an IC. Integrated circuits are used in almost all electronic equipment in use today and have revolutionized the world of electronics. A hybrid integrated circuit is a miniaturized electronic circuit constructed of individual semiconductor devices, as well as passive components, bonded to a substrate or circuit board. Integrated circuits were made possible by experimental discoveries which showed that semiconductor devices could perform the functions of vacuum tubes and by mid-20th-century technology advancements in semiconductor device fabrication the integration of large numbers of tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using electronic components. The integrated circuits mass production capability, reliability, and building-block approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. There are two main advantages of ICs over discrete circuits: cost and performance. Cost is low because the chips, with all their components, are printed as a unit by photolithography and not constructed as one transistor at a time. Furthermore, much less material is used to construct a circuit as a packaged IC die than as a discrete circuit. Performance is high since the components switch quickly and consume little power (compared to their discrete counterparts) because the components are small and close together

1.1 VLSI (VERY LARGE SCALE INTEGERATION) Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into billions of transistors. Common technologies used used in VLSI are CMOS, Bipolar, Bi CMOS etc.
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1.2 CHALLENGES FACED BY VLSI: As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon. Power usage/Heat dissipation As threshold voltages have ceased to scale with advancing process technology, dynamic power dissipation has not scaled proportionally. Maintaining logic complexity when scaling the design down only means that the power dissipation per area will go up. This has given rise to techniques such as dynamic voltage and frequency scaling (DVFS) to minimize overall power. Stricter design rules Due to lithography and etch issues with scaling, design rules for layout have become increasingly stringent. Designers must keep ever more of these rules in mind while laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses opting to switch to electronic design automation (EDA) tools to automate their design process.

1.3 VLSI DESIGN FLOW GRAPH:

figure-1.1 design flow

The design flow shown in Figure 1-1 is typically used by designers who use HDLs.

1.3.1 Design specificationsIn any design, specifications are written first. Specifications describe abstractly the functionality, interface, and overall architecture of the digital circuit to be designed. At this point, the architects do not need to think about how they will implement this circuit.

1.3.2 Behavioral descriptionA behavioral description is then created to analyse the design in terms of functionality, performance and compliance to standards, and other high-level issues. Behavioral descriptions are often written with HDLs. [2] New EDA tools have emerged to simulate behavioral descriptions of circuits. These tools combine the powerful concepts from HDLs and object oriented languages such as C++. These tools can be used instead of writing behavioral descriptions in Verilog HDL.

1.3.3 RTL descriptionThe behavioral description is manually converted to an RTL description in an HDL. The designer has to describe the data flow that will implement the desired digital circuit. From this point onward, the design process is done with the assistance of EDA tools.

1.3.4 Logic synthesis toolsLogic synthesis tools convert the RTL description to a gate-level netlist. A gate-level netlist is a description of the circuit in terms of gates and connections between them. Logic synthesis tools ensure that the gate-level netlist meets timing, area, and power specifications.

1.3.5 Gate level netlistThe gate-level netlist is input to an Automatic Place and Route tool, which creates a layout. The layout is verified and then fabricated on a chip.
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Thus, most digital design activity is concentrated on manually optimizing the RTL description of the circuit. After the RTL description is frozen, EDA tools are available to assist the designer in further processes. Designing at the RTL level has shrunk the design cycle times from years to a few months. It is also possible to do many design iterations in a short period of time. Behavioral synthesis tools have begun to emerge recently. These tools can create RTL descriptions from a behavioral or algorithmic description of the circuit. As these tools mature, digital circuit design will become similar to high-level computer programming. Designers will simply implement the algorithm in an HDL at a very abstract level. EDA tools will help the designer convert the behavioral description to a final IC chip. It is important to note that, although EDA tools are available to automate the processes and cut design cycle times, the designer is still the person who controls how the tool will perform. EDA tools are also susceptible to the "GIGO: Garbage In Garbage Out" phenomenon. If used improperly, EDA tools will lead to inefficient designs. Thus, the designer still needs to understand the nuances of design methodologies, using EDA tool to obtain an optimized design. 1.4 HDL (Hardware Description Language) For a long time, programming languages such as FORTRAN, PASCAL, and C were being used to described computer programs that were sequential in nature. Similarly in digital design field, designers felt the need for a standard language to describe the digital circuits. Thus Hardware Description Language(HDLs) came into existence. HDL allowed the designers to model the concurrency of proceses found in hardware elements. Hardware Description Languages such as Verilog HDL and VHDL became popular. Verilog HDL originated in 1983 at Gateway Design Automation. Later VHDL was developed under contract from DARPA.

1.5 Design using HDLs Efficiency gains realized using HDL means a majority of modern digital circuit design revolves around it. Most designs begin as a set of requirements or a high-level architectural diagram. Control and decision structures are often prototyped in flowchart applications, or entered in a state-diagram editor.The process of writing the HDL
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description is highly dependent on the nature of the circuit and the designer's preference for coding style. The HDL is merely the 'capture language'often begin with a high-level algorithmic description such as MATLAB or a C++ mathematical model. Designers often use scripting languages (such as Perl) to automatically generate repetitive circuit structures in the HDL language. Special text editors offer features for automatic indentation, syntax-dependent coloration, and macro-based expansion of

entity/architecture/signal declaration. The HDL code then undergoes a code review, or auditing. In preparation for synthesis, the HDL description is subject to an array of automated checkers. The checkers report deviations from standardized code guidelines, identify potential ambiguous code constructs before they can cause misinterpretation, and check for common logical coding errors, such as dangling ports or shorted outputs. This process aids in resolving errors before the code is synthesized. In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis tool has mapped the HDL description into a gate net list, this net list is passed off to the back-end stage. Depending on the physical technology (FPGA, ASIC gate array, ASIC standard cell), HDLs may or may not play a significant role in the back-end flow. In general, as the design flow progresses toward a physically realizable form, the design database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL description.

1.6 Simulating and Debugging HDL code To simulate an HDL model, an engineer writes a top-level simulation environment (called a testbench). At minimum, a testbench contains an instantiation of the model (called the device under test or DUT), pin/signal declarations for the model's I/O, and a clock waveform. The testbench code is event driven: the engineer writes HDL statements to implement the (testbench-generated) reset-signal, to model interface transactions (such as a hostbus read/write), and to monitor the DUT's output. An HDL simulator the program that executes the testbench maintains the simulator clock, which is the master reference for all events in the testbench simulation. Events occur only at the instants dictated by the testbench HDL (such as a reset-toggle coded into the testbench), or in reaction (by the model) to stimulus and triggering events. Modern HDL simulators have a full-featured graphical user interfaces, complete with a suite of debug tools. These allow
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the user to stop and restart the simulation at any time, insert simulator breakpoints (independent of the HDL code), and monitor or modify any element in the HDL model hierarchy. Modern simulators can also link the HDL environment to user-compiled libraries, through a defined PLI/VHPI interface. Linking is system-dependent (Win32/Linux/SPARC), as the HDL simulator and user libraries are compiled and link Design verification is often the most time-consuming portion of the design process, due to the disconnect between a device's functional specification, the designer's interpretation of the specification, and the imprecision of the HDL language. The majority of the initial test/debug cycle is conducted in the HDL simulator environment, as the early stage of the design is subject to frequent and major circuit changes. An HDL description can also be prototyped and tested in hardware programmable logic devices are often used for this purpose. Hardware prototyping is comparatively more expensive than HDL simulation, but offers a real-world view of the design. Prototyping is the best way to check interfacing against other hardware devices and hardware prototypes.

1.7 Design verifications with HDLs Design verification was a laborious, repetitive loop of writing and running simulation test cases against the design under test. As chip designs have grown larger and more complex, the task of design verification has grown to the point where it now dominates the schedule of a design team. Looking for ways to improve design productivity, the EDA industry developed the Property Specification Language. In formal verification terms, a property is a factual statement about the expected or assumed behavior of another object. Ideally, for a given HDL description, a property or properties can be proven true or false using formal mathematical methods. In practical terms, many properties cannot be proven because they occupy an unbounded solution space. However, if provided a set of operating assumptions or constraints, a property checker can prove (or disprove) more properties, over the narrowed solution space. The assertions do not model circuit activity, but capture and document the "designer's intent" in the HDL code. In a simulation environment, the simulator evaluates all specified assertions, reporting the location and severity of any violations. In a synthesis environment, the synthesis tool usually operates with the policy of halting synthesis upon
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any violation. Assertion-based verification is still in its infancy, but is expected to become an integral part of the HDL design toolset.

1.8 Importance of HDLs: A Hardware Description Language (HDL) is a software programming language used to model the intended operation of a piece of hardware. EDA tools are computer based software systems to design Very Large Scale Integrated circuits. Now EDA tools are available for almost every stage of VLSI design flow. But to start with we must convey design idea (that is in our mind) to EDA tool in such a way that the tool is able to understand that and generate a highly optimized design implementation. This transfer of idea from human beings to machines is called Design Entry. There are two methods of design entry: graphical and textual. Graphical method includes schematic entry and state diagram entry while textual method implies use of HDL's (Hardware Description Languages). Graphical method works fairly well up to a certain level of circuit complexity but in larger circuits they become cumbersome and time consuming.

1.9 Advantages of HDL: Compact description. Easy to edit Highly portable. Supports a higher level of abstraction. Rapid prototyping of design. Availability of extensive vendor libraries. Increasing capability of synthesis tools.

1.10 Disadvantages OF HDL No support for analog behavioral. Need to learn coding styles that ensures synthesizable results.

Chapter 2
VERILOG (VERIFY LOGIC)
In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL, is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits.

2.1 HISTORY OF VERILOG:

2.1.1 BEGINING: Verilog was invented by Phil Moorby and Prabhu Goel during the winter of 1983/1984 at Automated Integrated Design Systems (renamed to Gateway Design Automation in 1985) as a hardware modeling language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators.

2.1.2 VERILOG-95: With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed Verilog-95.
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2.1.3 VERILOG 2001: Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001. Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed-operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the boolean-algebra to determine its correct value). The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision-operators (case/if/else). Using generate/endgenerate, Verilog2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system-tasks. And finally, a few syntax additions were introduced to improve code-readability (eg. always @*, named-parameter override, C-style function/task/module header declaration). Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages.

2.1.4 VERILOG 2005: Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword). A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modeling with traditional Verilog.

2.1.5 SYSTEM VERILOG:

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SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid design-verification and design-modeling.

2.2 POPULARITY OF VERILOG HDL

Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers many useful features Verilog HDL is a general-purpose hardware description language that is easy to

learn and easy to use. It is similar in syntax to the C programming language. Designers with C programming experience will find it easy to learn Verilog HDL. Verilog HDL allows different levels of abstraction to be mixed in the same model.

Thus, a designer can define a hardware model in terms of switches, gates, RTL, or behavioral code. Also, a designer needs to learn only one language for stimulus and hierarchical design. Most popular logic synthesis tools support Verilog HDL. This makes it the

language of choice for designers. All fabrication vendors provide Verilog HDL libraries for postlogic synthesis

simulation. Thus, designing a chip in Verilog HDL allows the widest choice of vendors. The Programming Language Interface (PLI) is a powerful feature that allows the

user to write custom C code to interact with the internal data structures of Verilog. Designers can customize a Verilog HDL simulator to their needs with the PLI.

2.3 Advantages of Verilog HDLs

HDLs have many advantages compared to traditional schematic-based design. Designs can be described at a very abstract level by use of HDLs. Designers can

write their RTL description without choosing a specific fabrication technology.If a new technology emerges, designers do not need to redesign the circuit. They simply input the RTL description and create a new gate-level netlist, using the new fabrication technology and logic synthesis tool will optimize the circuit and timing for the new technology.
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By describing designs in HDLs, functional verification of the design can be done

early in the design cycle. Since designers work at the RTL level, they can optimize and modify the RTL description until it meets the desired functionality. This cuts down design cycle time significantly because the probability of hitting a functional bug at a later time in the gate-level netlist or physical layout is minimized.

Designing with HDLs is analogous to computer programming. A textual

description with comments is an easier way to develop and debug circuits. This also provides a concise representation of the design, compared to gate-level schematics. With rapidly increasing complexities of digital circuits and increasingly sophisticated EDA tools, HDLs are now the dominant method for large digital designs. [5] New tools and languages focused on verification have emerged in the past few years.These languages are better suited for functional verification.

2.4 Features of Verilog HDL

Verilog HDL is a general-purpose hardware description language that is easy to learn and easy to use. It is similar in syntax to the C programming language.

Verilog HDL allows different levels of abstraction to be mixed in the same

model.Thus, a designer can define a hardware model in terms of switches, gates, RTL, or behavioral code. Also, a designer needs to learn only one language for stimulus and hierarchical design.

Most popular logic synthesis tools support Verilog HDL. This makes it

thelanguage of choice for designers.

All fabrication vendors provide Verilog HDL libraries for postlogic synthesis

simulation. Thus, designing a chip in Verilog HDL allows the widest choice of vendors.

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The Programming Language Interface (PLI) is a powerful feature that allows the

user to write custom C code to interact with the internal data structures of Verilog. Designers can customize a Verilog HDL simulator[3] to their needs with the PLI.

2.5 Trends in HDLs

The speed and complexity of digital circuits have increased rapidly. EDA(Electronic Design Automation) tools take care of the implementation details. With designer assistance, EDA tools have become sophisticated enough to achieve a close-to-optimum implementation.

The most popular trend currently is to design in HDL at an RTL level, because logic synthesis tools can create gate-level netlists from RTL level design. Behavioral synthesis allowed engineers to design directly in terms of algorithms and the behaviour of the circuit, and then use EDA tools to do the translation and optimization in each phase of the design. Today, RTL design continues to be very popular. Verilog HDL is also being constantly enhanced to meet the needs of new verification methodologies.

Formal verification and assertion checking techniques have emerged. Formal verification applies formal mathematical techniques to verify the correctness of Verilog HDL descriptions and to establish equivalency between RTL and gate-level netlists. Assertion checkers allow checking to be embedded in the RTL code. This is a convenient way to do checking in the most important parts of a design.

New verification languages have also gained rapid acceptance. These languages combine the parallelism and hardware constructs from HDLs with the object oriented nature of C++. These languages also provide support for automatic stimulus creation, checking,

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and coverage. However, these languages boost the productivity of the verification process.

For very high-speed and timing-critical circuits like microprocessors, the gate-level netlist provided by logic synthesis tools is not optimal. In such cases, designers often mix gatelevel description directly into the RTL description to achieve optimum results. This practice is opposite to the high-level design paradigm, yet it is frequently used for high speed designs because designers need to squeeze the last bit of timing out of circuits, and EDA tools[4] sometimes prove to be insufficient to achieve the desired results.

Another technique that is used for system-level design is a mixed bottom-up methodology where the designers use either existing Verilog HDL modules, basic building blocks, or vendor-supplied core blocks to quickly bring up their system simulation. This is done to reduce development costs and compress design schedules.

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Chapter 3
HIERARCHICAL ARCHITECTURE OF VERILOG
3.1 DESIGN METHODOLOGY: There are two basic types of digital design methodologies: a top-down design methodology and a bottom-up design methodology. In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided. Figure 3-1 shows the top-down design process.

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TOP MODULE

SUB MODULE 1

SUB MODULE 2

SUB MODULE 3

cell

cell

cell

Sub Module 4

Sub Module5

cell

cell

cell

cell

cell

cell

cell

Figure-3.1- top down design methodology

In a bottom-up design methodology, we first identify the building blocks that are available to us.. These cells are then used for higher-level blocks until we build the toplevel block in the design. Figure 3-2 shows the bottom-up design process.

Figure-3.2- bottom-up design methodology

Typically, a combination of top-down and bottom-up flows is used. Design architects define the specifications of the top-level block. Logic designers decide how the design should be structured by breaking up the functionality into blocks and sub-blocks. At the
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same time, circuit designers are designing optimized circuits for leaf-level cells. They build higher-level cells by using these leaf cells. The flow meets at an intermediate point where the switch-level circuit designers have created a library of leaf cells by using 28 switches, and the logic level designers have designed from top-down until all modules aredefined in terms of leaf cells.

3.2 FIRST VERILOG PROGRAM: 3.2.1 PROGRAM OF THE HALF ADDER USING VERILOG:

in1 in2

Sum

Carry

Figure-3.3- half adder

module half adder (sum, carry, in1, in2) ; output sum, carry; input in1, in2; xor (sum, in1, in2); and (carry, in1, in2); endmodule

3.2.2 GENERAL SYNTAX FOR WRITING VERILOG PROGRAM: module Module Name (Port_List); ... ... <Module Internals> ... Endmodule
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3.3 MODULESModule is a basic functional unit in Verilog. A module can be seen as a design block with some inputs and outputs. How that block works is written inside that module. All the distinct blocks in design tree corresponds to a module in Verilog. So module is just like black box with input and output terminals and that black box interacts with the outside environment through these terminals only. The relationship between these input and output terminals is hidden from the environment. Every module definition begins with a keyword module and ends with keyword endmodule. Only within these two keywords functionality of a module is specified. Each module has a module name and port list. Module name is an identifier for that particular module and port list contains the list of all input and output terminals for the module.

Figure -3.4-components of module

To build a full adder from the half adder defined just now we have to create an instance of half adder module in full adder module. This instance is given a name and ports are connected appropriately. Certain predefined modules of basic hardware elements are
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provided in Verilog and we call them as primitives. These primitives can be instantiated inside modules in same way but giving them names is optional. So a module may contain instances of primitives and other modules.

3.4 FULL ADDER:

carry_in

HALF ADDER HALF ADDER

sum

a b

carry_out

Figure-3.5- block diagram of full adder using two half adders module full adder (sum, carry_out, a, b, carry_in); output sum, carry_out; input a, b, carry_in ; wire w1, w2, w3; half_adder ha1(w1, w2, a, b); half adder ha2 (sum, w3, w1, carry_in); or (carry_out, w2, w3); endmodule

SYNTAX: module Module Name (Port_List) ; <Port Declarations> <Internal Signals Declaration> <Functionality> endmodule

The port list in module definitions contains names of ports (terminals) only and we must specify whether they are input, output or bi-directional terminals. So port declarations are the first thing we write in module internals. Ports are declared using Verilog keywords
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input, output and inout. Keyword inout is used for bi-directional ports. All internal signals between various hardware units must be assigned some name and declared its type. So second thing we write in module internals is internal signal declaration. Then follows the actual module functionality.

3.5 INSTANCESA module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. In Example 4.1, the top-level block creates four instances from the T-flipflop (T_FF) template. Each T_FF instantiates a D_FF and an inverter gate. Each instance must be given a unique name. Note that // is used to denote single-line comments. Example 3.1 Module Instantiation // Define the top-level module called ripple carry // counter. It instantiates 4 T-flipflops. Interconnections are // shown in Section 2.2, 4-bit Ripple Carry Counter. module ripple_carry_counter(q, clk, reset); output [3:0] q; //I/O signals and vector declarations //will be explained later. input clk, reset; //I/O signals will be explained later. //Four instances of the module T_FF are created. Each has a unique //name.Each instance is passed a set of signals. Notice, that //each instance is a copy of the module T_FF. T_FF tff0(q[0],clk, reset); T_FF tff1(q[1],q[0], reset); T_FF tff2(q[2],q[1], reset); T_FF tff3(q[3],q[2], reset); Endmodule // Define the module T_FF. It instantiates a D-flipflop. We assumed // that module D-flipflop is defined elsewhere in the design. Refer // to Figure 2-4 for interconnections.
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module T_FF(q, clk, reset);\ //Declarations to be explained later output q; input clk, reset; wire d; D_FF dff0(q, d, clk, reset); // Instantiate D_FF. Call it dff0. not n1(d, q); // not gate is a Verilog primitive. Explained later. Endmodule

Chapter 4
BASIC CONCEPT
In this chapter, we discuss the basic constructs and conventions in Verilog. These conventions and constructs are used throughout the later chapters. These conventions provide the necessary framework for Verilog HDL. Data types in Verilog model actual data storage and switch elements in hardware very closely. This chapter may seem dry, but understanding these concepts is a necessary foundation for the successive chapters.

4.1 OPERATORS Operators are of three types: unary, binary, and ternary. Unary operators precede the operand. Binary operators appear between two operands. Ternary operators have two separate operators that separate three operands. a = ~ b; // ~ is a unary operator. b is the operand a = b && c; // && is a binary operator. b and c are operands a = b ? c : d; // ?: is a ternary operator. b, c and d are operands

4.2 STRING

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A string is a sequence of characters that are enclosed by double quotes. The restriction on a string is that it must be contained on a single line, that is, without a carriage return. It cannot be on multiple lines. Strings are treated as a sequence of one-byte ASCII values. "Hello Verilog World" // is a string "a / b" // is a string

4.3 INTEGER , REAL, AND TIME REGISTER DATA TYPES Integer, real, and time register data types are supported in Verilog.

4.3.1 INTEGER An integer is a general purpose register data type used for manipulating quantities. Integers are declared by the keyword integer. Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for purposes such as counting. The default width for an integer is the host-machine word size, which is implementation-specific but is at least 32 bits. Registers declared as data type reg store values as unsigned quantities, whereas integers store values as signed quantities. integer counter; // general purpose variable used as a counter. initial counter = -1; // A negative one is stored in the counter

4.3.2 REAL Real number constants and real register data types are declared with the keyword real. They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which is 3 x 106 ). Real numbers cannot have a range declaration, and their default value is 0. When a real value is assigned to an integer, the real number is rounded off to the nearest integer. real delta; // Define a real variable called delta initial begin delta = 4e10; // delta is assigned in scientific notation delta = 2.13; // delta is assigned a value 2.13 end
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integer i; // Define an integer i initial i = delta; // i gets the value 2 (rounded value of 2.13)

4.3.3 TIME Verilog simulation is done with respect to simulation time. A special time register data type is used in Verilog to store simulation time. A time variable is declared with the keyword time. The width for time register data types is implementation-specific but is at least 64 bits.The system function $time is invoked to get the current simulation time. time save_sim_time; // Define a time variable save_sim_time initial save_sim_time = $time; // Save the current simulation time

4.4 IDENTIFIERS AND KEYWORDS

Keywords are predefined, nonescaped identifiers that define the language constructs. An escaped identifier is never treated as a keyword. All keywords are defined in lowercase. [1] From IEEE Std. 1364-2001. Copyright 2001 IEEE. All rights reserved. The list is sorted in alphabetical order. always and assign automatic begin buf bufif0 bufif1 case casex casez ifnone incdir include initial inout input instance integer join large liblist
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rnmos rpmos rtran rtranif0 rtranif1 scalared showcancelled signed small specify specparam

cell cmos config deassign default defparam design disable edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event for force forever fork function generate genvar highz0 highz1 if

library localparam macromodule medium module nand negedge nmos nor noshowcancelled not notif0 notif1 or output parameter pmos posedge primitive pull0 pull1 pulldown pullup pulsestyle_onevent pulsestyle_ondetect rcmos real realtime reg release repeat

strong0 strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg unsigned use vectored wait wand weak0 weak1 while wire wor xnor xor

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4.4.1 SYSTEM TASKS AND FUNCTIONS The following is a list of keywords frequently used by Verilog simulators for names of system tasks and functions. Not all system tasks and functions are explained in this book. For details, refer to the IEEE Standard Verilog Hardware Description Language document. This list is sorted in alphabetical order. $bitstoreal $fdisplay $fwrite $incsave $list $monitoron $countdrivers $fmonitor $finish $input $log $nokey $display $fopen $getpattern $itor $monitor $fclose $fstrobe $history $key $monitoroff

4.4.2 COMPILER DIRECTIVES The following is a list of keywords frequently used by Verilog simulators for specifying compiler directives. Only the most frequently used directives are discussed in the book. For details, refer to the IEEE Standard Verilog Hardware Description Language document. This list is sorted in alphabetical order. 'accelerate 'default_nettype 'else 'endif 'expand_vectornets 'include 'autoexpand_vectornets 'define 'elsif 'endprotect 'ifdef 'noaccelerate 'celldefine 'define 'endcelldefine 'endprotected 'ifndef 'noexpand_vectornets 'protect 'remove_netnames 'unconnected_drive

'noremove_gatenames 'nounconnected_drive 'protected 'resetall 'remove_gatenames 'timescale

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Chapter 5
PROGRAMMING MODELING IN VERILOG
Different types of modeling used in verilog: Gate level modeling Data flow modeling Behavioral modeling

5.1 GATE LEVEL MODELING: 5.1.1 PRIMITIVES: Verilog provides a robust set of built-in gate primitives. Primitives are like predefined modules. A logic circuit is described on gate to gate basis using these primitives. Primitives can be instantiated only within modules and use of identifier name with primitive instantiation is optional. The port list of a primitive have output(or outputs) written first, followed by inputs.

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AND

if any of the input is 0, output is 0 else if any of input is x or z , output is x else if all inputs are 1, output is 1

NAND

if any of the input is 0, output is 1 else if any of input is x or z , output is x else if all inputs are 1, output is 0

OR

if any of the input is 1, output is 1 else if any of input is x or z , output is x else if all inputs are 0, output is 0

NOR

if any of the input is 1, output is 0 else if any of input is x or z , output is x else if all inputs are 0, output is 1

XOR

if any of the input is x or z, output is x else if odd number of inputs are 1, output is 1 else output is 0

XNOR if any of the input is x or z, output is x else if even number of inputs are 1, output is 1 else output is 0

BUF if input is 1, output is 1 else if input is 0, output is 0 else if input is x or z, output is x

NOT

if input is 1, output is 0 else if input is 0, output is 1 else if input is x or z, output is x

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5.1.2 Verilog gate level description of a and-or-invert logic gate: module AOI(out, in1, in2, in3, in4) ; output out ; input in1, in2, in3, in4 ; wire y1, y2 ; and (y1, in1, in2) ; and a1(y2, in3, in4) ; nor (out, y1, y2); endmodule

in1 in2

y1 out

in3
in4

y2

FIGURE 5.1 AND-OR-INVERT Logic Gate

5.2 DATA FLOW MODELING: Data flow modeling describes the design in terms of expressions instead of primitive gates. A continuous assignment statement is the most basic statement in the dataflow modeling. It is used to assign a value to a net. It starts with the keyword assign followed by actual assignment

e.g. assign A = x | (Y & ~Z) ; assign B[3:0] = 4b10xx ; assign C[15:0] = F[15:0] ^ E[15:0] ; Left hand side of the assignment must be nets(scalar or vector), but right hand side expression can have registers, nets or function calls as operands.

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The continuous assignment statement are continuously active and they all execute in parallel. Whenever value of any operand on right side changes expression is reevaluated and new value is assigned to the corresponding net. Continuous assignments can be made implicitly by associating the right hand side expression with the declaration of target net e.g. Instead of wire cout ; assign cout = cin1 + cin2 ; we can write wire cout = cin1 + cin2 Multiple assignments can be made with one assign keyword using comma-separated lists e.g. assign y1 = a1 ^ a2, y2 = a2 | a3, y3 = a1 + a3 ; assign data = s[3:0] + r[5:2], m = a & g ;

5.2.1 Verilog dataflow style description of a 1-bit full adder:

module f_add_1bit ( sum, cout, a, b, cin) ; output sum, cout ; input a, b, cin ; assign sum = a ^ b ^ cin ; assign cout = (a & cin) | (b & cin) | (a & b) ; endmodule Verilog has a robust set of built-in operators that manipulate the various types of data implemented in the language to produce values on nets and registers. Some of the operators are used within expressions on right-hand side of continuous assignment statements and procedural statements; others are used in Boolean expressions in conditional statements or with conditional operators.

5.2.2 OPERATORS: 5.2.2.1 LOGICAL OPERATORS: && - logical AND

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|| !

- logical OR - logical NOT

Logical operators evaluates to one bit value 0, 1, or x. These operators gives result on the basis of logical values of operands I.e. If operand has zero value, it is taken as logical false (0) If operand has non-zero value, it is taken as logical true (1) If a bit in any of the operand is x or z, whole operand is treated as x

A= 6 B=0 C=x C && B

A && B A || (!B) C || B

1 && 0 1 || 1 x || 0 x && 0

0 1 x 0

5.2.2.2 REDUCTION OPERATORS & | ^ ~& ~| ~^ or ^~ reduction AND reduction OR reduction XOR reduction NAND reduction NOR reduction XNOR

Reduction operators are unary operators i.e. they act on single operands. They create a single-bit result by operating on a multibit operand. &(010101) a = 4b1001 b = ^a |(010x10) b=1^0^0^1 0|1|0|x|1|0 b=1 1 0&1&0&1&0&1 0

5.2.2.3 BITWISE OPERATORS & - bitwise AND

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| ~ ^ ~^

- bitwise OR - bitwise NOT - bitwise XOR - bitwise XNOR

Bitwise operators acts on individual bits of the operands. The operands may be scalar or vector. If one of the operand is shorter than the other, it will be zero extended to match the length of the longer operand. The bitwise not operator negates the individual bits of an operand. a = 4b1010 b = 4b1100 c = ~a d=a&b c = ~(1010) d = 1010 & 1100 c = 0101 d = 1000

e = (101011) ^ b e = 101011 ^ 001100

e = 101011 ^ 1100 e = 100111

5.2.2.4 SHIFT OPERATORS >> << shift right shift left

Verilog shift operators operate on a single operand and shift (left or right) the bit pattern of the operand by a specified number of positions, filling zeroes in the position that are vacated. a = 4b1010 d = a >> 2 c = a << 1 d = 0010 c = 0100

5.2.2.5 CONCATENATION OPERATOR { op1, op2, } This operator concatenates op1, op2, to a single number. The operand should be sized, no unsized constant operand is allowed. If the operand A is bit pattern 1011 and
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the operand B is the bit pattern 0001, then {A, B} is the bit pattern 1011_0001 {0011, {{01}, {10}}} = 0011_0110

Replication of same operand can be expressed by using a replication constant which specifies how many times to replicate the number inside the brackets ({ }). a = 1b1 b = 3b010 c = 3b101 catr = { 4{a}, b, 2{c} } catr = {1, 1, 1, 1, 010, 101, 101}

5.2.2.6 RELATIONAL OPERATOR < >= <= > less than greater than or equal to less than or equal to greater than

The Verilog relational operators compare operands and produce a Boolean 0 or 1 (true or false) result. If any bit in one of the operands is unknown (x), the result is unknown.

1>0 b1x1 <= 0 10 < z

1 x x

5.3 BEHAVIORAL MODELING: Verilog behavioral code is inside procedures blocks, but there is a exception, some behavioral code also exist outside procedures blocks. We can see this in detail as we make progress.
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There are two types of procedural blocks in Verilog initial : initial blocks execute only once at time zero (startexecution at time zero). always : always blocks loop to execute over and over again, in other words as

name means, it executes always.

initial begin clk = 0; reset = 0; enable = 0; data = 0; end end

always@ (posedge clk) begin : D_FF if (reset == 1) q <= 0; else q <=d;

5.3.1 Procedural Assignment Statements: Procedural assignment statements assign values to registers and cannot assign values to nets (wire data types). You can assign to the register (reg data type) the value of a net

(wire), constant, another register, or a specific value. If a procedure block contains more then one statement, those statements must be enclosed within Sequential begin - end block, Parallel fork - join block. When using begin-end, we can give name to that group. This is called Named blocks.

5.3.2 Sequential statement The begin - end keywords: Group several statements together. Cause the statements to be evaluated in sequentially (one at a time). Any timing within the sequential groups is relative to the previous statement. Delays in the sequence accumulate (each delay is added to the previous delay) Block finishes after the last statement in the block.

5.3.3 Conditional statement:

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The if - else statement controls the execution of other statements, In programming language like c, if - else controls the flow of program. if (condition) statements; if (condition) statements; else statements; if (condition) statements; else if (condition) statements; ................ else statements;

5.3.4 Case statement: The case statement compares a expression to a series of cases and executes the statement or statement group associated with the first matching case ? case statement supports single or multiple statements. ? Group multiple statements using begin and end keywords. case (<expression>) <case1> : <statement> <case2> : <statement> ..... default : <statement> endcase

5.3.5 Looping statement: Looping statements appear inside a procedural blocks only, Verilog has four looping statements like any other programming language.
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While Loop The while loop executes until the while expression is not true. If the loop is entered when the while-expression is not true, the loop is not executed at all. //Illustration 1: Increment count from 0 to 127. Exit at count 128. //Display the count variable. integer count; initial begin count = 0; while (count < 128) //Execute loop till count is 127. //exit at count 128 begin $display("Count = %d", count); count = count + 1; end end

For Loop Example 7-3. For Loop integer count; initial for ( count=0; count < 128; count = count + 1) $display("Count = %d", count);

Repeat Loop A repeat construct cannot be used to loop on a general logical expression. A while loop is used for that purpose. A repeat construct must contain a number, which can be a constant, a variable or a signal value. Example 7-4. Repeat Loop //Illustration 1 : increment and display count from 0 to 127 integer count; initial
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begin count = 0; repeat(128) begin $display("Count = %d", count); count = count + 1; end end

Forever loop The keyword forever is used to express this loop. The loop does not contain any expression and executes forever until the $finish task is encountered. //Example 5: Synchronize two register values at every positive edge of //clock reg clock; reg x, y; initial forever @(posedge clock) x = y;

5.3.6 Continuous assignment statements: Continuous assignment statements drives nets (wire data type). Theyrepresent structural connections. They are used for modeling Tri-State buffers. They can be used for modeling combinational logic. They are outside the procedural blocks (always and initial blocks). The continuous assign overrides and procedural assignments. The left-hand side of a continuous assignment must be net data type.

Syntax: Assign (strength, strength) # delay net = expression;

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5.3.7 Modeling the flip flops with always statement: Very basic: an edge-sensitive flip-flop reg q; always @(posedge clk) q = d; q = d assignment runs when clock rises: exactly the Behavior you expect.

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