Jntu Hyd 2 2ece PDC Set 4

S.
54 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

B.Tech. II-Year II-Sem. ( JNTU-Hyderabad )
Code No.: R09220403/R09
B.Tech. II Year II Semester Examination
April/May - 2012
PULSE AND DIGITAL CIRCUITS
( Common to ECE, BME, ETM )
Time: 3 Hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
- - -
1. (a) An inductor does not allow sudden changes in current and a capacitor does not allow sudden changes in
voltage. Justify with relevant equations. (Unit-I, Topic No. 1.1)
(b) What are the disadvantages of RL linear wave shaping circuit compared to RC circuit? (Unit-I, Topic No. 1.4)
(c) A symmetrical square wave of t5 V at a frequency of 5 kHz is applied to a high pass RC circuit with a cut-off
frequency of 20 kHz. Sketch the steady state input and output voltage waveforms. Calculate the steady state
output voltage levels. [4+3+8] (Unit-I, Topic No. 1.2)
2. (a) A voltage signal of 10 sin t is applied to the circuit with ideal diodes shown in Figure. Estimate the maximum
and minimum values of output waveform and maximum current through each diode. Also draw the input-output
waveforms with proper explanation. (Unit-II, Topic No. 2.1)
D
2
10 V
10 k
10 k
D
1
+
V
i
+
V
o
D
2
10 V
10 k
10 k
D
1
+
V
i
+
V
o
Figure
(b) Explain the steps to analyze a clamping network with an example. [10+5] (Unit-II, Topic No. 2.3)
3. (a) Calculate the output levels of the circuit shown in figure (2), for the inputs 0 and 6 volts and verify that the
circuit is an inverter. What is the minimum value of h
FE
required? Neglect junction saturation voltages and
assume an ideal diode. (Unit-III, Topic No. 3.3)
6 V
18 V
6 V
5.6 k
V
i
2.2 k
22 k
6 V
18 V
6 V
5.6 k
V
i
2.2 k
22 k
Figure (2)
(b) With neat sketches representing minority-carrier density distribution as a function of distance from junction,
explain the diode reverse recovery time in detail. [10+5] (Unit-III, Topic No. 3.1)
Se t - 4
S o l u t i o n s
S. 55 Pulse and Digital Circuits (April/May-2012, Set-4) JNTU-Hyderabad
( JNTU-Hyderabad ) B.Tech. II-Year II-Sem.
4. (a) Explain various methods to improve the resolution of a binary. (Unit-IV, Topic No. 4.1)
(b) Design a Schmitt trigger circuit using npn silicon transistors with V
BE
= 0.7 V, V
CE(sat)
= 0.2 V, h
fe(min)
= 60 and I
C(ON)
= 3 mA to meet the following specifications, V
CC
= 12 V, upper threshold voltage, V
UT
= 4 V, lower threshold
voltage, V
LT
= 2V. [3+12] (Unit-IV, Topic No. 4.4)
5. (a) Prove that when restoration time is zero, saw-tooth output waveform can be obtained from a sweep generator
circuit. (Unit-V, Topic No. 5.3)
(b) The transistorized bootstrap sweep generator circuit has the following parameters, V
CC
= 25 V, V
EE
= 15 V,
R= 10 k, R
B
= 150 k, R
E
= 1k, C = 0.05 F. The gating waveform has 300 s duration. The transistor
parameters are h
ie
= 1.1 k, h
re
= 2.5 10
4
, h
fe
= 50, h
oe
= 24 A/V.
(i) Draw the waveforms for the collector current of input transistor (Q
1
), I
C1
and output voltage at the emitter
of output transistor (Q
2
), labeling all current and voltage levels.
(ii) What is the slope error of the sweep?
(iii) What is the sweep speed and the maximum value of the sweep voltage?
(iv) What is the retrace time T
r
for C to discharge completely?
(v) Calculate the recovery time T
1
for C
1
to recharge completely. [7+8] (Unit-V, Topic No. 5.2)
6. (a) Draw the bidirectional diode sampling gate in the form of a bridge network and explain its working.
(Unit-VI, Topic No. 6.2)
(b) Explain how a sampling gate is used in chopper amplifier. [8+7] (Unit-VI, Topic No. 6.4)
7. (a) What do you mean by synchronization? (Unit-VII, Topic No. 7.1)
(b) What is the condition to be met for pulse synchronization? (Unit-VII, Topic No. 7.1)
(c) Compare sine wave synchronization with pulse synchronization. [3+6+6] (Unit-VII, Topic No. 7.3)
8. (a) Compare the RTL and DTL logic families in terms of fan out, propagation delay, power dissipated per gate and
noise immunity. (Unit-VIII, Topic No. 8.2)
(b) What is meant by tri-state logic? Draw the circuit of tri-state TTL logic and explain its operation in detail. [8+7]
(Unit-VIII, Topic No. 8.1)
S. 56 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
SOLUTIONS TO APRIL/MAY-2012, SET-4, QP
Q1. (a) An inductor does not allow sudden
changes in current and a capacitor does
not allow sudden changes in voltage.
Justify with relevant equations.
Answer : April/May-12, Set-4, Q1(a) M[4]
An Inductor does not Allow Sudden Changes in Current
In a circuit, when an inductor is employed as an
element, voltage gets developed across it, if there is a rate of
change of current.
Consider an inductor connected across a supply voltage
V
S
. Let i be the current flowing through it as shown in the
following figure.
The voltage across the inductor is given by,
V =
dt
di
L
L
i
V
S
t = 0
S
L
i
V
S
V
S
t = 0
S
Figure
Suppose, at t = 0
i.e., just before closing the switch,

the current through the inductance is zero. At t = 0, the
switch is closed. Suppose at t = 0
+
i.e., just after closing the
switch, a current of 5 A is expected through the inductor.
This would happen, if and only if the voltage across the
inductor becomes infinity i.e.,
V =
dt
di
L
=
) 0 ( ) 0 (
)] 0 ( ) 0 ( [
+
+
t t
i i
L
=
+
0 0
) 0 5 (
L
But, 0
+
0
0
V =
0
) 5 ( L
=
But, infinite voltage across an inductor when input
voltage is finite is not possible. Hence, due to this, the current
through an inductor cannot change within zero time i.e.,
instantaneously, rather it increases gradually and requires
some finite time. During this period, the current through the
inductor takes the previous value,
i.e., i(0
+
) = i(0
)
A Capacitor does not allow Sudden Changes in Voltage
In a circuit, when a capacitor is employed as an
element, current is induced through it, if there is a rate of
change of voltage.
Consider a capacitor connected across a supply
voltage V
S
, let V be the voltage across it as shown in the
figure. The current through the capacitor is given by,
i = C
dv
dt
V
s
C
t = 0
s
i
V
s
C
t = 0
s
i
Figure
Assume that at t = 0

i.e., just before closing the switch,
the voltage across the capacitor is zero. At t = 0, the switch
is closed.
Also assume that at t = 0
+
i.e., just after closing the
switch, the voltage of 3V is expected across the capacitor.
This occurs only when the current through the capacitor
becomes infinity i.e.,
i = C
dv
dt
= C
(0 ) (0 )
(0 ) (0 )
v v
t t
+
+
1
1
]
= C 1
]
1
+
0 0
0 3
Since,
0
+
0
0
i =
0
3 C
=
Hence, a small change in voltage across a capacitor
within zero time gives an infinite current through the
capacitor, which is physically impossible. In a fixed
capacitance, the voltage cannot change abruptly.
(b) What are the disadvantages of RL linear
wave shaping circuit compared to RC
circuit?
Answer : April/May-12, Set-4, Q1(b) M[3]
1. At low frequencies, the shunt inductor in a RL linear
wave shaping circuit becomes large which cannot be
reduced.
2. A heavy iron core inductor should be employed to
obtain larger values of inductor in order to achieve
higher time constants.
3. A large distributed capacitor should be employed in
parallel to an iron cored inductor.
4. Higher value of inductors are very expensive.
5. Unwanted distortions may occur in RL circuits due
to the non-linear properties of iron.
(c) A symmetrical square wave of 5 V at
a frequency of 5 kHz is applied to a high
pass RC circuit with a cut-off frequency
of 20 kHz. Sketch the steady state input
and output voltage waveforms.
Calculate the steady state output voltage
levels.
Answer : April/May-12, Set-4, Q1(c) M[8]
Given that,
For a high pass RC circuit,
Amplitude of input symmetrical square wave,
= t 5 V
V = 5 ( 5) = 10 V
Frequency of symmetrical square wave, f = 5
kHz
Cut-off frequency, f
L
= 20 kHz
Steady state output voltage levels = ?
The square wave applied at the input of high pass
RC circuit is as shown in figure (b),
t
V
5V
0
+ 5V
T
t
V
5V
0
+ 5V
T
V
V
0
i (t)
C
+
V
V
0
i (t)
C
+
Figure (a) Figure (b)
The cut-off frequency, f
L
=
RC 2
1
20 10
3
=
RC 2
1
RC =
3
10 20 2
1

= 0.008 10
3
RC = 0.008 ms
Time period of the input, T =
f
1
=
1
5k
= 0.2 ms
The output voltage levels of high pass filter are V
1
,
'
1
V , V
2
and
'
2
V .
For a symmetrical input square wave,
V
1
=
RC T
e
V
/ ) 2 / (
1
+
... (1)
V
2
= V
1
... (2)

'
1
V = V
1
e
(T/2)/RC
... (3)

'
2
V =
'
1
V ... (4)
From equation (1),
V
1
=
) 10 008 . 0 2 / 10 2 . 0 (
3 3
1
10

+ e
1
10V V
2 1
10V V V (QFrom equation (2))
From equation (3), we get,

'
1
V = 10
) 10 008 . 0 2 / 10 2 . 0 (
3 3

e
= 37.3 10
6

'
1
37.3 V V

' '
2 1
37.3 V V V (QFrom
equation (4))
Therefore, the output voltage levels under steady
state are,
V
1
= 10 V

'
1
V = 37.3 V
V
2
= 10 V

'
2
V = 37.3 V
The input and output steady state voltage waveforms
are as shown in figure (c).
37.3 V
37.3 V
5 V
10 V V
1
V
0
V
2
10V
'
1
V
'
2
V
0
37.3 V
37.3 V
5 V
10 V V
1
V
0
V
2
10V
'
1
V
'
2
V
0
Figure (c): Steady State Response
Q2. (a) A voltage signal of 10 sin t is applied to the circuit with ideal diodes shown in figure
Estimate the maximum and minimum values of output waveform and maximum current
through each diode. Also draw the input-output waveforms with proper explanation.
D
2
10 V
10 k
10 k
D
1
+
V
i
+
V
o
D
2
10 V
10 k
10 k
D
1
+
V
i
+
V
o
Figure
Given that,
For a circuit with ideal diodes,
Voltage signal, V
i
= 10 sin t
Maximum current through D
1
and D
2
= ?
Maximum and minimum values of output voltage waveform = ?
Plot of input and output voltage waveforms = ?
V
i
10
10
t
V
i
10
10
t
D
2
10V
10 K
10 K
D
1
+
V
i
V
o
D
2
10V
10 K
10 K
D
1
+
V
i
V
o
Figure (1)
From figure (1), we get,
V
R
= 10 V
Case (i)
For V
i
< 0
Diode D
1
is OFF and does not conduct.
Since V
i
< V
R
, Diode D
2
is OFF and does not conduct, and the circuit shown in figure (1) is modified as shown in figure (2).
D
2
10V
10 k
10 k
D
1
+
V
i
+
V
o
D
2
10V
10 k
10 k
D
1
+
V
i
+
V
o
Figure (2)
Hence, no current flows in the circuit for V
i
= 0,
0V
o
V
Case (ii)
For 0 <V
i
< 10 V
Diode D
1
is ON and conducts
Since, V
i
< V
R
, diode D
2
is OFF and does not conduct
and the circuit shown in figure (1) is modified as shown in
figure (3).
D
2
10V
10 k
10 k
D
1
+
V
i
+
V
o
V
A
D
2
10V
10 k
10 k
D
1
+
V
i
+
V
o
V
A
Figure (3)
10 k || = 10 k
The voltage, V
A
=
10 k
10 k 10 k
_

+ ,
V
i

Output voltage
2
i
o A
V
V V
This continues till, V
A
= 5 V
5 =
2
i
V
10V
i
V
As diode D
1
is ON, when V
i
< V
R
V
i
= 10 V
Maximum current through diode, D
1
=
( )
10 k
A i
V V
=
3
10 10
) 10 ( 5

=
3
10 10
15
= 1.5 mA
1
Maximumcurrent throughdiode, 1.5mA D
Case (iii)
For V
i
> 10 V (input)
Diode D
1
is ON and conducts
Since, V
A
increases above V
R
, (i.e., V
A
> V
R
)
Diode D
2
is ON and starts conducting.
The circuit shown in figure (1) is modified as shown
in figure (4).
D
2
10V
10 k
10 k
D
1
+
V
i
V
o
V
A
1.5 mA
1
i
P
i
2
D
i
D
2
10V
10 k
10 k
D
1
+
V
i
V
o
V
A
1.5 mA
1
i
P
i
2
D
i
Figure (4)
10 k || = 10 k
V
A
= 10 V
Hence, V
o
= V
A
= V
R
= 10 V
10V
o
V
The current across parallel resistor 10k is,
i
P
=
10 k
A
V
=
10
10 k
i
P
= 1 mA
No current flows through infinite resistor, as applying
KCL at node (1), we get,
1.5 mA= i
p
+
2
D
i

+ i

2
D
i
= 1.5 mA 1mA 0
= 0.5 mA

2
Maximum current through diode, 0.5mA D
Input V
i
Output V
0
Diode Status
V
i
< 0 V
o
= 0 V D
1
OFF
D
2
OFF
0 < V
i
< 10 V V
o
=
2
i
V
D
1
ON
D
2
OFF
V
i
< 10 V V
o
= 10 V D
1
ON
D
2
ON
Thus, the input-output waveforms for the circuit can
be drawn as shown in figure (5).
10
5V
10 V
V
i
10 V
5 V
V
o
Input waveform
t
t
Output waveform
10
5V
10 V
V
i
10 V
5 V
V
o
Input waveform
t
t
Output waveform
Figure (5): Input Output Waveforms
The transfer characteristics of the circuit is as shown in figure (6).
D
1
OFF
D
2
OFF
0
S
l
o
p
e

=

0
.
5
Slope = 0
D
1
ON
D
2
OFF
10 V
D
1
ON
D
2
ON
Slope = 0
V
i
V
o
D
1
OFF
D
2
OFF
0
S
l
o
p
e

=

0
.
5
Slope = 0
D
1
ON
D
2
OFF
10 V
D
1
ON
D
2
ON
Slope = 0
V
i
V
o
Figure (6)
(b) Explain the steps to analyze a clamping network with an example.
Steps to Analyze a Clamping Network
The various steps involved in the analysis of a clamping network are,
Step 1
Portion of the input of the clamping network is considered which forward biases the diode.
Step 2
When the diode is in ON state (i.e., conducts), consider that the charging of the capacitor occurs rapidly to a
voltage level which is estimated by the network input.
Step 3
When the diode is in OFF state (i.e., not conducting), it is assumed that the capacitor holds its voltage level
(because of the large time constant).
Step 4
The output is then analyzed and the respective waveforms are plotted.
Example
Consider the clamping circuit as shown in figure (1).
V
i
V
m
V
m
t
0
V
i
V
m
V
m
t
0
D
V
i
V
o
+
V
R
L
C
D
V
i
V
o
+
V
R
L
C
Figure (1): Clamping Circuit with Controlled Voltage
Step 1
It is observed that at first quarter of negative half cycle, when V
i
< V, the diode D is forward biased (i.e., ON).
Step 2
As the diode is conducting, the capacitor instantaneously charges to the voltage V
C
of V
m
V as shown in figure (2).
i.e., V
C
= V
m
V ... (1)
D
(on)
V
i
+
V
C
C
+
+
V
V
C
= V
m
V
2
1
i
D
(on)
V
i
+
V
C
C
+
+
V
V
C
= V
m
V
2
1
i
Figure (2): Charging of Capacitor
Step 3
At positive half cycle the diode D is reverse biased due to the capacitor voltage V
C
= V
m
V. The modified circuit is
as shown in figure (3)
V
i
V
o
+
V
R
C
V
C
= V
m
V

+
+ +
D
(off)
V
i
V
o
+
V
R
C
V
C
= V
m
V

+
+ +
D
(off)
Figure (3): Circuit at Positive Half Cycle
Applying KVL to the above circuit, we get,
V
i
+ V
C
V
o
= 0
V
o
= V
i
+ V
C
( )
o i m
V V V V + (Q From equation (1))
Case (i)
When, V
i
= V
m
V
o
= V
m
+ V
m
V

o
V V
Case (ii)
When, V
i
= 0 V
V
o
= 0 + V
m
V

o m
V V V
Case (iii)
When, V
i
= + V
m
V
o
= V
m
+ V
m
V
2
o m
V V V
Step 4
The input and output waveforms are plotted as shown in figure (4)
+ V
m
V
m
V
i
t
2V
m
V
V
V
o
t
V
m
V
0
D.C shift of V
m
V
Output
Input
+ V
m
V
m
V
i
t
2V
m
V
V
V
o
t
V
m
V
0
D.C shift of V
m
V
Output
Input
Figure (4): Input and Output Waveforms
Q3. (a) Calculate the output levels of the circuit
shown in figure for the inputs 0 and 6
volts and verify that the circuit is an
inverter. What is the minimum value of
h
FE
required? Neglect junction
saturation voltages and assume an ideal
diode.
6 V
18 V
6 V
5.6 k
V
i
2.2 k
22 k
6 V
18 V
6 V
5.6 k
V
i
2.2 k
22 k
Figure
Given that,
For a circuit with ideal diodes is shown in figure (1)
6 V
18 V
6 V
5.6 k
V
i
2.2 k
22 k
I
22 K
I
5.6 K
I
B
6 V
18 V
6 V
5.6 k
V
i
2.2 k
22 k
I
22 K
I
5.6 K
I
B
Figure (1)
Input voltage,
V
min
= 0 V
V
max
= 6 V
h
FE(min)
= ?
The relation between input and base emitter voltage
is,
5.6 k
BE i
V V
+
6
22 k
BE
V
= 0
22 kV
BE
22 kV
i
+ 5.6 kV
BE
33.6 k = 0
27.6 kV
BE
= 22 kV
i
+ 33.6 k
217 . 1 797 . 0 +
i BE
V V ... (1)
When,
V
i
= 0
V
BE
= 0 + 1.217
217 . 1
BE
V
Since, V
BE
is positive and transistor is pnp, the
transistor enters into cut-off and becomes OFF. (i.e., V
BE
should be ve for pnp and +ve for npn)
As the transistor is in cut-off region,
I
C
= 0
Hence, no voltage drops across R
C
= 2.2 k
Then the circuit becomes as,
18 V
6 V
2.2 k
V
o
= 6 V
18 V
6 V
2.2 k
V
o
= 6 V
Figure (2)
The diode is forward biased due to less voltage at
the n-region.
6V
o
V
When,
V
i
= 6 V
Substituting V
i
in equation (1), we get,
V
BE
= 0.797 ( 6) + 1.217
= 4.782 + 1.217
V
BE
= 3.565 V
Since, V
BE
is negative, the transistor operates in
saturation region.
i.e., V
CE
0 V
Then, the diode is reverse biased.
Hence, the output voltage is low,
0V
o
V
Therefore, it can be concluded that the given circuit
acts as an inverter.
The h
FE(min)
of a transistor which is in saturation
region is given by,
h
FE(min)
=
B
C
I
I
... (2)
Base current, I
B
= I
5.6
+ I
22
=
6
5.6
+
6
22
= 1.07 mA + 0.27 mA
I
B
= 0.8 mA
Collector current, I
C
=
C
CC
R
V
=
18V
2.2k
mA 18 . 8
C
I
Substituting the values of I
B
and I
C
in equation (2),
we get,
h
FE(min)
=
8.18 mA
0.8 mA
FE(min)
h 10.23
(b) With neat sketches representing
minority-carrier density distribution as
a function of distance from junction,
explain the diode reverse recovery time
in detail.
For answer refer Unit-III, Q1, (Exclude first 2 Paras).
Q4. (a) Explain various methods to improve
the resolution of a binary.
There are three methods to improve the resolution of
a binary. They are,
1. Reducing all stray capacitances
2. Reducing the resistors R
1
, R
2
and R
C
3. Avoiding the transistor to enter into saturation.
1. Reducing all Stray Capacitances
When the values of the stray capacitances are
reduced, their charging time decreases. Because of this the
transistor enters into the state opposite to its present state
in a small amount of time.
2. Reducing the Resistors R
1
, R
2
and R
C
When the values of the resistors R
1
and R
2
are
reduced, the charging time of the transpose (commutating)
capacitors and the recovery time are reduced. This reduction
in charging time increases the speed of transition (from one
state to another state) in transistors.
3. Avoiding the Transistor to Enter into Saturation
The storage time of a non-saturated transistor
decreases which results in the rapid switching of transistors
from ON to OFF state.
(b) Design a Schmitt trigger circuit using
npn silicon transistors with V
BE
= 0.7 V,
V
CE(sat)
= 0.2 V, h
fe(min)
= 60 and I
C(ON)
= 3
mA to meet the following specifications,
V
CC
= 12 V, upper threshold voltage,
V
UT
= 4 V, lower threshold voltage,
V
LT
= 2 V.
Given that,
For a schmitt trigger circuit using NPN silicon
transistors,
V
BE
= 0.7 V
V
CE(sat)
= 0.2 V
h
fe(min)
= 60
I
C(ON)
= 3
V
CC
= 12 V
V
1
= V
UT
= 4 V
V
2
= V
LT
= 2 V
1
C
R
= ?
2
C
R
= ?
R
E
= ?
R
1
= ?
R
2
= ?
R
S
= ?
The circuit diagram of a schmitt trigger to be designed is as shown in figure.
I
2
I
1
C
1
C
2
R
1
Q
1
Q
2
E
1
E
2
V
0
I
E
R
E
R
2
V
CC
B
1
B
2
V
1

+
+
R
S
1
C
I
1
C
R
2
C
R
2
C
I
2
B
I
I
2
I
1
C
1
C
2
R
1
Q
1
Q
2
E
1
E
2
V
0
I
E
R
E
R
2
V
CC
B
1
B
2
V
1

+
+
R
S
1
C
I
1
C
R
2
C
R
2
C
I
2
B
I
Figure: Schmitt Trigger
For NPN transistor,
Cut-in voltage, V
1
= V
2
= 0.5 V
Calculation of R
E
V
UT
= V
1
= V
E
= V
1
V
E
= V
UT
V
1
= 4 0.5
V
E
= 3.5 V
And R
E
=
2
E
E
V
I
Where,

2
E
I
=
2
C
I
= 3 mA (
Q

2
B
I
<<
2
C
I
,
2
C
I

2
E
I
)
R
E
=
3.5 V
3mA
= 1.167 10
3
1.167 k
E
R
Calculation of
2
C
R
Let Q
2
be in the active region, then V
CE(active)
is given as,
V
CE(active)
=
3
1
V
CC
=
3
1
12 = 4 V
V
CE(active)
= 4 V
On applying KVL at the collector side of transistor
Q
2
, we get,
V
CC

2
c
I

2
c
R
V
CE(active)

2
C
I
R
E
= 0
2
c
R
=
2
2
( ) cc CE active C E
C
V V I R
I

=
3
3 3
10 3
) 10 167 . 1 10 3 ( 4 12

=
3
10 3
499 . 4
= 1.49 10
3

1.5 k

2
1.5 k
C
R
Calculation of
1
C
R
Since,
V
UT
= V
1

V
'
0.1
Where,
V
'
=
1
2
1 2 C
R
R R R
1
1
+ +
1
]
V
cc
V
1
=
1
2
1 2 C
R
R R R
_

+ +
,
V
CC
0.1 ... (1)
1
2
1 2 c
R
R R R + +
=
CC
V
V 1 . 0
1
+
=
4 0.1
CC
V
+
1
2
1 2 c
R
R R R + +
= 0.342 ... (2)
Then,
V
1
= 0.342 V
cc
0.1 (Q From equation (1))
But, R =
1
C
R
|| (R
1
+ R
2
)
=
1
1
1 2
1 2
( )
C
C
R R R
R R R
+
+ +
... (3)
and common base current gain, =
2 1
2
R R
R
+
R =
,
_
+
2 1
2
R R
R

1
1
1 2
1 2
( )
)
C
C
R R R
R R R
_ +

+ +
,
=
1
2 1
1 2
C
C
R R
R R R + +
R = 0.342
1
c
R
[
Q
From equation (2)]
V
LT
=
1
BE
V
+
'
'
s
E
E
R
R
R R
1
+
1
+
]
(V'

V
2
)
For very large values of h
fe
,

'
E
R R
E
And
fe
S
h
R
<< R
E

V
LT
= V
2
=
1
BE
V
+
E
E
R
R R
_

+ ,
(V'

V
2
)
On substituting corresponding values, we get,
2 = 0.7 +
1
3
3
1.167 10
0.342 1.167 10
c
R
1
1
+
1
]
[(0.342 V
cc
)

(0.5)]
1.3 =
1
3
3
1.167 10
0.342 1.167 10
c
R
1
1
+
1
]
[0.342 12

0.5]
1.3 =
1
3
3
1.167 10
0.342 1.167 10
c
R
1
1
+
1
]
(3.604)
0.342
1
C
R
+ 1.167 10
3
=
3 . 1
604 . 3 10 167 . 1
3

0.342
1
c
R
= 2.068 10
3

1
c
R
= 6.046 10
3

1
6.05k
c
R
Calculation of R
1
R
1
is 3 or 5 times greater than
1
c
R

i.e., R
1
= 5
1
C
R
= 5 6.05 10
3
= 30.25 10
3

1
30.25 k R
Calculation for R
2
From equation (2),

1
2
1 2 c
R
R R R + +
= 0.342
R
1
+ R
2
+
1
c
R
=
342 . 0
2
R

342 . 0
2
R
R
2
= R
1
+
1
c
R
On substituting corresponding values, we get,
R
2

,
_
1
342 . 0
1
= 30.25 10
3
+ 6.05 10
3
R
2
(1.924) = 36.3 10
3
R
2
= 18.86 10
3

2
18.86 k R
Calculation of R
S
We have,
R
S
<< h
fe
R
E
R
S
<< 60 1.167 10
3
R
S
<< 70.02 k
Let,
R
S
= 2 k (an arbitrary value)
Therefore, the design values are,
R
E
= 1.167 k
2
C
R
= 1.5 k

1
C
R
= 6.05 k
R
1
= 30.25 k
R
2
= 18.86 k
R
S
= 2 k
Q5. (a) Prove that when restoration time is zero, sawtooth output waveform can be obtained from a
sweep generator circuit.
The sweep generator using UJT is shown in figure (1), which is used to produce the sweep.
C
T
V
0
+
V
BB
R
2 R
T
R
1
I/P
C
T
V
0
+
V
BB
R
2 R
T
R
1
I/P
Figure (1)
The resultant output waveform of the sweep generator is shown in figure (2).
T
r
r T T
T /R C
r P
V = V e
T
S
V
E(min)
V
BB
V
P
S T T
T /R C
S P
V V 1 e
1
]
T
r
r T T
T /R C
r P
V = V e
T
S
V
E(min)
V
BB
V
P
S T T
T /R C
S P
V V 1 e
1
]
Figure (2)
Where,
T
r
= Retrace or restoration period
T
s
= Sweep period.
Consider the increasing exponential waveform of sweep circuit,
V
S
= V
P

[ ]
T T
C R t
e
/
1
at t = T
s
... (7)
Expanding the exponential term,
V
S
= V
P
2 3
1 1
1 1 ...
2! 3!
T T T T T T
t t t
R C R C R C
1 1
1 1
1 1 + + +
1 1
1 1
] ]
] ]
V
S
= V
P
1
1
]
1
1
]
1
2
2
1
T T T T
C R
t
C R
t
~
,
_
T T
P
C R
V
T
s
By differentiating with respect to t at t = 0 and t = T
s
, the initial slope is obtained as,
Initial slope
0
0
t
dt
dV
=
T T
p
C R
V
(Q From equation (1))
Initial slope at t = T
S
, which is represented by
'
S
V

'
S
V = T
S

p
T T
V
R C

'
S
V =
,
_
T T
ST
C R
T
V
P
Hence, it is increasing ramp.
Now, consider the decaying exponential equation of sweep circuit.
i.e., V
r
= T T
C R t
e
/
at t = T
r
= V
P

2
1
1 ...
2!
T T C T
t t
R C R C
1
_
1 + +

, 1
]
V
r
= V
P 1
]
1
T T
C R
t
1
By differentiating with respect to t at t = T
s
and t =
T
r
, the final slope is obtained as,

s
r
t
dV
dt

=
P s
T T
V T
R C
... (2)
At t = T
r
,

'
r
r
t T
d
dt
=
r
P
T T
t T
V t
R C

When restoration time is zero,
i.e., T
r
= 0
And t = T
r
+ T
s
t = T
S
So,

'
r
r
t T
dV
dt
=
P s
T T
V T
R C
... (3)
Since the slope at T
s
and T
r
is equal it is a zero slope
live i.e., straight line.
Hence, the output will be a straight decrease as shown
in figure (3)
0 T
S
V
P
t
0 T
S
V
P
t
Figure (3)
Therefore, at zero restoration time, the output of sweep
generator is a sawtooth waveform.
(b) The transistorized bootstrap sweep
generator circuit has the following
parameters, V
CC
= 25 V, V
EE
= 15 V,
R = 10 k , R
B
= 150 k , R
E
= 1 k ,
C = 0.05 F. The gating waveform has
300 s duration. The transistor
parameters are h
ie
= 1.1 k , h
re
= 2.5
10
4
, h
fe
= 50, h
oe
= 24 A/V.
(i) Draw the waveforms for the
collector current of input transistor
(Q
1
), I
C1
and output voltage at the
emitter of output transistor (Q
2
),
labeling all current and voltage
levels.
(ii) What is the slope error of the
sweep?
(iii) What is the sweep speed and the
maximum value of the sweep
voltage?
(iv) What is the retrace time T
r
for C to
discharge completely?
(v) Calculate the recovery time T
1
for
C
1
to recharge completely.
Given that,
V
CC
= 25 V
V
EE
= 15 V
R = 10 k
R
B
= 150 k
R
E
= 1 k
C= 0.05 F
Gating duration, T
g
= 300 S
h
ie
= 1.1 k
h
re
= 2.5 10
4
h
fe
= 50
h
oe
= 25 A/V
To calculate,
(i)
1
c
I
, for drawing waveform of
1
c
I
Vs for drawing
waveform of V
0
.
(ii) Slope error, e
s
= ?
(iii) Sweep speed and maximum value of sweep voltage
V
S(max)
= ?
(iv) Retrace time, T
r
= ?
(v) Recovery time, T
1
= ?
The circuit diagram of bootstrap sweep generator is shown in figure (1).
Q
2
+
R
i
R
Q
1
R
E
C
V
B1
V
EE
T
g
R
B
V
CC
D
+
V
0
2
B
I
1
C
I
1
B
I
Q
2
+
R
i
R
Q
1
R
E
C
V
B1
V
EE
T
g
R
B
V
CC
D
+
V
0
2
B
I
1
C
I
1
B
I
Figure (1): Bootstrap Sweep Generator
(i) Q
1
is Saturation Under Quiescent Conditions

) ( 1 sat
c
I
=
R
V
CC
=
3
10 10
25
= 2.5 mA
At t = T
g
,
1(recovery)
c
I

= h
fe
i
B
,
= h
fe
B
CC
R
V
=
3
10 150
25 50
= 8.33 mA
Sweep amplitude,
V
S
=
CC g
V T
RC
=
6 3
6
10 05 . 0 10 10
10 300 25

= 15 V
Now, the waveform for
1
c
I
and V
o
can be drawn as shown in figure (2).
T
r
V
0
300 S
15 V
t
8.33 mA
0
2.5 mA
1
c
I
T
r
V
0
300 S
15 V
t
8.33 mA
0
2.5 mA
1
c
I
Figure (2): Waveform of
1
c
I
and V
0
(ii) Slope Error (e
s
)
Slope error, e
s
=
1
]
1
+ +
1
1
C
C
R
R
A
i
V

CC
S
V
V
Let,
C
1
= 100 F
A
V
= 1
i
ie
R
h
... (1)
R
i
= h
ie
+ A
i
R
E
But,
A
i
=
E oe
fe
R h
h
+
+
1
1
R
i
= h
ie
+ 1
]
1
+
+
E oe
fe
R h
h
1
1
R
E
= 1.1 10
3
+
1
]
1
+
+
3 6
10 1 10 25 1
50 1
1 10
3
= 50.86 k
By substituting corresponding values in equation (1),
we get,
A
v
= 1
3
3
10 86 . 50
10 1 . 1
= 0.978
Slope error,
e
s
=
1
1
]
1
6
6
3
3
10 100
10 05 . 0
10 86 . 50
10 10
978 . 0 1

25
15
= 0.219 0.6
= 0.1314
e
s
= 13.14 %
(iii) Sweep Speed and V
S(max)
Sweep speed =
C
I
C
=
CC
V
RC
=
6 3
10 05 . 0 10 10
25

=
4
10 5
25
= 5 10
4
V/s
Maximum value of sweep voltage,
V
S(max)
= V
CC
= 25 V
And
V
S(max)
= Sweep-speed T
s
T
s
=
S(max)
Sweepspeed
V
=
4
10 5
25
=
4
5
10
= 500 s
(iv) Retrace Time (T
r
)
i
A
T
r
= CV
s
T
r
=
1
S
CC
fe
B
V
C
V
h
R R
1 1
1 1
] 1
1
1
1
]
T
r
=
3 3
6
10 10
1
10 150
50
25
15
10 05 . 0
1
]
1
=
4
8
10 33 . 2
10 3
T
r
= 128.57 10
6
= 128.57 S.
(v) Recovery Time (T
1
)
Charge lost during (T
g
+ T
r
) = Charge gained during T
1
i.e.,
R
V
CC
(T
g
+ T
r
) =
E
EE
R
V
T
1

T
1
=
R
V
CC

EE
E
V
R
(T
g
+ T
r
)
=
3
10 10
25

15
10 1
3
(300 10
6
+ 128.57 10
6
)
= 0.167 428.57 10
6
= 71.57 10
6
T
1
= 71.57 S
Q6. (a) Draw the bidirectional diode sampling
gate in the form of a bridge network and
explain its working.
For answer refer Unit-VI, Q11.
(b) Explain how a sampling gate is used in
chopper amplifier.
Chopper Amplifier
In this case sampling is done by synchronous
demodulater or which makes the output voltage V
o
to take
the shape of input signal V
i
by passing V
o
through a low-
pass filter such that only signal frequency appears at the
output and the square wave gets rejected. In this way the
amplified replica of original signal is obtained.
Operation of the Chopper Amplifier
Chopper amplifier is a device, used to amplify the
very small signals of the order of millivolts. The circuit
arrangement of chopper amplifier and its input and output
waveforms are shown below in figures (1) and (2)
respectively.
S
1
R
V
+
V
i
+
V
A
S
2
+
V
o
C
A-C amplifier
S
1
R
V
+
V
i
+
V
A
S
2
+
V
o
C
A-C amplifier
Figure (1): Circuit Diagram of Chopped Stabilized Amplifier
t
v
0 t
v
0
(a) Input Voltage
t
V
i
0 t
V
i
0
(b) Chopped Signal
t
V
A
0 t
V
A
0
(c) Modulated Signal
t
V
o
0 t
V
o
0
(d) Output Signal
Figure (2): Input and Output Waveforms of Chopped Amplifier
The low-frequency signal of amplitude V, shown in
figure 2(a) is applied at the input of the chopper amplifier. As
the switch S
1
at the input side is operated alternately. The
input signal gets chopped and the resulting chopped signal
shown in figure 2(b) is applied at the input of the A.C amplifier.
The amplitude of the chopped waveform is V when
S
1
is opened and is 0 when S
1
is closed.
As the frequency of operation of switch S
1
, is very
high when compared to the frequency of the input signal,
chopped signal is obtained as square wave of amplitude
proportional to V.
The chopped square wave is made to pass through
the A.C amplifier. The low cut-off frequency of A.C amplifier
is selected in such a way that it allows high frequency square
wave signal and alternates the low frequency signal. Thus
the output of the A.C amplifier is a modulated signal shown
in figure 2(c).
From the modulated signal, original signal can be
extracted by passing it through the capacitor and switch (S
2
).
Switch S
2
operates in synchronism with switch S
1
. Hence, in
the interval T
1
, negatives peaks of modulated signal
suppressed to 0 where as in the interval T
2
, positive peaks
suppressed to 0. To obtain the original signal, chopped signal
is made, pass through the low-pass filter. Thus, we get amplified
version of the input signal V, as shown in figure 2(d).
Q7. (a) What do you mean by synchronization?
For answer refer Unit-VII, Q1.
(b) What is the condition to be met for pulse
synchronization?
(c) Compare sine wave synchronization with pulse synchronization.
Answer : April/May-12, Set-4, Q7(c) M[6]
Q8. (a) Compare the RTL and DTL logic families in terms of Fan out, propagation delay, power
dissipated per gate and noise immunity.
For answer refer Unit-VIII, Q24.
(b) What is meant by tri-state logic? Draw the circuit of tri-state TTL logic and explain its opera-
tion in detail?
Tri-State Logic
For answer refer April/May - 11, Set-3, Q8(b)(iii).
Tri-State TTL Logic
A tri-state TTL two input NAND gate is as shown below.
Q
7
D
2
Q
3
D
1
Q
4
1.6 k
V
CC
130 4 k 1.6 k 4 k
A
B
Q
5
Q
1
Q
2
1 k
Tristate enable
Logic
inputs
Q
6
Q
7
D
2
Q
3
D
1
Q
4
1.6 k
V
CC
130 4 k 1.6 k 4 k
A
B
Q
5
Q
1
Q
2
1 k
Tristate enable
Logic
inputs
Q
6
Figure
Tri-state circuit is used in data multiplexing when a single bus is shared among different data sources. Hence for
multiplexing a tri-state circuit, gate should provide very high impedance when disabled. This is achieved in TTL NAND gate
by turning off both TTL totem-pole output transists at the same time.
Consider the above figure, the extra emitter on Q
1
and a steering diode connected to the collector of Q
2
are used to
turn off the output transistors, when the enable input is asserted (which is active low). When enable is asserted it drives Q
2
and hence Q
3
to cut-off and forward biases the diode D
2
which in turn turns off Q
4
.
When enable input is not asserted, the circuit behaves as a normal NAND gate.
Hence, the above circuit behaves as a tri-state TTL NAND gate providing high impedance at the output.
A B Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Output
L L OFF ON ON OFF OFF ON OFF H
L H OFF ON ON OFF OFF ON OFF H
H L OFF ON ON OFF OFF ON OFF H
H H ON OFF OFF ON ON OFF ON L

Jntu Hyd 2 2ece PDC Set 4

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Jntu Hyd 2 2ece PDC Set 4

Încărcat de

Drepturi de autor:

Formate disponibile

S.

54 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

i.e., just before closing the switch,

S-ar putea să vă placă și