Jntu Hyd 2 2ece PDC Set 2

S.
17 Pulse and Digital Circuits (April/May-2012, Set-2) JNTU-Hyderabad

( JNTU-Hyderabad ) B.Tech. II-Year II-Sem.
Code No.: R09220403/R09
B.Tech. II Year II Semester Examination
April/May - 2012
PULSE AND DIGITAL CIRCUITS
( Common to ECE, BME, ETM )
Time: 3 Hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
- - -
1. (a) Obtain an expression for the input impedance of RC differentiating circuit. Compare it with that of RL
differentiating circuit.(Unit-I, Topic No. 1.2)
(b) A pulse of 5 V amplitude and width of 0.5 msec is applied to high pass RC circuit consisting of R = 22 k and
C = 0.47 F. Estimate the output voltage levels and sketch the waveform. Also determine the percentage tilt in
the output. [5+10] (Unit-I, Topic No. 1.2)
2. (a) A voltage signal of 10 sin t is applied to the circuit with ideal diodes shown in figure. Estimate the maximum
and minimum values of output waveform and maximum current through each diode. Also draw the input-output
waveforms with proper explanation. (Unit-II, Topic No. 2.1)
V
i
V
o
10 k
+
10 k
D
1
4 V
D
2
4V
V
i
V
o
10 k
+
10 k
D
1
4 V
D
2
4V
Figure
(b) A square wave input is applied to the clamper circuit shown in figure. By taking the effect of source resistance,
R
s
, the diode forward dynamic resistance R
f
and the diode reverse dynamic resistance R
r
into account, draw the
equivalent circuits for the following cases,
(i) When the diode is conducting
(ii) When the diode is not conducting. [9+6] (Unit-II, Topic No. 2.3)
C
R
D
+
R
s
V
s
V
o
C
R
D
+
R
s
V
s
V
o
Figure
Se t - 2
S o l u t i o n s
S. 18 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Hyderabad )
3. (a) A simple diode-switch circuit and the input signal applied to it are shown in figure. Draw and explain the
waveforms representing the variation in minority carrier concentration, diode current I and diode voltage V
D
with respect to input signal variations.(Unit-III, Topic No. 3.1)
I
V
D
R
V
i
+
V
i
V
F
t
1
t
o
V
R
Input signal Diode-switch circuit
I
V
D
R
V
i
+
I
V
D
R
V
i
+
V
i
V
F
t
1
t
o
V
R
Figure
(b) Derive an expression for collector-to-emitter breakdown voltage with open-circuited base, BV
CEO
in terms of
collector-to-base breakdown voltage, with open-circuited emitter, BV
CBO
. [8+7] (Unit-III, Topic No. 3.2)
4. What for the circuit shown in figure is used? Discuss the role of the diodes, D1 and D2 in the circuit. With neat
waveforms and necessary equations, explain the operation of the circuit, without D1, D2, R3 and R3'. [15]
(Unit-IV, Topic No. 4.3)
Q
2
D2
C
2
R
1
R
2
R
3
D1
C
1
Q
1
'
3
R
V
CC
2
C
R
1
C
R
Q
2
D2
C
2
R
1
R
2
R
3
D1
C
1
Q
1
'
3
R
V
CC
2
C
R
1
C
R
Figure
5. (a) Draw and explain the operation of transistorized miller sweep generator. Show that the sweep speed for miller
circuits is same as in the case where the capacitor C charges through a resistor R directly from the source V.
(Unit-V, Topic No. 5.2)
(b) A transistor bootstrap ramp generator is to produce a 15 V, 5 ms output to a 2 k load resistor. The ramp is to
be linear within 2%. Design a suitable circuit using V
CC
= 22 V, V
EE
= 22 V and transistor with h
fe(min)
= 25,
h
ie
= 1.1 k, h
re
= 2.5 10
4
, h
oe
= 25 A/V, V
BE(sat)
= 0.8 V, V
BE(active)
= 0.7 V, V
CE(sat)
= 0.2 V. The input pulse has an
amplitude of 5 V, pulse width = 5 ms and space width = 2.5 ms. [7+8] (Unit-V, Topic No. 5.2)
6. (a) Explain how to cancel the pedestal in sampling gate with suitable circuit diagram. (Unit-VI, Topic No. 6.3)
(b) Explain the function of a sampling gate used in sampling scopes. [7+8] (Unit-VI, Topic No. 6.2)
S. 19 Pulse and Digital Circuits (April/May-2012, Set-2) JNTU-Hyderabad
7. (a) Explain the factors which influence the stability of a relaxation divider with the help of a neat waveforms.
(Unit-VII, Topic No. 7.2)
(b) A UJT sweep operates with valley voltage (V
v
) = 3 V, peak voltage (V
p
) = 16 V and = 0.5. A sinusoidal
synchronizing voltage of 2 V peak is applied between bases and the natural frequency of the sweep is 1 kHz,
over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the sync signal? [7+8]
(Unit-VII, Topic No. 7.2)
8. (a) With the help of circuit diagram explain the purpose of clamping diode in a positive diode AND gate.
(Unit-VIII, Topic No. 8.1)
(b) What is meant by active pull-up? Draw the circuit of TTL active pull-up NAND gate and explain its operation
with the help of function table. [7+8] (Unit-VIII, Topic No. 8.2)
Q1. (a) Obtain an expression for the input
impedance of RC differentiating circuit.
Compare it with that of RL differen-
tiating circuit.
Answer : April/May-12, Set-2, Q1(a) M[5]
Input Impedance of RC Differentiating Circuit
Figure (1) illustrates RC differentiating circuit
+
R
C
i
V
i
V
o
+
R
C
i
V
i
V
o
Figure (1): RC Differentiating Circuit
From Ohms Law
iR V
V
i
= i Z
i
Where,
Z
i
= Input impedance.
And
Z
i
= R +
1
j C

1
i
Z R
j C
+
or

1
2
i
Z R
j fC
+
(Q = 2f )
Input impedance of RC differentiating circuit is,
Z
i
= R +
1
j C
= R +
1
2 j fC
SOLUTIONS TO APRIL/MAY-2012, SET-2, QP
Input Impedance of RL Differentiating Circuit
Figure (2) illustrates RL differentiating circuit.
+
L
R
i
V
i
V
o
+
L
R
i
V
i
V
o
Figure (2): RL Differentiating Circuit
Input impedance is expressed as,
Z
i
=
l
V
i
Z
i
= R + jL
or
= R + j2 f L (
Q
= 2 f)
2
i
Z R j L R j fL + +
Therefore, the input impudence of RL differentiating
circuit is,
2
i
Z R j L R j fL + +
(b) A pulse of 5 V amplitude and width of
0.5 msec is applied to high pass RC
circuit consisting of R = 22 k and C =
0.47 F. Estimate the output voltage
levels and sketch the waveform. Also
determine the percentage tilt in the
output.
Answer : April/May-12, Set-2, Q1(b) M[10]
Given that,
For a high pass RC circuit,
Pulse Amplitude (A) = 5 V
Pulse width, t
p
= 0.5 msec
R = 22 k
C = 0.47 F
V
01
(t), V
02
(t) = ?
% tilt = ?
The input pulse applied to high pass RC circuit is
represented in figure (1).
V
i
(t) Input
0
t
t = 0 t = t
p
= 0.5 ms
Pulse width
V
i
(t) Input
0
t
t = 0 t = t
p
= 0.5 ms
Pulse width
Figure (1): Input Pulse
The output of the circuit can be estimated by
considering two different cases.
Case (i): Circuit response to 5 V step occurred at t = 0,
The output voltage in this case is expressed as,
V
01
(t) = Ae
t/RC
for 0 < t < t
p
At t = tp, the response to first step pulse is
V
01
(t) = Ae
tp/RC
= V
p
Where,
RC = 22 k 0.47 F
= 22 10
3
0.47 10
6
= 0.01034 sec

/
p
t RC
p
V Ae

V
p
= 5 e
01034 . 0
10 5 . 0
3

= 5 e
0.0483
= 5 0.952
= 4.76
01
( ) 4.76 V
p
V t V
The output voltage at first step response is 4.76 V.
Case (ii): Circuit response to 5V step occurred at t = 0.5 ms
The output voltage falls by A from
V
p
at t = +
p
t
Thus, the output voltage at t = +
p
t
is expressed as,
V
02
(t
P
+
) = V
p
A
= 4.76 5
= 0.24
V
02
(t
P
+
) is the undershoot at t = t
P
The response to the second step pulse is expressed as,
V
02
(t) = A ) 1 (
/
RC t
P
e
RC t t
P
e
/ ) (
= 5
01034 . 0
) 10 5 . 0 (
01034 . 0
10 5 . 0
3 3
1

,
_
t
e e
= ( )
3
( 0.5 10 )
0.01034 0.0483
5 1
t
e e

,
1
1
1
]
= 5(0.952 1)
01034 . 0
) 10 5 . 0 (
3
t
e
= 0.24
01034 . 0 / ) 10 5 . 0 (
3
t
e
3
( 0.5 10 )/ 0.01034
02
( ) 0.24
t
V t e

The waveform for the two outputs is illustrated in
figure (2).
5 V
t
p
t
V
01
(t) V
02
(t)
5 V
Input pulse
V
0
(t)
V
P
= 4.76 V
0
5 V
t
p
t
V
01
(t) V
02
(t)
5 V
Input pulse
V
0
(t)
V
P
= 4.76 V
0
Figure (2): Output Waveform for the Total Response
The expression for % tilt is given below,
% P= 100
A
V A
p
=
100
5
76 . 4 5
= 0.048 100
= 4.8%
% 8 . 4 % P
Q2. (a) A voltage signal of 10 sin t is applied to the circuit with ideal diodes shown in figure.
Estimate the maximum and minimum values of output waveform and maximum current
through each diode. Also draw the input-output waveforms with proper explanation.
V
i
V
o
10 k
+
10 k
D
1
4 V
D
2
4V
V
i
V
o
10 k
+
10 k
D
1
4 V
D
2
4V
Figure
Given that,
For a circuit with ideal diodes,
Voltage signal, V
i
= 10 sin t
Maximum and minimum values of output waveform = ?
Maximum current through each diode = ?
The given circuit is,
V
i
V
o
10 k
+
10 k
D
1
4 V
D
2
4V
+10
10
0
V
i
V
o
10 k
+
10 k
D
1
4 V
D
2
4V
V
i
V
o
10 k
+
10 k
D
1
4 V
D
2
4V
+10
10
0
+10
10
0
Figure (1)
Case (i)
V
i
<
1
R
V
i.e., 4
D
1
is ON, D
2
is OFF because D
1
is reversed biased and D
2
is forward biased. The figure above is modified as follows.
V
i
V
out
10 k
10 k
4V
4V
i
1
V
i
V
out
10 k
10 k
4V
4V
i
1
Figure (2)
From figure (2)
Voltage across resistors is,
10
o i
V V
+
4
10
o
V +
= 0
V
o
V
i
+ V
o
+ 4 = 0
2V
o
+ 4 = V
i
2V
o
+ 4 = 10 (
Q
V
i
= 10 V)
2V
o
= 14
V
o
= 7 V
7V
o
V
Maximum current through diode D
1
applying KVL to
figure,
V
i
i
1
10 k + 4 i, 10 k = 0
V
i
i
1
20 k + 4 = 0
10 i
1
20 k + 4 = 0
i
1
20 k 6 = 0
i
1
20 k = 6
i
1
=
k 20
6
i
1
= 0.3 mA
mA 3 . 0
1
i
Maximum current through the diode D
1
is 0.3 mA.
Case (ii)
4 < V
i
< 4
D
1
is OFF, D
2
is also OFF
So D
1
and D
2
does not conduct the modified circuit
is,
V
i
10 k
10 k
4V
4V
V
o
V
i
10 k
10 k
4V
4V
V
o
Figure (3)
From figure (3), the output voltage, V
o

10
o i o
V V V
+
= 0
V
o
V
i
= 0
o i
V V
As no current flows through resistor so the current
in figure (3) is zero.
0
2
i
Case (iii)
V
i
> 4
D
1
is OFF, D
2
is ON
So D
2
conducts and D
1
does not conduct the
modified circuit is
V
i
10 k
10 k
4 V
4 V
V
o
i
2
V
i
10 k
10 k
4 V
4 V
V
o
i
2
Figure (4)
From figure (4),
4V
o
V
Maximum current through the diode D
2
, applying KCL
i
2
=
4
10
i
V
i
2
=
4 10
10
i
2
= 0.6 mA
mA 6 . 0
2
i
Maximum current through diode, D
2
is 0.6 mA
The input-output waveform is shown in figure (3).
+10 V
10 V
0
+ 10 V
4 V
7 V
10 V
+10 V
10 V
0
+10 V
10 V
0
+ 10 V
4 V
7 V
10 V
+ 10 V
4 V
7 V
10 V
Figure (5): Input-Output Waveforms
(b) A square wave input is applied to the
clamper circuit shown in figure. By
taking the effect of source resistance R
s
,
the diode forward dynamic resistance
R
f
and the diode reverse dynamic
resistance R
r
into account, draw the
equivalent circuits for the following
cases,
(i) When the diode is conducting
(ii) When the diode is not conducting.
C
R
D
+
R
s
V
s
V
o
C
R
D
+
R
s
V
s
V
o
Figure
C
R
D
+
+
+
R
s
V
s
V
o
C
R
D
+
+
+
R
s
V
s
V
o
Figure
(i) When the Diode is Conducting
Figure (a) represents the equivalent circuit when
diode (D) is conducting.
+
V
s
+
+
V
c
C
R
s
V
o
R
f
|| R R
f
i
F
i
F
Forward current
+
V
s
+
+
V
c
C
R
s
V
o
R
f
|| R R
f
i
F
i
F
Forward current
Figure (a): Equivalent Circuit When Diode is Conducting
(ii) When the Diode is not Conducting
+
V
s
+
+
+
V
c
C
R
s
V
o
R || R
r
R
i
R
i
R
Reverse current
+
V
s
+
+
+
V
c
C
R
s
V
o
R || R
r
R
i
R
i
R
Reverse current
Figure (b): Equivalent Circuit When Diode is Not Conducting
Figure (b) represents the equivalent circuit when
diode (D) is non-conducting.
Q3. (a) A simple diode-switch circuit and the
input signal applied to it are shown in
figure. Draw and explain the waveforms
representing the variation in minority
carrier concentration, diode current I
and diode voltage V
D
, with respect to
input signal variations.
I
V
D
R
V
i
+
V
i
V
F
t
1
t
o
V
R
I
V
D
R
V
i
+
I
V
D
R
V
i
+
V
i
V
F
t
1
t
o
V
R
Figure
I
V
D
R
V
i
+
V
i
V
F
t
1
t
o
V
R
I
V
D
R
V
i
+
I
V
D
R
V
i
+
V
i
V
F
t
1
t
o
V
R
Figure (i)
Figure (i) illustrates the waveforms representing the
variation in minority carrier concentration, diode current I
(i.e., forward and reverse currents) and diode voltage V
D
with respect to input signal variations.
Storage time t
s
Transition time t
t
Reverse recovery time t
rr
t
1
t
2
t
3
V
R
V
D
o
Reverse current,
R
V
I
R
R

o
I
Forward current,
F
F
V
I
R
Minority carrier
Concentration
(P
n
P
no
)
V
F
V
R
t
1
t
1
t
2
t
3
(d) Diode
voltage
(c) Diode
current
(b) Minority carrier
concentration
Ideal
response
(a) Input voltage
t
t
t
t
V
in
Storage time t
s
Transition time t
t
Reverse recovery time t
rr
t
1
t
2
t
3
V
R
V
D
o
Reverse current,
R
V
I
R
R

o
I
Forward current,
F
F
V
I
R
Minority carrier
Concentration
(P
n
P
no
)
V
F
V
R
t
1
t
1
t
2
t
3
(d) Diode
voltage
(c) Diode
current
(b) Minority carrier
concentration
Ideal
response
(a) Input voltage
t
t
t
t
V
in
Figure (ii): Waveforms for Diode-switch Circuit
Three events occur because of the nature of the applied input signal. They are,
Event (a)
V
f
is the applied forward voltage till the time duration t
1
. The resistance (R) is maintained large enough, such that the
drop across forward biased diode is lesser than that of drop across R. If forward diode resistance is ignored, then the
forward diode current, I
F
is nearly V
F
/R.
Event (b)
The voltage applied is reversed abruptly at t
1
and ' V
R
' is applied to the diode-switch circuit which is simply a
reverse voltage. So the diode must suddenly be turned off. Since, the number of minority carriers consume certain amount
of time to decrease from P
n
- P
no
to O (at the junction), the diode is not switched OFF instantly. This results in the reversal
of current (I) in the circuit.
This reverse current (I
R
) continues to flow till the minority carrier concentration is reduced to zero i.e., till t
2
.
Mathematically, it is expressed as I
R
= V
R
/R.
Event (c)
The diode voltage begins to reverse and the diode
current also starts decreasing from t
2
. The diode gets
completely reverse-biased and attains a complete steady
state at t = t
3
.
The time taken by the diode current to reduce to its
reverse saturation value i.e., from t
2
to t
3
is known as
Transition interval or Transition time.
(b) Derive an expression for collector-to-
emitter breakdown voltage with open-
circuited base. BV
CEO
in terms of
collector-to-base breakdown voltage,
with open-circuited emitter, BV
CBO
.
The general expression for common emitter current
gain is given as,
h
FE
=

1
... (1)
Where,
= Common-base current gain.
If avalanche multiplication is taken into account, then
the equation (1) becomes
*
FE
h =
*
*
1
M
M
1
... (2)
Where,
M = Avalanche multiplication factor and
expressed as,
M =
n
CBO
CB
BV
V
,
_
1
1
... (3)
Where,
V
CB
= Voltage between collector and base
BV
CBO
= Collector-to-base breakdown voltage
with open-circuited emitter.
In equation (2), if M is set equal to 1 (i.e., for M = 1),
*
fE
h becomes infinity and breakdown occurs in the transistor.
i.e., M = 1
M =
1
=
n
CBO
CB
BV
V
,
_
1
1
1
n
CBO
CB
BV
V
,
_
= 1

CBO
CB
BV
V
=
( )n
1
1
V
CB
= B V
CBO

n
1
... (4)
V
CB
in equation (4) can be replaced by V
CE
, as at
transistor breakdown the value of V
CB
is much greater than
the small forward base-to-emitter voltage (V
BE
).
BV
CEO
= BV
CBO

n
1
... (5)
Where,
BV
CEO
= Collector to emitter breakdown
voltage with open circuited base.
From equation (1), h
FE
=

1
1 =
FE
h
=
FE
h
1
) 1 ( Q
1 =
FE
h
1
... (6)
Substituting equation (6), in equation (5), we get,
BV
CEO
= BV
CBO

n
FE
h
1
.... (7)

1
n
CEO CBO
FE
BV BV
h

Q4. What for the circuit shown in figure is used? Discuss the role of the diodes, D1 and D2 in the
circuit. With neat waveforms and necessary equations, explain the operation of the circuit, without
D1, D2, R3 and R3'.
Q
2
D2
C
2
R
1
R
2
R
3
D1
C
1
Q
1
'
3
R
V
CC
2
C
R
1
C
R
Q
2
D2
C
2
R
1
R
2
R
3
D1
C
1
Q
1
'
3
R
V
CC
2
C
R
1
C
R
Figure
Answer : April/May-12, Set-2, Q4 M[15]
Q
2
D2
C
2
R
1
R
2
R
3
D1
C
1
Q
1
'
3
R
V
CC
2
C
R
1
C
R
Q
2
D2
C
2
R
1
R
2
R
3
D1
C
1
Q
1
'
3
R
V
CC
2
C
R
1
C
R
Figure
The circuit is used to eliminate distortion problem in collector waveforms of astable multivibrater. Due to distortion,
an exact square wave is not obtained, instead the vertical rising edges are rounded at the output. This process is known as
rounding. Figure illustrates rounding in collector waveform.
Rounding
t
1 2
,
c c
V V

V
c
Rounding
t
1 2
,
c c
V V

V
c
Figure (1): Rounding Problem in Collector Waveform
Rounding can be avoided and an exact square wave output can be obtained with the addition of the diodes D
1
, D
2
and resistors R
3
and
'
3
R . Figure 4.2 represents collector coupled astable multivibrater with D
1
, D
2
, R
3
and
'
3
R .
[ ]
2 1
,
c c
V V
R
C
D
2
C
1
R
2
R
3
R
C
D
1
C
2
V
CC
Q
2
ON
Q
1
OFF
R
1
C
2
+
C
1
'
3
R R
C
D
2
C
1
R
2
R
3
R
C
D
1
C
2
V
CC
Q
2
ON
Q
1
OFF
R
1
C
2
+
C
1
'
3
R
Figure (2): Distortion Elimination
When transistor Q
1
is in OFF state, its collector voltage rises abruptly to V
cc
. Hence the diode, D
1
becomes reverse
biased. Thus C
2
charges through R
3
instead of R
c
. Since the current is not passing through the resistor R
c
, the collector
voltage can be rapidly increased to V
cc
. As a result, the rounding at the collector is completely eliminated. Figure (3)
represents the elimination of rounding in collector waveform.
V
cc
Rounding eliminated
V
CE(sat)
1
c
V
t
V
cc
Rounding eliminated
V
CE(sat)
1
c
V
t
Figure (3): Rounding Elimination in Collector Waveform
The given circuit without D
1
D
2
, R
3
and
'
3
R becomes astable multivibration.
For remaining answer refer Unit-IV, Q20.
Q5. (a) Draw and explain the operation of transistorized miller sweep generator. Show that the
sweep speed for Miller circuits is same as in the case where the capacitor, C charges through
a resistor, R directly from the source V.
Transistorized Miller Sweep Generator
For answer refer Unit-V, Q13.
Sweep Speed for Miller Circuits
The sweep speed of the miller circuit is expressed as,
Sweep speed =
i
C
... (1)
From Ohms law
V '= iR'
i =
'
'
R
V
... (2)
Substituting equation (2) in equation (1), we get,
Sweep speed =
C
R
V
'
'
=
C R
V
'
'
... (3)
But, for Miller circuits,
V' = V
R R
R
i
i
+
... (4)
And
R ' =
R R
R R
i
i
+
... (5)
Substituting equations (4) and (5) in equation (3),
we get,
Sweep speed=
( )
( )
i
i
i
i
R
V
R R
R R
C
R R
_

+ ,
1
1
+
]
=
RC
V
... (6)
From equations (3) and (6), we get
RC
V
C R
V

'
'
speed Sweep
Hence, it is showed that the sweep speed for Miller
circuits is same as in the case where the capacitor, C charges
through a resistor, R directly from the source V.
(b) A transistor bootstrap ramp generator
is to produce a 15 V, 5 ms output to a 2
k load resistor. The ramp is to be linear
within 2%. Design a suitable circuit
using V
CC
= 22 V, V
EE
= 22 V and
transistor with h
fe(min)
= 25, h
ie
= 1.1 k ,
h
re
= 2.5 10
4
, h
oe
= 25 A/V,
V
BE(sat)
= 0.8 V, V
BE(active)
= 0.7 V, V
CE(sat)
=
0.2 V. The input pulse has an amplitude
of 5 V, pulse width = 5 ms and space
width = 2.5 ms.
Apri/May-12, Set-2, Q5(b) M[8]
Answer :
Given that,
For a transistor bootstrap-ramp generator,
Sweep amplitude, V
s
= 15 v
Load resistor, R
E
= 2 k
Gate duration, T
g
= 5 ms
Ramp is linear within 2%

s
= Slope error = 2%

s
=
100
2
= 0.02
V
CC
= 22 V
V
EE
= 22 V
h
fe(min)
= 25
h
ie
= 1.1 k
h
re
= 2.5 10
4
h
oe
= 25 A/V
V
BE(sat)
= 0.8 V
V
BE(active)
= 0.7 V
V
CE(sat)
= 0.2 V
Input pulse amplitude = 5V
Pulse width = 5 ms
Space width = 2.5 ms
To design a Circuit of Boot Strap Time Base Generator
To design transistor bootstrap time-base generator
circuit we need to determine the values of components, R
1
C, C
1
and R
B
.
To Calculate R
The expression for slope error (e
s
) is given by,
(1 )
s
s V
cc i
V R
e A
V R
1
+
1
]
Where,
V
cc
= 22 V,
V
s
= 15 V
And R
i
, R, A
v
= ?
Amplitude of the sweep,
g
c
cc
s
T
R
V
V
s
g cc
V
T V
RC
RC =
15
10 5 22
3

7.33 ms RC
The expression for current gain (A
I
) of an emitter
follower circuit is,
E oe
fe
I
R h
h
A
+
+
1
1
Where,
h
fe
= 25, h
oe
= 25 A/v, R
E
= 2 k
A
I
=
) 10 2 ( 10 25 1
25 1
3 6
+
+
=
3
10 50 1
26
+
24.76
I
A
E I ie i
R A h R +
= 1.1 k + 24.76 2 10
3
= 1.1 10
3
+ 24.76 2 10
3
= 10
3
(1.1 + 49.52)
= 50.62 10
3
50.62 k
i
R
Also,
1 A
v
=
i
ie
R
h
1 A
v
=
3
3
10 62 . 50
10 1 . 1
1 A
v
= 0.0217
(Where, A
v
= Voltage gain of emitter follower)
Consider that C
1
is very large,
Slope error, C
s
=
,
_
+ ) 1 (
v
i cc
s
A
R
R
V
V
0.02 =
22
15
1
]
1
0217 . 0
10 62 . 50
3
R
0.68
3
10 62 . 50
R
+ 0.68 (0.0217) = 0.02

3
10 62 . 50
68 . 0
R
+ 0.014 = 0.02

3
10 62 . 50
68 . 0
R
= 0.02 0.014

3
10 62 . 50
68 . 0
R
= 0.006
R =
68 . 0
10 62 . 50 006 . 0
3

R = 446.6
6 . 446 R
To Calculate C
R
RC
C
C =
6 . 446
ms 33 . 7
= 16.4 10
6
= 16.4 F
F 4 . 16 C
To Calculate C
1
C C 10
1
= 10 16.4 F
= 164 F
F 164
1
C
To Calculate R
B
1
(sat )
(actual)
CC BE
B
B
V V
R
I
Where,

1
B
I
=
1
C
fe
I
h
As
1
C
I

~ I
R
, under quiescent condition

1(sat)
CC D CE
R
V V V
I
R

Assume, V
D
= 0.5
I
R
=

6 . 446
2 . 0 5 . 0 22
= 0.047 A
47 mA
R
I
Substituting I
R
=
1
C
I
in
1
B
I
, we get,

(min) 1
B
I
=
fe
C
h
I
1

(min) 1
B
I
=
25
mA 47
=
25
10 47
3
= 1.88 10
3
= 1.88 mA

1(min)
1.88 mA
B
I
And
(min) 1 (actual) 1
5 . 1
B B
I I
= 1.5 1.88 10
3

(actual) 1
B
I
= 2.82 mA
Now,
R
B
=
1(actual)
(sat) CC BE
B
V V
I
=
3
10 82 . 2
8 . 0 22
= 7.51 10
3
= 7.51 k
k 51 . 7
B
R
The values for designing the circuit are R = 446.6 , C = 16.4 F, C
1
= 164 F, R
B
= 7.51 k.
Figure represents the circuit designed for transistor bootstrap ramp generator.
C
B
R
B
= 7.51 k
C
1
= 164 F
I
R
= 147 mA
D
V
CC
= 22 V
C = 16.4 F
Q
1
V
i
V
i
R
E
= 2 k
V
EE
= 22 V
Q
2
1 B
I 2.82mA
1
E
I
R= 446.6
2 B
I
C
B
R
B
= 7.51 k
C
1
= 164 F
I
R
= 147 mA
D
V
CC
= 22 V
C = 16.4 F
Q
1
V
i
V
i
R
E
= 2 k
V
EE
= 22 V
Q
2
1 B
I 2.82mA
1
E
I
R= 446.6
2 B
I
Figure (1): Designed Circuit of Bootstrap Time Base Generator
Q6. (a) Explain how to cancel the pedestal in sampling gate with suitable circuit diagram.
Figure (1) illustrates a pedestal associated with sampling gate.
V
CC
V
C
V
s
+
_
+
_
R
C
Q
2
Q
1
R
c
V
0
+
_
V
CC
V
C
V
s
+
_
+
_
R
C
Q
2
Q
1
R
c
V
0
+
_
Figure (1)
Pedestal is the typical appearance of sampled portion of the signal at the output during a gating interval. The
pedestal can be cancelled with the help of a circuit used in figure (2) with symmetrical arrangement. Transistor Q
1
acts as a
gating transistor and transistor Q
2
is employed to eliminate the pedestal. The bases of Q
1
and Q
2
transistors are supplied
with gating voltages of opposite polarity.
V
s
V
c
V
c
+

+
V
CC
R
C
+
V
o
Q
1
Q
2
1 BB
V
2 BB
V
V
s
V
c
V
c
+

+
V
CC
R
C
+
V
o
Q
1
Q
2
1 BB
V
2 BB
V
Figure (2): A Sampling Gate Circuit Used to Cancel the Pedestal
If the control signal is high, then Q
1
is ON and Q
2
is OFF at transmission time t
p
.
As a result, current flows through resistor R
C
and transistor (Q
1
) from V
CC
. Similarly, if the control signal is LOW, then
Q
1
is OFF and Q
2
is ON. So, the current flows through R
C
and Q
2
from supply voltage V
CC
.
In order to make equal transistor currents, the base voltages
1
BB
V
and
2
BB
V
are adjusted along with amplitude of
gate signal. This leads to a constant quiescent level of output voltage in a steady state and hence the pedestal is cancelled.
(b) Explain the function of a sampling gate is used in sampling scopes.
For answer refer Unit-VI, Q16.
Q7. (a) Explain the factors which influence the stability of a relaxation divider with the help of a
neat waveforms.
For answer refer Unit-VII, Q6.
(b) A UJT sweep operates with valley voltage (V
v
) = 3 V, peak voltage (V
p
) = 16 V and = 0.5. A
sinusoidal synchronizing voltage of 2 V peak is applied between bases and the natural
frequency of the sweep is 1 kHz, over what range of sync signal frequency will the sweep
remain in 1:1 synchronism with the sync signal?
For answer refer Unit-VII, Q13.
Q8. (a) With the help of circuit diagram explain the purpose of clamping diode in a positive diode
AND gate.
For answer refer Unit-VIII, Q7.
(b) What is meant by active pull-up? Draw the circuit of TTL active pull-up NAND gate and
explain its operation with the help of function table?
Active Pull-Up
Pulling of output level from LOW level to HIGH level using active components (such as transistor and FETs) is
known as Active Pull-up in digital circuits.
TTL Active Pull-up NAND Gate
Figure illustrates an active pull-up circuit of TTL NAND gate. Transistor Q
4
acts as an active device. It gives
charging current to output capacitor C
o
.
Hence, the circuit is known as active pull-up circuit and the output is known as active pull-up output.
B
2
Q
3
C
o
V
o
C
3
D
E
4 Q
1
A
B
B
1
C
2
+ V
CC
= 5V
2
C
R
4
C
I
2
C
R
1
B
R
Q
2
2
E
R
Q
4
B
4
4
B
I
B
2
Q
3
C
o
V
o
C
3
D
E
4 Q
1
A
B
B
1
C
2
+ V
CC
= 5V
2
C
R
4
C
I
2
C
R
1
B
R
Q
2
2
E
R
Q
4
B
4
4
B
I
Figure: Circuit Diagram of TTL NAND Gate with Active Pull-up
The output can also be called as Totempole output because the transistors Q
4
and Q
3
form a pair of totem-pole. Q
2
serves as a phase splitter for totem-pole transistors Q
4
and Q
3
. The use of active pull-up in TTL NAND gate is to increase
the speed without any increase in power dissipation. Diode (D) in the circuit is used to maintain Q
4
in cutoff state, when the
gate output is low i.e., logic 0.
When both the inputs A and B are maintained at logic 1 (i.e., High), Q
1
is ON. Hence Q
3
conducts and Q
4
is OFF (since
Q
3
and Q
4
are totempole pair).
Therefore, the output of the gate is O (i.e., LOW) which is given by, V(o) = V
CEsat
= 0.2 V.
If any of the inputs (A or B) are low i.e., at logic O, the transistor Q
4
starts conducting and hence enters into saturation
region. This leads to the changing of capacitance C
o
through Q
4
and D. The current flowing through transistor Q
4
falls
during the charging period of C
o
. When C
o
reaches V(1), HIGH, Q
4
enters into cut off region, the expression for output
voltage, when the gate output is HIGH is given by,
V(1) = V
cc

3
( )
o Q
V
(V
o
) D
TTL NAND Gate with Active Pull-up Function Table
Table below represents the function table for TTL NAND gate with active pull-up.
Inputs
A B Q
1
Q
2
Q
4
Q
3
Output
0 0 OFF OFF ON OFF 1
1 1 ON ON OFF ON 0
Table

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17 Pulse and Digital Circuits (April/May-2012, Set-2) JNTU-Hyderabad

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