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EE 314-Digital Electronics Laboratory

6. TTL AND CMOS LOGIC STRUCTURES

I. INTRODUCTION 1. Objectives TTL and CMOS are the most widely used logic structures in digital electronics applications. In this experiment, TTL and CMOS logic structures will be characterized and compared. II. PRELIMINARY WORK 1. You can refer to Chapter 7 of Digital Integrated Circuits by T.A. DeMassa and Z. Ciccone and your EE312 course notes for information on TTL logic structures and sections 23.1-23.5 from DeMassa/Ciccone and sections 10.1-10.3 from Microelectronic Circuits by Sedra/Smith (5th edition) for information on CMOS logic structures. 2. Figure 6-1 shows the schematic view of a TTL inverter. Assume that VBEsat=0.8 V, VCEsat=0.2 V and R=0.2. Find the operation mode of each BJT and I1, I2, I3 and I4 when Vin= 0 V and Vin= 5 V.

Figure 6-1. The schematic view of a TTL inverter. 3. What are the advantages of the circuit given in Part 2 when compared with the basic BJT inverter (RTL inverter that you also constructed in Experiment 2)? What are the limitations of the circuit? 4. Figure 6-2 shows the schematic view of a CMOS inverter. Calculate the output voltage for Vin=0, 2.5, and 5 V for this circuit. VTp= -2 V, VTn= 2 V, Kn=Kp=0.5 mA/V2.

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Figure 6-2. The schematic view of a CMOS inverter. 5. Simulate the circuit given in Part 4 (Figure 6-2) using LtSpice and obtain the transfer characteristic for Kp= 1, 5, 20 and 300 uA/V2 (fix Kn at 50 uA/V2). You can obtain the transfer characteristics by sweeping the input voltage from 0 to 5 Volts using DC Sweep analysis. Be sure to set the increment small enough so that the smooth behavior in the transfer characteristics can be seen. For each Kp value, determine and record high and low noise margins. Plot the noise margins versus K n/Kp. Comment on the variation of the noise margins with the K ratio. Note: LtSpice is a freeware SPICE simulator which can be downloaded from the following link: http://ltspice.linear.com/software/LTspiceIV.exe If you do not have any familiarity with making simulations using SPICE, you can find a tutorial which covers all the basics of SPICE in general and using LtSpice here: http://www.mems.eee.metu.edu.tr/courses/ee313/Spice_Tutorial_ver2010.pdf

III. EXPERIMENTAL WORK

Basic TTL Inverter

1. Figure 6-3 shows the schematic view of a TTL inverter circuit and the internal diagram of CA3046 BJT array chip. Construct the TTL inverter circuit by using two npn BJTs in CA3046. Connect pin 13 to ground.

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Figure 6-3. The schematic view of a TTL inverter circuit and the internal diagram of CA3046 BJT array chip. 2. Use the multimeter in voltage measuring mode to find the operation modes of the BJTs for Vin= 0V and Vin= 5V. 3. Connect the multimeter in the current measuring mode between the collector of Q1 and the base of Q2. Connect the output of the circuit to Channel 1 of the scope. Starting from 0 V, slowly increase the input voltage until the output voltage starts to decrease significantly and observe the base current of Q2. Record VIL. 4. Now connect the multimeter in current measuring mode between the emitter of Q1 and Vin. Start from 5V and while observing the base current of Q2, slowly decrease the input voltage until the output voltage starts to increase rapidly. Record V IH. Measure the emitter current of Q1 for Vin= 0 and 5 V. 5. Explain the operation of this inverter. 6. Find the noise margins of the inverter. Why is the difference between V IL and VIH is small? Why is the low noise margin much smaller than the high noise margin? 7. What is the limiting case for determining the fan-out limit of this circuit? Comment briefly on what is expected when VOUT=VOH? 8. (Optional) Ground the circuit input and connect a resistance between the output and ground with a value equivalent to the fan-out of 1. Measure the output voltage and comment on the result. What is the limitation of this circuit? How can the circuit be improved for a reasonable fan out limit? 9. Now, find the fan-out limit of the circuit for VOUT=VOL.

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Hint: Connect a 1 K resistor in series with a 50 K potentiometer between the output and VCC. Change the potentiometer resistance and record the current through the resistor when VOUT exceeds the acceptable low level voltage. 10. Disconnect the input of the circuit from the power supply. Connect a 100 pF capacitor between the output and ground. Set the output of the function generator to High Z. Connect the input of the circuit to the output of the function generator and set the waveform to a square wave with 5 VPP amplitude and 2.5 V offset at a frequency of 1 kHz. Measure and record the rise and fall times of the output.

CMOS Inverter
11. Figure 6-4 shows the schematic view of a CMOS inverter. Construct this circuit by using CD4007 MOS array chip. Chip pin numbers are shown in the figure. Connect pin 14 to VDD and pin 7 to ground.

Figure 6-4. The schematic view of a CMOS inverter and CD4007 pin diagram. 12. Connect the multimeter in current measuring mode between V DD and pin 11. Connect the input to 0V and 5V and determine the power dissipation of the circuit in each case. Comment on the result. Does the CMOS inverter dissipate static power? Explain your reasoning. 13. Set the output of the function generator to a triangle wave with 5 Vpp amplitude, 2.5 V offset and 1 kHz frequency. Connect the input to Channel 1 and output to Channel 2 of the scope and observe the transfer characteristic on the scope in the X-Y mode. 14. Determine the noise margins and compare them with those of the TTL inverter. 15. Connect a 100pF capacitor between the output and ground. Change the waveform at the function generator to a square wave of 10 kHz. Connect a 1 k resistor between pin 9 and ground. Connect Channel 1 of the scope to the input and Channel 2 to pin 9
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and observe the voltages on the scope. Comment on the voltage waveform on the resistor which also represents the current waveform during switching. 16. Connect the multimeter between VDD and 11. Find the power dissipation PD of the inverter as the frequency is varied (f = 1, 10, 100 and 1000 kHz) and comment on the frequency dependence of the power dissipation in CMOS circuits.

TTL and CMOS IC NAND GATES

17. 74LS00 TTL NAND Gates i) Figure 6-5 shows the pin diagram of 74LS00 and the internal structure of one of the NAND gates. Insert 74LS00 IC into your breadboard. Connect pin 14 to 5 V and pin 7 to ground. Connect a 10 nF capacitor between VCC and ground. Leave the other pins unconnected and measure the voltages on pins 1,2,3,4,5,6,8,9,10,11,12, and 13. Comment on the results.

Figure 6-5. The pin diagram of 74LS00 and the internal structure of one of the NAND gates. ii) Now use one of the NAND gates in the IC. Short circuit the two inputs and obtain the no load noise margins by connecting the inputs to the power supply (Do not exceed 5 V) and observing the output voltage on the multimeter as the input voltage is changed. Measure the input currents under high and low level input conditions. Connect the inputs to ground. Connect a resistor equivalent to a fan-out of 15 between the output and ground and measure the output voltage. Compare the fanout limitation of this circuit (schematics shown above) with the circuit in Part 1 of Experimental Work (TTL inverter). Comment on the result by stating the reason for higher fan-out in this circuit. Disconnect the resistor connected at the output. Connect a 100 pF capacitor between the output and ground. Apply a 5 Vp-p square wave of 1 kHz frequency and 2.5 V offset at the input and measure the rise and fall times of the NAND gate and
5

iii) iv)

v)

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compare them with those measured in Part 1 of Experimental Work. State the reasons of any differences you observe in the switching times of this circuit and the circuit in Part 1. 18. 74HC00 CMOS NAND Gates i) Repeat (i) and (ii) of Part 17 for 74HC00 NAND gate. In Figure 6-6, the pin diagram of 74HC00 is given. Compare the noise margins with the 74LS00 NAND gate.

Figure 6-6. The pin diagram of 74HC00. ii) iii) Determine the noise margins for VDD= 7V and compare them with those measured under VDD= 5V. Set VDD to 5V. Connect a 100 pF capacitor between the output and ground and measure the rise and fall times. Compare the switching response with that of the TTL NAND gate and comment on the result. Now, set the output of the function generator to NOISE and apply a noise signal with 1.5V offset to the input as the output is connected to the oscilloscope. (Do not exceed the peak to peak amplitude of 5V). Starting from 0V slowly increase the amplitude until output signal becomes noisy, and record the input noise amplitude. Is there a relation between the recorded noise level and noise margin of the gate?

iv)

v)

REQUIRED IC LIST CA3046 CD4007 74LS00 74HC00 BJT Array Chip MOS Array Chip Four 2-input NAND gates (TTL) Four 2-input NAND gates (CMOS)

Experiment 6

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TTL AND CMOS LOGIC STRUCTURES

NAMES: SECTION: 1. 2.

Basic TTL Inverter (Fig. 6-3)

Operation modes of the BJTs: Q1: VIL= IE(Q1)= Explain the operation of this inverter briefly. VIH= Q2:

NMH=

NML=

Why is the low noise margin much smaller than the high noise margin?

What is the limiting case for determining the fan-out limit of this circuit? Comment briefly on what is expected when VOUT=VOH.

(Optional) Measure the output voltage when the resistor is connected: Vo= Comment on the result. What is the limitation of this circuit? How can the circuit be improved for a reasonable fan out limit?

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Fan-out limit of the circuit for VOUT=VOL trise= tfall=

CMOS Inverter (Fig. 6-4)

Does the CMOS inverter dissipate static power? Comment on the result.

Plot the transfer characteristics, indicating important points.

NMH=

NML=

Compare the noise margins with those of the TTL inverter.

Draw the waveform which corresponds to the current through the inverter during switching and comment on it.

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Determine the power dissipation values at various frequencies and comment on the result. f=1 kHz PD= f=10 kHz PD= f=100 kHz PD= f=1MHz PD=

74LS00 TTL NAND Gates (Fig. 6-5)

i)
V1 = V2 = V3 = V4 = V5 = V6 = V8 = V9 = V10 = V11 = V12 = V13 = Comments:

ii) NMH= iii) Input high:

Input low:

NML= Iin= Iin=

iv) Output voltage when load resistance is connected: Vo=

Compare the fan-out limitation with TTL inverter. Comment on the result.

v) trise=

tfall=

Compare rise and fall times with TTL inverter and comment on the result.

74HC00 CMOS NAND Gates (Fig. 6-6)

i)
V1 = V2 = V3 = V4 = V5 = V6 = V8 = V9 = V10 = V11 = V12 = V13 =
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Comments:

NMH=

NML=

Compare the noise margins with the TTL NAND gate.

ii) NMH=

NML=

Compare the noise margins with those when VDD=5V.

iii) trise=

tfall=

Compare the switching response with that of the TTL NAND gate and comment on the result.

iv) Input noise amplitude when output becomes noisy: Vnoise= v) Is there a relation between the recorded noise level and noise margin of the gate?

Experiment 6

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