Q. Define incompletely specified machine? How an incompletely specified machine can be simplified?

Simplify the following incompletely specified machine.

Ans. In real life, for all states for all inputs, the next state or outputs or both are not mentioned. For such types of machines, where for all states for all inputs the next state, or output or both are not mentioned, those types of machines are called incompletely specified machine. In the previous machine for state A for 00 input no next state and outputs are specified. Hence the previous machine is an example of incompletely specified machine. Simplification: An incompletely specified machine can be simplified by the following steps: (a) If next state is not mentioned for a state, for a given input, put a temporary state T in that place. (b) If output is not mentioned, make it blank. (c) If next state and output are not mentioned, put a temporary state T in next state place and nothing in output place. (d) Add the temporary state T in the present state column, putting T as next state and no output for all inputs. By following the previous steps, the simplification of the previous incompletely specified machine is as follows: 4.Discuss about any one method of fault diagnosis in sequential circuits using an example? Sequential Fault Diagnosis Methods

In sequential fault diagnosis the process of fault location is carried out step by step, where each step depends on the result of the diagnostic experiment at the previous step. Such a test experiment is calledadaptive testing. Sequential experiments can be carried out either by observing only output responses of the UUT or by pinpointing by a special probe also internal control points of the UUT (guided probing). Sequential diagnosis procedure can be graphically represented as diagnostic tree. Guided-Probe Testing Guided-probe testing extends edge-pin testing process by monitoring internal signals in the UUT via a probe which is moved (usually by an operator) following the guidance provided by the test equipment. The principle of guided-probe testing is to backtrace an error from the primary output where it has been observed during edge-pin testing to its physical location in the UUT. Probing is carried out step-by-step. In each step an internal signal is probed and compared to the expected value. The next probing depends on the result of the previous step. A diagnostic tree can be created for the given test pattern to control the process of probing. The tree consists of internal nodes (circles) to mark the internal lines to be probed, and of terminal nodes (rectangles) to show the possible result of diagnosis. The results of probing are indicated as passed (P) or failed (F). Typical faults located are opens and defective components. An open between two points A and B in a connection line is identified by a mismatch between the error observed at B and the correct value measured at A. A faulty device is identified by detecting an error at one of its outputs, while only correct values are measured at its inputs. The most time-consuming part of guided-probe testing is moving the probe. To speed-up the fault location process, we need to reduce the number of probed lines. A lot of methods to minimize the number of probings are available.

Example:

Let have a test pattern 1010 applied to the inputs of the circuit. The diagnostic tree created for this particular test pattern is shown. On the output x8 , instead of the expected value 0, an erroneous signal 1 is detected. By backtracing (indicated by bold arrows in the diagnostic tree) the faulty component NOR- x5 is located.

Diagnostic tree allows to carry out optimization of the fault location procedure, for example to generate a procedure with minimum average number of probes. 5. Define a diagnosable sequential machine and how it can be constructed. 6.Give the PLA realization of the following functions using a PLA with 5 inputs, 4 outputs and 8 AND gates. f ABCDE m 1 ( )( ) , , , , 0,1,2,3,11,12,13,14,15,16,17,18,19,27,28,29,30,31 = f ABCDE m 2 ( )( ) , , , , 4,5,6,7,8,9,10,11,20,21 7.What are the different faults present in PLA and how to test these faults? the faults are: 1) input inverters stuck-at-1 and 0, 2) AND gate inputs and outputs stuck-at-i and 0, 3) OR gate inputs and outputs stuck-at-1 and 0,

4) output inverters stuck-at-I and 0. We are now ready to present a test generation algorithm. At the top level, the algorithm consists of seven steps. Informally, the steps are: 1) input a description of the PLA to be tested; 2) select a fault fe F which has not yet been detected; 3) generate a test t forf and add it to T; if no test exists, output f and indicate that it is undetectable; 4) determine which other faults in F are detected by t; 5) if there are still faults which have not been considered 6) using the E vector which indicates inverted determine test results for the fault-free PLA; 7) output the test set T and the correct test results. 8.Draw the basic model form of NOR S-R latch and explain its function with truth table. SR NOR latch An SR latch, constructed from a pair of cross-coupled NOR gates (an animated picture). Red and black mean logical '1' and '0', respectively. When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of crosscoupled NOR logic gates. The stored bit is present on the output marked Q. While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

b) Give a state assignment without critical races to the following asynchronous machine shown in figure below. 9.For the circuit shown below, generate the test pattern to detect an S-a-1 fault at P2 using path sensitization. 11.State the Essential Prime Cubes EPC test criteria as a theorem, and then prove it? 12.Discuss the capabilities and limitations of Finite State Machine (FSM) Finite state machine can be defined as a type of machine whose past histories can affect its future behavior in a finite number of ways. To clarify, consider for example of binary full adder. Its output depends on the present input and the carry generated from the previous input. It may have a large number of previous input histories but they can be divided into two types: (i) Input combination that produces carry; (ii) Input combination that produces no carry. Implying the past histories can affect the future behavior in a finite number of ways (here 2). What are the capabilities and limitations of finite-state machine? Ans. Let a finite state machine have n states. Let a long sequence of input be given to the machine. The machine will progress starting from its beginning state to the next states according to the state transitions. However, after some time the input string may be longer than n, the number of states. As there are only nstates in the machine, it must come to a state it was previously been in and from this phase if the input remains the same the machine will function in a periodically repeating fashion. From here a conclusion that for a n state machine the output will become periodic after a number of clock pulses less than equal ton can be drawn. States are memory elements. As for a finite state machine the number of states is finite, so finite number of memory elements are required to design a finite state machine.

Limitations: (a) No finite state machine can be produced for an infinite sequence.

Lets consider the design of a finite state machine which receives a long sequence of 1. The machine will produce an output 1, when the input string length will be equal to [ p(p+1)]/2, where p=1,2,3,...... and 0 for all other cases. Therefore for p = 1, [p(p + 1)]/2 = 1. In first place there will be o/p 1. For p = 2, [p(p + 1)]/2 = 3. In third place there will be o/p 1. For p = 3, [p(p + 1)]/2 = 6. In sixth place there will be o/p 1. For this type of machine the input output form is as follows:

Here the output does not become eventually periodic after a certain number of clock pulses. Hence from this type of sequence no finite state machine can be produced.

(b) No finite state machine can multiply two arbitrary large binary numbers. Lets consider multiplying two binary numbers given that are input serially to a finite state machine for multiplication. The inputs are given to the machine with least significant bit (LSB) first then the other bits. Suppose, to multiply 2m 2m, where m>n (n is the number of states of the Machine), the result will be 22m. The 2m is represented by one 1 followed by m number of 0's (Simlarly 23=1000). Hence the inputs are given to the machine from t1 to tm + 1 time. Throughout the time the machine produces 0'. At tm
2 + 2

times the input stops and the machine produce output 0 followed by 1 from tm

to t2m time. In the time period tm + 1 to t2m, no input is given to the machine, but the machine produces

outputs. As m > n, according to the definition of Finite State machine the output must be periodic

and the period must be < m. As we are not getting any repeating output sequence, therefore Binary Multiplication of two arbitrary large binary numbers is not possible to design by using finite state machine. 13.A fundamental-mode asynchronous machine has two inputs and a single output. The output becomes 1 only after the following input sequence: 1 2 x x : 00 11 01 . In addition, if x1 and x2 have the same value, then x2 cannot change before x1. a) Construct a primitive flow table. b) Assuming a flicker-free fast output, reduce the table to minimal form. c) Make a valid assignment, and write expressions for the excitation functions. d) Implement the circuit

14.It is necessary to determine the final state of the machine shown below when the initial state is unknown and only output sequences from the machine are available to the experiments. Derive the procedure to determine the final state of the machine. ----- 469/70/71/72/ PS NS,2 x=0x=1 A B,0 C,0 B A,0 D,1 C D,1 B,0 D A,1 D,1 15. Explain the properties of a successor tree. ---- 458/9/. 6. a) Explain about the fault model of PLA, with an example and derive the test vector set for the example.

16.Explain the EPC theorem that is used in IISC algorithm to minimize the function to be implemented on PLA. ----- 148/9/50/1/2 7. Apply COMPACT algorithm to fold the PLA column wise for the given SSR table for columns. Column SSR

A 3,6,8 B 1,2,4,5,9,11 C 1,3,6,7,9,10 D 2,5,7,8,12 E 1,3,6,11 F 4,6,7,8,10 G 1,3,5,7,9 H 6,8,12 17.Design a flow table for a fundamental mode sequential circuit with two inputs, x1 and x2 and one output z. z=1 if both equal to 0, but only if x1 becomes 0 before x2. b) For the given reduced flow table, find an assignment which contains no critical races and requires a minimum of secondary variables. 18.a) Implement the following Boolean function by Hazard free OR-AND network F=(0,2,6,7). ---- 293_12.6.1 b) Explain signature analysis with example ---- 431 19.a) Homing tree. - 469/70 b) Synchronizing tree. - 471/2/3 PS NS X=0 X=1 A B,0 D,0 B A,0 B,0 C D,1 A,0 D D,1 C,0

18.Design a Mealy sequential circuit which investigates an input sequence X and will produce an output Z=1 for any input sequence ending in 0010 or 100 X=110010010100101 Z=000101101001010