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BJT BIAS PROBLEMS

Problem 1) Estimate the collector current for each transistor in the diode-connected transistor biasing circuit. shown. Compute and compare the collector currents over a temperature range -50C to +50C. \ Answer Estimate the Q1 collector current, and so also the Q2 collector current as (100.7)/10 = 0.93 ma. *Bias Illustration VCC 1 0 DC 10 RM 1 2 10K Q1 2 2 0 Q2N3904 RL 1 3 4.7K Q2 3 2 0 Q2N3904 .LIB EVAL.LIB .PROBE .DC TEMP -50 50 .1 .END The first plot compares the Q1 and Q2 collector currents over the specified temperature range. There is about a 20 a variation in current, about a 2% absolute change. The next plot shows the relative change between the two currents (normalized to the Q2 collector current.); this is less than 0.1%.

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Problem 2) The current-mirror biasing circuit discussed above is redrawn to the right. Compute the circuit performance and compare with the estimates made before. Answer *Current mirror illustration RM 1 0 Q1 1 1 2 Q2N3906 Q2 3 1 2 Q2N3906 RL 3 0 5K Q3 3 0 4 Q2N3904 RE 4 5 10K V+ 2 0 DC 10 V- 5 0 DC -10 .LIB EVAL.LIB .PROBE .DC TEMP -50 50 .2 .END

5K

PSpice computes the transistor currents as shown; estimated values calculated also are tabulated: NAME MODEL IC(computed) IC(calculated) Q1 Q2N3906 -1.83E-03 -1.86E-03 Q2 Q2N3906 -2.15E-03 -1.86E-03 Q3 Q2N3904 9.27E-04 9.3E-04

Note the influence of the Early Effect on the Q2 current. The computed value of Vo is 6.1 volts, while the estimated value calculated is 4.65 volts. The difference is primarily the consequence of the Early Effect increase in the Q2 current. Nevertheless the calculation using the simpler model provides a meaningful estimate of currents. At least as important the simpler model also provides a useful indication of the relative importance of various components in determining the currents. The computed value of Vo over a -50C to +50C temperature range is plotted next.

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Problem 3) Given the circuit shown: estimate the collector current. Use the PWL model analysis above, which provides the relation

Answer Estimate VBE as 0.7 volt. (Recall that the collector current will change an order of magnitude for roughly a 50 mv change in junction voltage, two orders of magnitude for a 0.1 volt change. Since the base supply voltage is 4 volts an uncertainty in VBE of as much as 0.4 volt results in only a 10% change in the value of the numerator. Similarly with a minimum of 99 the second term in the denominator is 0.15 K compared to the first term value of 3.3 K. Ignoring the second term entirely changes the denominator by less than 5%. The emitter current estimate of 0.96 ma is largely independent of the transistor parameters VBE and . A PSpice computation of the collector current over a 100C temperature range is plotted below.

Problem 4) Estimate the collector current in the PNP bias circuit shown. Answer Replace the BJT by the simplified PWL model described above; use nominal transistor parameter values 120, VBE 0.7v. Note that the biasing arrangement reduces the influence of the BJT parameters in establishing the current value, and so 'typical values' from manufacturer's specifications may be used with some confidence. As described before replace the biasing resistors by their Thevenin equivalent 33K||82K = 23.5K, and the Thevenin voltage (82/(82+33))10 = 7.13v to obtain the equivalent circuit as shown. Avoid the not uncommon careless topological error of confusing the PNP transistor with a NPN transistor. Write a base-emitter loop equation as was done for the NPN configuration discussed above; again avoid the topological error confusing the emitter and collector. Solve for IC = 120IB=0.91 ma. A PSpice analysis provides the collector current 0.935 ma. Introductory Electronics Notes The University of Michigan-Dearborn 41-3 Copyright M H Miller: 2000 revised

Problem 5) a) Use the expression for the emitter current derived before for the circuit shown to derive the expression to the right for changes due to variation of VBE and . Interpret the expression in terms of the design guidelines discussed.

b) Evaluate the following argument. Suppose the collector current consists of a DC component and a sinusoidal component, i.e., ICQ + A sin (t). The average power provided by the source, ICQVCC, is constant, and this is the same whether the AC signal is present or not. But the energy expended in the resistor increases since the average value of the sine-squared is not zero. Conservation of energy then requires the collector dissipation to be smaller with the AC signal present than in its absence. Thus the transistor operates cooler with a signal than without! Hence for safe operation with maximum AC signal the power rating for the transistor should be such that it is able to operate safely in the absence of an AC signal. Answer a) The first term is the effect of a variation in VBE, and to minimize the per cent change in IE make the variation small compared to VS-VBE. The second term is the effect off a change of , and to minimize the per cent change in IE make the denominator, in particular the second term, large compared to 1. b) Maximum transistor dissipation occurs during the absence of a signal. Problem 6) Design the transistor circuit for a 0.1 ma variation about a nominal collector current of 1 ma. Assume a range of temperature variation of 50C to + 50C.

Answer The variation in VBE over a 100C temperature range is about 0.2 volt ( 2 mV/C). To be somewhat more conservative (and suggestive) write VBE = 0.65 0.15 volt, allowing a bit for a threshold voltage different from 0.7 v. The current is may vary 10%. Suppose we (arbitrarily) allocate 5% to variations in VBE, allowing the remaining 5% for variations. Then set VBB to a minimum of 20 times the 0.15 volt variation, or 3 volts. The numerator term then will be constrained. To limit the effect of a variation the second term in the denominator is made small compared to RE. If we simply neglect this term we can estimate RE (3-0.65)/1 = 2.35K. This is not a standard value, so use a standard 10% tolerance value of 2.2K. (This will tend to make the current higher than 1ma; a choice of 2.5K would make it smaller.) To limit the influence of make RB/(+1) small compared to RE. If it is made less than 5% of RE for the minimum value of expected then it will have less than a %% influence. Hence using a minimum value for of 100 (see manufacturers specifications) make RB = (101)RE/20 = 11.1 K. Use a Introductory Electronics Notes 41-4 Copyright M H Miller: 2000 The University of Michigan-Dearborn revised

standard 10% tolerance value of 10 K. A PSpice computation of collector current over the temperature range is plotted below for the nominal and for 50% values.

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Problem 7) Assume (subject to verification) that the Q2 base current can be neglected compared to the Q1 emitter current. (Why ?) Calculate the voltage at the collector of Q2. Assume 2N3904 devices. Answer The voltage across the 220 is less than that across the 680, and hence both emitter currents are roughly in proportion to the resistors. With a > 100 the base currents will be an order of magnitude or more greater than the emitter currents. Neglecting the Q2 base current (compared to the Q1 emitter current) allows the Q1 biasing to be treated independently of Q2. Hence

Determine IE(Q2) from the Q1 emitter voltage. To substantiate the approximation used verify that the Q2 base current, 5.13/121 = 0.04 ma is small compared to the Q1 emitter current. For comparison a PSpice operating point computation provides IE(Q1) = 4.3 ma and IE(Q2) = 9.98 ma. Problem 8 All the transistors in the symmetrical circuit shown are identical (Use 2N3904). Determine the collector voltage of Q2. Suggestion: Determine the collector current of T3 first, and take advantage of the symmetry of the Q1, Q2 circuitry. Answer Use the simplified PWL transistor model. This model neglects the Early Effect, and so the Q3 current can be estimated without explicit knowledge of the collector voltage.

Because of the symmetry, and supposing some uniformity in nature, the collector current of Q3 is divided equally between Q1 and Q2, i.e., IE(Q1) = IE(Q2) = 4.7 ma. Since IC(Q2) IE(Q2) the Q2 collector voltage is estimated as 9 - 4.7 = 4.3 v. For comparison a PSpice operating point computation provides the following data: NAME MODEL IC Q1 Q2N3904 5.39E-03 Q2 Q2N3904 5.39E-03 41-6 Q3 Q2N3904 1.08E-02 Copyright M H Miller: 2000 revised

Introductory Electronics Notes The University of Michigan-Dearborn

Problem 9 Calculate the emitter current in the circuit shown. Comment: Circuit designers who do not verify assumptions they make are often surprised. Answer Assume, subject to verification, that the transistor is biased in normal forward mode, i.e., emitter forward-biased and collector reverse-biased. Replace the base biasing resistors by a Thevenin equivalent voltage source of 9(3.3/(3.3+6.8)) = 2.94v, in series with a resistance of 3.3||6.8 = 2.22K. Use a nominal of 120 and a VBE of 0.7v to estimate the emitter current as (2.94-0.7)/(1+(2.22/121)) = 2.2 ma. But since the collector current is essentially equal tot he emitter current the voltage drop across the 5.6K collector resistance would be 12.3v, making the collector negative! The assumed reverse-biased state of the collector diode is inconsistent, and the calculation is invalid. The actual collector junction state is actually forward-biased, i.e., the transistor must be operating saturated. The PWL model in this case is as shown to the right (both diodes ON). Solve (for example) for the node voltage V = 2.2v, and so the emitter current is 1.5 ma, and the collector current is 1.2 ma. A PSpice analysis computes a collector current of 1.3 ma, and an emitter current of 1.6 ma. Problem 10 Anticipate (and later verify) that both transistor base currents are small compared to the current in the base biasing resistors. ( That current will be roughly 10/(68+15+18) 100 A. Neglecting the collector-emitter voltage drops indicates that the transistor collector current will be less than 10/(3.9+1) 2 mA. With 120 the base currents are estimated to be less than 20 A.) Estimate the collector current of T2. Improve the collector current estimate by a recalculation using the base currents estimated from the first calculation, rather than neglecting them. Answer Neglecting the base currents the voltage at the base of Q1is 10(18/(18+15+68)) = 1.78v. Estimate the Q1 emitter voltage to be 1.08v, and the Q1 emitter current as 1.08ma. Estimate the base voltage of Q2 to be 10((15+18)/(18+15+68)) = 3.27v, and so the Q2 emitter voltage is estimated to be 2.57v. Finally the Q2 collector voltage is estimated to be 10 -(3.9)(1.08) = 5.79v. A PSpice netlist is shown on the right and the computed currents and node voltages are below. These computed results should be compared to values calculated as described in the problem statement.

Cascade Biasing RB3 6 4 RB2 4 2 RB1 2 0 RC2 6 5 RE1 1 0 CV 6 0 Q2 5 4 Q1 3 2 .LIB .OP .END

68K 15K 18K 3.9K 1K DC 10 3 Q2N3904 1 Q2N3904

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NODE VOLTAGE (1) .9338 (2) 1.5973 NAME MODEL IBC IC BE BC CV

(3) 2.3707 Q2 Q2N3904 6.73E-06 9.20E-04 6.62E-01 -3.38E+00 4.04E+00

(4) 3.0331 Q1 Q2N3904 6.98E-06 9.27E-04 6.64E-01 -7.73E-01 1.44E+00

5) 6.4118

(6) 10.0000

Problem 11 Calculate the collector voltage of Q2. Assume 2N3904 devices. Refer to the discussion above for simplifying suggestions. Answer Neglect the base current of Q2 relative to I, the collector current of Q1, and write the loop equation as described above: 9 = 3.3I + 0.7 + 47(I/120) + 0.7 to determine I 2.06 ma. The estimate the Q1 collector voltage as 9 (2.06)(3.3) = 2.2 v. The Q2 emitter voltage then is 1.5 v, and the Q2 emitter current is 1(1.5/1) + (1.5 - 0.7)/47 = 1.52ma. A PSpice computation gives the collector current of Q1 as 2.1ma and the collector current of Q2 as 1.36ma. Problem 12 Determine the Q2 collector voltage for the complementary pair' biasing configuration shown. Assume 2N3904 and 2N3906 devices.

Answer Note that the Q2 emitter current is about the same magnitude as the Q1 collector current. The Q2 base current should be negligible compared to the Q1 collector current (an assumption to be verified), and if this approximation is applied calculation of the Q1 biasing is independent of Q2. Determine that the Q1 emitter current is 1.15ma. The Q1 collector voltage then is 8.21v, and so the Q2 emitter current is estimated to be 2.0ma. The currents are consistent with neglecting the base currents. Node voltages and device currents computed by PSpice are shown below. NODE VOLTAGE (1) 3.2453 (2) 8.1928 (3) 2.5773 (4) 12.0000 (5) 8.9131 (6) 4.5061

NAME MODEL IC

Q1 Q2N3904 1.16E-03

Q2 Q2N3906 -2.05E-03

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Problem 13 A forward-biased junction operates over large current ranges with small voltage changes. The bias circuit shown takes advantage of this to reduce sensitivity to supply voltage variations. I0, assumed to have been made large compared to the base currents, is (approx.) (VCC - 2VBE)/R0. This current biases Q1 so as to provide a voltage VBE across R1, so that the Q2 emitter current is approximately VBE/R. And VBE is relatively insensitive to changes in VCC . For R0 = 8.2K, R = 470, and VCC = 10 volts estimate the Q2 collector current. Assume 2N3904 devices. Use PSpice to step VCC from 0 to 10 volts, and plot IC(Q2) vs VCC .

Answer Assuming a nominal value of 0.7 volt for VBE the Q2 collector current would be approximately 0.7/.47 = 1.49ma. This assumes that VCC is sufficiently large to forward-bias both emitter junctions, i.e., VCC > 1.4v. A netlist is shown to the right and the PSpice computations are plotted below. Junction Voltage Bias RO3 2 8.2K Q1 2 1 0 Q2N3904 Q2 4 2 1 Q2N3904 R1 1 0 470 VCC 3 0 DC 10 V+ 4 0 DC 10 .DC LIN VCC 0 10 .1 .PROBE .OP .LIB EVAL.LIB .END

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Problem 14) Calculate (approximately) the transfer characteristic Vout vs. V in for the circuit shown, for -1v Vin 1v. Compare the calculated prediction against a computed plot.

Answer Useful approximate information can be obtained from not much more than inspection of the circuit diagram (with the PWL BJT model in mind as a guide). Suppose for example Vin is such that the transistor is operating in the normal forward active mode. An upper limit on the collector current is obtained by ignoring the collector-emitter voltage drop; IC <1 0/5.6 = 1.8 ma. The base current more than likely will be negligible compared to the other currents the base node; assume this to make estimates (subsequently verifying the adequacy of the approximation from the estimates). Neglecting the base current, and allowing for a nominal 0.7 volt emitter junction voltage drop [Vout - 0.7]/10 [0.7 - Vin]/1.8 or Vout 4.595.56Vin. The voltage gain, i.e., the slope of this line, is -5.56. When the transistor is just cutoff the emitter junction voltage is 0.7v, and the transistor draws no current. Hence The transistor saturates when the current drawn through the 5.6K collector resistor reduces Vout to (roughly) 0.7 volts. The estimates are superimposed on a PROBE plot of the transfer characteristic.

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Problem 15) Calculate (approximately) the transfer characteristic Vout vs Vin for the circuit shown, for 0 V in 10v. Compare the calculated prediction against a computed plot. Answer Assuming normal operating mode the 2N3906 transistor is (approximately) a DC current source with a collector current of

Note that 22||68 = 16.6K and the term in the calculation of the emitter current is relatively small if >>16.6/2.2 = 7.56. The PNP current splits between the 5.6K load and the NPN collector; the latter transistor also is assumed to operate in normal mode for the present calculation. Saturation of the NPN transistor occurs when the collector-emitter voltage of Q1 is approximately zero, i.e., This condition occurs when Vin V(3) 2.7v. With Q1 saturated increasing Vin increases the Q1 emitter current but decreases the collector current. Hence V(4) V(3) Vin begins to increase. Eventually Q2 will saturate but we do not consider that region of operation further; it is not a region of particularly useful operation. At the other extreme the NPN device is cut off for Vin 0 ( or more nearly a few tenths volt), and Vout (1.27)(5.6) = 7.1v. An estimate for the transfer characteristic is as drawn to the right. * Inverter Illustration VIN 1 0 RIN 1 2 Q1 4 2 3 RE1 3 0 RB21 5 0 RB22 7 5 Q2 4 5 6 RE2 7 6 VCC 7 0 RL 4 0 .LIB .OP .DC .PROBE .END EVAL.LIB VIN 0 15 .05 DC 0 1K Q2N3904 2.2K 68K 22K Q2N3906 2.2K DC 15 5.6K

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A computed characteristic (PSpice netlist follows) is plotted below.

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