DIGITAL SIGNAL PROCESSING FOR DEEP SPACE TRANSPONDER

L. Simone
(1)
, S. Cocchi
(1)
, M. DAttilia
(1)
, M. Delfino
(1)
, A. Delfino
(1)
, G. Boscagli
(2)
(1)
Alenia Spazio
Via Marcellina 11 - 00131 Rome (Italy)
Email: l.simone@roma.alespazio.it
(2)
Formerly Alenia Spazio, now ESA
Email: G.Boscagli@esa.int
INTRODUCTION
The progress of Digital Signal Processing techniques and the improvements of the Very Large Scale Integration (VLSI)
technologies allow the implementation of digital modem for Deep Space Transponder (DST). Accordingly, a new class
of DST based on digital architecture has been developed by Alenia for the ESA next Deep Space Missions (Rosetta,
Mars Express). Besides, the digital-based design makes the proposed architecture suitable for a wide range of space
applications other than deep space missions.
Traditionally, DST provides up-link carrier tracking, command data demodulation, ranging signal turn-around and
down-link carrier generation and modulation. The receiver digital architectures have the following advantages with
respect to a fully analog solution:
Receiver reconfigurability (for carrier loop bandwidth) according to the received signal input power
Easy implementation of narrow loop bandwidths
Inclusion of data demodulation capability
Data rate flexibility with matched filtering implementation
Interface optimization based on the extensive use of command and telemetry housekeeping in digital format
Design flexibility with receiver tuning based on software constants
On-board regenerative ranging.
Besides the frequency synthesis and the modulation process based on Numerically Controlled Oscillator (NCO) offer a
great flexibility in terms of channel selection, data rate, modulation format and spectral shaping.
This paper is presented in three sections. The first section provides an architectural overview of a digital DST. The
second part offers in-depth description of the implemented algorithms and functions. Finally, the third part deals with
the employed technology.
DEEP SPACE TRANSPONDER ARCHITECTURE
Fig.1 shows the Alenia DST architecture developed for Rosetta and Mars Express missions. It is composed by tree
main blocks: the receiver section (with S-band and X-band front-end), the 5 W S-band transmitter and the low power (7
dBm) X-band transmitter [1]. The receiver section is based on a digital architecture as will be detailed in the following.
The transmitter sections perform the function of transmitting and modulating the down-link signal in order to provide
the ground stations with the telemetry signal and the ranging signal demodulated by the receiver. The DST frequency
plan is based on the Sampled Phase Locked Loop (SPLL) approach and on the use of the Direct Digital Frequency
Synthesis (DDFS). This architectural solution is very attractive, both in terms of size and output spectral purity, when
high multiplication factors are required. Besides the Numerically Controlled Oscillator (NCO), based on the Coordinate
Rotation Digital Computer (CORDIC) algorithm, allows great design flexibility with wide range tracking capability. In
coherent mode, the down-link frequencies include the up-link Doppler contribution
d
F evaluated by the
microprocessor and scaled by the relevant turn-around ratio. In non-coherent mode the down-link frequencies are fixed.
In general future deep space missions require transponders capable of up-link in X-band and down-link both in X and K
band (X/X/K DST). Indeed the selection of X and K bands offer better link performance, in particular when accurate
radio science experiment are required [2]. Alenia DST design allows to replace the S-band with the K-band transmitter
leaving almost unchanged all the other functions included the digital signal processing.
DIGITAL SIGNAL PROCESSING FUNCTIONS
The receiver analog section performs the signal down-conversion, filtering and amplification in order to provide the
proper level to the Analog-to-Digital Converter (ADC) input. An analog wide-band Automatic Gain Control (AGC) is
required to keep constant the signal-plus-noise power at the ADC input.
The carrier loop closure at Intermediate Frequency (IF) allows the application of the coherent sampling: the signal is
sampled at the fixed intermediate frequency
1
F with a clock frequency
1
4F and the IF-to-baseband conversion is
eliminated. The proposed sampling scheme produces alternatively in-phase and quadrature baseband samples, allowing
the receiver digital signal processing section to perform the complex carrier demodulation without the use of a
multiplier. With this approach, only one ADC is required and the phase and amplitude imbalances are avoided, being
the mixing accomplished in the digital domain. The IF digitized samples are passed to the receiver digital section
implementing signal tracking and data demodulation functions. The digital receiver section is based on a Receiver
Application Specific Integrated Circuit (Rx ASIC), which mainly performs the high speed processing tasks, and on a
Microprocessor, which allocates the low rate processing tasks (Fig.2).
Fig. 1 Deep Space Transponder: architectural block diagram
Fig. 2 Digital receiver: functional block diagram
Quadr at ur e
Cha nne l

ADC
4 F
1
I n-phas e
Channel
Eve n/ Odd
Deci mat i on

Cost as
Lo o p
Det ect or

Sub- Car r i er
Loop
Fi l t er
Sub- Car r i er
NCO
Carri er
Lo o p
Filter
Carri er
Lock
Det ect or
Rx NCO Bas e
2
nd
L O
Generat i on
1 3F
1
+ F
d 2
nd
I F
strip
1
4
F
1

+

F
d
DTTL
&
Mat ched Fi l t er
Car r i er
NCO
F
1
F
1
Rx ASIC
Mi croproces s or
I/D
To Ra ngi ng DAC
S-Tx
SPLLL
S-Tx
NCO
X- Tx
SPLL
X- Tx
NCO
240F
1
+R
s
F
d
880 F
1
+R
x
F
d
K
s
K
x
S - Tx NCO
Base
X- Tx NCO
Base
R
a
n
g
in
g
C
h
a
n
n
e
l
Sub-carri er
Lock
Det ect or
Cl oc k
Recover ed Dat a
F
1
2/ 3 F
1
+ F
d
/ 3
2/ 3 F
1
+ R
x
F
d
/ 6
2/3 F
1
+ R
s
F
d
/ 3
221 F
1
+ F
d
2
nd
IF
4 F
1
ASI C
P Memor i es
DAC
Phase
Modul at or
2
nd
LO Gener at i on
1
st
IF ADC
AGC
S- Rx
Front - End
X- Rx
Front - End
749 F
1
+ F
d
1s t LO Gener at i on
1s t LO Gener at i on
To
Decoder
T
e
l
e
m
e
t
r
y
T
e
le
c
o
m
m
a
n
d
Rx
NCO
S-Tx
NCO
X-Tx
NCO
S-Tx Frequency Generat i on
Power
Ampl i fi er
240 F
1
+ R
s
F
d
T
e
le
m
e
tr
y
R
a
n
g
in
g
Phase
Modul at or X-Tx Frequency Generat i on
X2
880 F
1
+ R
x
F
d
DAC DAC
T
e
le
m
e
tr
y
R
a
n
g
i
n
g
DAC
Rangi ng
Vi deo Fi l t er
To S- Tx
Phase Modul at or
To X- Tx
Phase Modul at or
2
/
3

F
1

+

F
d
/
3
4 F
1
2
/
3

F
1

+

R
s
F
d
/
3
2
/
3

F
1

+
R
x
F
d
/
6
2 F
1
2 F
1
4 F
1
4 F
1
Fr equency
Ref er ence
( USO/ I nt er nal TCXO)
4 F
1 2
2 F
1
1 3 F
1
+ F
d
1
4

F
1

+
F
d
F
1
The chosen Hardware/Software partitioning allows a great flexibility in terms of functions, algorithms and design
parameters. As an example, the tracking loops constants can be easily optimized during the receiver tuning phase to
obtain the best performance. The following sections are devoted to Digital Signal Processing functions and
management.
Digital Receiver Algorithms
Signal Model
The command signal at the ADC input can be expressed as:
( ) ( ) ( ) [ ]
c sc sc
t F t D t F C t s + + + 2 sen 2 sen 2
1
(1)
where C is the total transmitted power,
1
F is the carrier frequency (9.5702 MHz),
c
is the carrier phase,
sc
F is the
sub-carrier frequency,
sc
is the sub-carrier phase, is the carrier modulation index and D(t) is the command non-
return-to-zero (NRZ) data.
The digital samples s(k) at the ADC output can be derived from (1) setting
1
4F k t being k an integer value, i.e.:
) (
2
cos 2 ) (
2
sen 2
4
) (
1
k Q k C k I k C
F
k
s k s
c c

,
_

,
_

,
_

(2)
in which:
( ) ( ) ( ) ( ) ( ) ( )
1
]
1

+
sc sc c c c
F
k
F k D J J k I
1
1 0
4
2 sen sen cos (3)
( ) ( ) ( ) ( ) ( ) ( )
1
]
1

+ +
sc sc c c c
F
k
F k D J J k Q
1
1 0
4
2 sen cos sen
(4)
are the in-phase and quadrature residual carrier baseband components, derived using the Anger-Jacobi expansion and
neglecting the higher order terms being filtered out by the decimator stages.
Carrier Demodulation
As suggested by (2), the in-phase ) (k I
c
and quadrature ) (k Q
c
baseband components can be recovered demultiplexing
the sampled signal s(k) into even and odd samples and then multiplying alternatively by +1 and 1.
Carrier Tracking Loop
Equation (4) shows that the carrier loop error term
c
can be obtained from the quadrature samples, after digital mixing
with quadrature reference signal. The carrier quadrature samples are accumulated to reduce the sampling rate, thus
enabling the software implementation of the loop filter. The digital loop filter includes a perfect integrator, making the
carrier recovery loop capable of tracking a frequency offset without steady state phase error.
The filter outputs a frequency error estimate at the loop update rate adjusting the nominal frequency of the NCO that
feeds the Digital-to-Analog Converter (DAC). The DAC output is mixed with the SPLL output frequency allowing the
analog closure of the carrier loop at IF.
The difference between the absolute value of the in-phase and quadrature baseband samples is used to implement the
carrier lock detector.
Sub-Carrier Tracking Loop
In case of perfect carrier tracking 0
c
and ) (k Q
c
becomes proportional to the modulated sub-carrier. Hence, the
sub-carrier tracking loop input is given by the quadrature baseband component of the residual carrier. The sub-carrier
tracking loop is implemented as a second-order order Costas loop with hard-limited in-phase channel and squarewave
reference. This solution has been analyzed in detail in [3]. During the sub-carrier acquisition phase, the Costas loop
detector is configured as a frequency detector thus speeding the frequency acquisition process. Once the sub-carrier
frequency has been acquired, the Costas loop detector is configured as a phase detector in order to perform sub-carrier
tracking. The in-phase signal of the sub-carrier is proportional to the modulating NRZ sequence.
The difference between the absolute value of the in-phase and quadrature sub-carrier samples is used to implement the
sub-carrier lock detector.
Symbol Synchronization
The in-phase signal of the sub-carrier is applied to the Digital Data Transition Tracking Loop (DTTL) performing
symbol synchronization and matched filtering. The base-band input signal is passed through two parallel channels: the
in-phase channel monitors the polarity of the actual transitions and the quadrature channel measures the timing error
accumulating over the estimated symbol transition. The quadrature channel output is delayed by one-half symbol period
and then multiplied by the in-phase channel output. The multiplication results is the loop error signal, that is
proportional to the estimate of the timing error. Subsequently, the loop error signal is filtered by the loop filter with the
resulting output being used to control the timing generator. The DTTL is implemented as a digital first-order loop and it
shows a steady-state error in presence of Doppler or frequency instability. However, at low symbol rates, the DTTL
NCO is clocked by the estimated sub-carrier frequency and only the phase must be recovered.
Transponder Coherence
The DST frequency plan must guarantee the coherent turn-around ratio between the transmitted and the received signal
in order to enable two-way ranging. The DST architecture is based on DDFS that intrinsically does not allow the
coherent turn-around function due to frequency control quantization. To avoid a frequency error due to the NCO control
word quantization, the dithering of the base frequency is performed at carrier loop sampling time. Besides, a dedicated
signal processing is implemented to compensate the deviation of the down-link signal phase from its desired value.
Digital Automatic Gain Control
Digital AGC algorithms are used for digital receiver calibration. The digitized samples are collected from the Rx ASIC
by the Microprocessor and the loop filter is software implemented. During the signal detection and carrier acquisition
phases a non-coherent AGC is performed, using both the in-phase (3) and quadrature (4) baseband components of the
residual carrier. During carrier tracking, a coherent AGC based on the in-phase baseband component of the residual
carrier is implemented.
Turn-Around Ranging
The tone demodulation with base-band conversion is implemented inside the digital section; after mixing with the
1
F
frequency, the samples are processed by an integrate-and-dump filter (I/D) which accumulates the base-band samples
and dumps at an output rate equal to 2
1
F . After digital-to-analog conversion, the samples are routed to ranging video
circuit composed by: high pass filter for DC offset rejection, active low pass filter for rejection of non desired spectral
component (spectrum replica and alias), resistive divider to route the signal both at S-band and X-band down-link
modulator. To simplify the hardware design, the video AGC (usually applied in the video channel) has been removed.
However, at low signal-to-noise ratio, the same performance have been obtained by properly tuning the overall ranging
channel, including the down-link modulation index. In Fig.3 the performance of Rosetta ranging channel (RF AGC
only) in terms of down-link ranging side-bands power over overall down-link signal power
tot r
P P is compared versus
the classical video AGC approach. The transponder digital architecture allows the application of on-board regenerative
ranging. This approach becomes important in case of low signal to noise ratio typical of deep space application. Indeed
the traditional ranging channel routes to the down-link modulator all the up-link noise power reducing the useful side-
band ranging components and affecting the ground station performances.
Digital Receiver Management
The Microprocessor manages the digital signal processing operations according to the State Diagram sketched in Fig.4.
The following operative scenarios are foreseen:
Low input power level: -146 dBm C <-126 dBm (carrier sweep rate for on-board acquisition = 20 Hz/s)
High input power level : C -126 dBm (carrier sweep rate for on-board acquisition < 500 Hz/s)
as consequence the receiver configures itself respectively in Narrow-Band or Wide-Band, in order to optimize the
carrier acquisition and tracking performance. An overview of the receiver software states is provided in the following.
S1: Signal Detection
The signal detection is based on two center frequency detectors (one for the Narrow-Band and one for the Wide-Band),
together with a non-coherent AGC. This architectural solution allows to close the carrier loop bandwidth only when the
carrier is inside the loop pull-in (i.e. the carrier is inside the center frequency detector bandwidth). This approach
reduces the probability of false alarm and gives the opportunity to automatically discriminate between the two operative
conditions: low level signal or high level signal. When one of the two center frequency flag is active the relevant Carrier
Acquisition state is entered.
S2N/S2W: Carrier Acquisition Narrow/Wide
In this state the carrier tracking loop and the lock detection algorithms are performed, along with a coherent AGC.
A maximum time is allowed to obtain the carrier lock condition; if this time elapses without carrier lock, the Signal
Detection state is reinitialised and the signal detection is started again. After locking the carrier, the processing
continues with the Sub-carrier Acquisition Narrow/Wide state.
S3N/S3W: Sub-carrier Acquisition Narrow/Wide
The sub-carrier tracking loop and lock detection algorithms are performed during this state, together with the carrier
tracking loop and the carrier lock condition verification. When the sub-carrier is locked, the processing continues with
the Signal Tracking Narrow/Wide state, while if the carrier lock is lost the Carrier Acquisition Narrow/Wide state is
entered.
S4N/S4W: Signal Tracking Narrow/Wide
During this state, the carrier and sub-carrier tracking loops and the lock condition verification algorithms are executed;
a squelch algorithm is executed to verify the quality of the received signal.
Narrow-Band to Wide-Band and Wide-Band to Narrow-Band Transitions
Transition between the Narrow-Band to Wide-Band configuration and vice-versa are allowed to cope with variation of
signal power and dynamic during the carrier tracking phase. If the carrier lock is lost, the Carrier Acquisition
Narrow/Wide state is entered; otherwise, if the sub-carrier lock is lost, but the carrier is still locked, the Sub-carrier
Acquisition Narrow/Wide state is entered.
TECHNOLOGY
ASIC and FPGA
The design of the Rx ASIC model shall be adequate both for FPGA (Field Programmable Gate Array) and ASIC
implementation. The FPGA is aimed to support the development of the transponder breadboard when the signal
processing algorithms are tested and tuned.
Fig. 3 Rosetta ranging channel performance Fig. 4 Digital receiver: software states
Up-Link Modulation Index: 0.8 rad-pk --- Down-Link Modulation Index: 0.6 rad-pk
-60
-50
-40
-30
-20
-10
0
23 33 43 53 63 73 83 93
C/N0 (dBHz)
AGC VIDEO
AGC RF
P
r
/
P
t
o
t
(
d
B
)
S1
S2N
S3N
S4N
S2W
S3W
S4W
E1-2
E2-1
E2-3
E3-4
E4-3
E1-2
E2-1
E
2
-3
E3-4
E4-3
E3-1
E4-1
E3-1
E4-1
E
3
N
-
3
W
E
4
N
-
4
W
E
3
W
-
E
3
N
E
4
W
-
4
N
The FPGA was chosen from the ALTERA FLEX10K devices, which are S/W or EPROM configurable.
Clock Scheme
To obtain the best out of FPGA and ASIC, the project relays on a Clock and Clock Enable scheme: in general a global
clock drives a domain of registers, but the registers are active only when the clock enable is true. This type of
architecture in fact requires a multiplexer in front of each flip flop, and this may seem gate consuming and power
inefficient: however this is not the case, since the current FPGA technology relays on the elementary cells made of
registers with clock enable, multiplexer and combinatory logic. Furthermore, FPGA uses a number of dedicated clock
nets that run throughout the device with optimised skew. From the ASIC standpoint, the same architecture requires the
generation of the Clock Tree, which is the state-of-the-art of the Silicon Manufacturers community; the gate overhead
due to the multiplexers did not require a larger die, and power consumption was not affected, since multiplexers switch
at very low rates with respect to the clock frequency. The Clock and Clock Enable scheme leaves a clear and
straightforward data path which is very easy to handle when using EDA synthesis and analysis tools. A power saving
strategy was implemented on the Rx ASIC by allowing a number of functions to be turned ON and OFF, according to
the current computing needs. The ON/OFF function inhibits the relevant gates from toggling, without physically
disconnect them from the supply rails.
Metastability
The Rx ASIC requires a number of independent clocks: the two most critical are the CPU clock which drives the
Microprocessor and the
1
4F clock that goes with the IF data samples. The clocks are totally independent. Each clock
drives its own registers domain, but since data exchange is required from a domain to another, suitable synchronising
circuits are provided to prevent large register areas from going into metastable states. The synchronising circuits
provide adequate interface so that only one flip flop goes into metastability in an interval of two clock periods.
Design Flow
The Rx ASIC was modelled with a VHDL-RTL code. The VHDL-RTL code was simulated and validated to the
requirements with a VHDL Test Bench, which is a description of both the input stimuli that drive the model, and how to
catch the outputs of the model for further analysis. Afterwards the VHDL-RTL was synthesized for the FPGA housed
in the Rosetta Transponder breadboard. The synthesized model was then simulated and compared to the VHDL-RTL
simulation results, to check for critical timings, and logic synthesis outputs. The above steps produce an accurate
VHDL-RTL model description and Test Bench that will also be good for the ASIC development. The whole model or
part of it can be evaluated in advance for synthesis in terms of gate complexity and speed, so that the required
performance can be met.
Power Consumption
The power consumption of the designed device is difficult to estimate since it largely depends on the number of
switching gates, functions settings, bit rates and cut off frequencies of the filters. The worst case estimation is 1.2 W,
fully operating, at the maximum frequencies. The power consumption can be reduced performing the coherent sampling
process at 3 4
1
F instead of
1
4F , thus exploiting the sub-sampling technique.
REFERENCES
[1] M.C. Comparini, G.Boscagli, L.Simone, Deep Space Digital Transponder for Rosetta and Mars Express
Mission 2nd ESA Workshop on Tracking Telemetry and Command Systems for Space Applications, 29-31
October 2001
[2] L.Iess, G.Boscagli , Advanced Radio Science Instrumentation for the Mission BepiColombo to Mercury" 2nd
ESA Workshop on Tracking Telemetry and Command Systems for Space Applications, 29-31 October 2001
[3] L.Simone, S. Cocchi, M. DAttilia, M.C. Comparini, D. Gelfusa, G.C. Cardarilli, M. Re, A. Del Re, Analysis
and Design of Digital Costas Loop Based on CORDIC Algorithm 2nd ESA Workshop on Tracking Telemetry
and Command Systems for Space Applications, 29-31 October 2001