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Semiconductor Memories
8–1
IC design 8.1. GENERAL CONCEPTS
VDD
GND
C1 C2 C3 C4
0 1 0 1
R1
GND
R2
1 0 0 0
1 1
R3
GND
R4
0 0 0
In the layout the bit lines (columns) are implemented in metal 1 and
the word lines (rows) connecting the gates of the nMOS “memory”
transistors are implemented in polysilicon. The sources of the nMOS
transistors are connected to GND through the n diffusion. To save
silicon area two adjacent rows share the GND diffusion connection.
For every row address only one word line is activated by applying a
low signal to the gates of nMOS transistors in a row. When no word
line is activated, all nMOS transistors are on and the line signals, Ci
are all low.
When a word line is activated all transistors in the row are switched off
and the respective Ci signals are high. If a transistor in the selected row
is short-circuited, then the respective Ci signal is low.
In other words, the logic ‘0’ is stored when a transistor is replaced with
a wire, whereas the logic ‘1’ is stored by an nMOS transistor being
present.
VDD
GND
C1 C2 C3 C4
1 1 0 1
R1
0 1 1 0
R2
1 0 1 1
R3
GND
In the layout, similarly to the NOR ROM, the bit lines (columns) are
implemented in metal 1 and the word lines (rows) connecting the gates
of the nMOS “memory” transistors are implemented in polysilicon.
The drawback of the NAND ROM however is that they are usually
slower comparing with the corresponding NOR ROM, because of a
significant number of serially connected nMOS transistors between the
bit line and the ground.
GND
VDD
S0
S1
S2
S3
S4
S5
S6
S7
GND GND GND GND
a2 a2 a1 a1 a0 a0
The cells of the CMOS SRAM are based on a simple latch circuit as
shown in Figure 8.8.
Bit line C
Bit line C
Word line S
The two-inverter latch is able to store one bit data. In order to access
the cell the word line is activated with high-level signal S, which closes
access switches on both sides of the cell.
The state of the cell (and its complement) is now available on two
complemented bit lines and the read operation can be performed.
Bit line C
GND
Word line S
The cell consists of six transistors: four nMOS a two pMOS. Two pairs
of transistors form a pair of inverters and two nMOS transistors form
the access switches.
The stick diagram of a possible layout of a CMOS SRAM cell is
shown in Figure 8.10.
VDD
bit line C
bit line C
word
line S
GND
VDD VDD
p3 p4
VDD
Bit line C
Bit line C
p1 p2
Q
n3 n4
Cc Cc
n1 n2
GND
Word line S
Figure 8.11: A CMOS static memory cell with column pull-up transistors and parasitic
column capacitances.
When none of the word lines is selected, that is, all S signals are ‘0’,
the pass transistors n3, n4 are turned off and the data is retained in all
memory cells. The column capacitances are charged by the drain
currents of the pull-up pMOS transistors, p3, p4.
The column voltages VC and VC̄ both reach the level just below
VDD − VT p , say 3.5V for VDD = 5V and the threshold voltage
VT p = 1V.
For the read or write operations we select the cell asserting the word
line signal S=‘1’.
For the write operation we apply a low voltage to one of the bit line,
holding the other one high.
Similarly, to write ‘1’ in the cell, the opposite column voltage VC̄ is
forced to low (C̄ = 0) which sets the signal Q = 1.
The difference between the column voltages is small, say 0.5V, and
must be detected by the sense amplifiers from data-read circuitry.
Figure 8.12: The structure of the write circuitry associated with one column of the
memory cells.
VDD
p3 p4
Bit line C
Bit line C
Cc 1-bit cell Cc
Word line S
M1 M2
clk
M3
M5 Data
Current-mirror Out
Read differential
cross-coupled Select sense amplifier
sense amplifier
M4
Figure 8.13: The structure of the write circuitry associated with one column of the
memory cells.
During the read operation the voltage level on one of the bit lines drops
slightly after the pass transistors in the memory cell are turned on.
The read circuitry must properly sense this small voltage difference
and form a proper output bit:
Word Line S
C1
Bit Line D
M1
Despite of the need for additional refreshing circuitry SRAM has two
fundamental features which have determined is enormous popularity:
• The DRAM cell occupies much smaller silicon area than the
SRAM cell. The size of a DRAM cell is in the order of 8F 2 ,
where F is the smallest feature size in a given technology. For
F = 0.2µm the size is 0.32µm2
• No static power is dissipated for storing charge in a capacitance.
BC M12 M13
SC M22 M23
WL2
BC
SC
Note that the bit-line contacts BC are shared between two diagonally
adjacent memory cells.
D -- Data In/Out
Bit Line
S -- Read/Write Select
Word Line
C1
CC
M1
The cell is selected for a read/write operation by asserting its word line
high (S = 1). This connects the storage capacitance to the bit line.
Note that the read operation destroys the charge stored on the storage
capacitance C1 (“destructive readout”). Therefore the data must be
restored (refreshed) each time the read operation is performed.