Course Duration: 16 Weeks Mod.

Module Title

P1 Applied Network (3 Days) Analysis

Course Structure and Outline What You Learn Electrical Network Elements - Independent and Dependent Sources, Passive Elements Network Analysis Techniques - Review Review of Time and Frequency Domain responses of RC networks MOSFET Characteristics, MOSFET Capacitances CMOS Inverter - Conceptualizing the Inverter using Network Elements, Inverter VTC, Transient Response CMOS Gate Design PN Junction, BJT Device Characteristics and Applications Review OPAMP Applications - Review Quality Metrics of a Digital System Review of Number Systems , Combinational Logic Design Interpreting the Logic gate Data Sheets Designing with Mux, Demux, Decoders, Encoders Sequential Elements and Sequential Logic Design- D Latch, D Flop Design of Sequential Systems - Registers and Counters Introduction to C Programming - Structure of a C program, The C compilation process Types and Operators - C base types, Precedence & associativity, - Arithmetic operations Functions -The Function as a logical program unit, Parameter passing, Memory segments Control Flow -Logical expressions and operations, Decision Making, Loops, Introduction to Pointers Introduction to a Generic Microprocessor Instruction Execution Cycles, Single, Multi Cycle, Pipelined Data Paths Interrupts, Memory Mapping and Peripheral Interfaces Introduction to Bus Architecture overview - APB, AXI Synchronous Finite State Machine Design

P2 Devices and Circuits (4 Days) for Microelectronics

P3 Digital System (4 Days) Design

P4 Basic C (3 Days) Programming

Review of Micro P5 Processors/ (3 Days) Microcontrollers C1 Advanced Digital

Data-path elements - Arithmetic Structures Introduction to and Programmable Platforms Design Capture and Simulation Practical Digital System Design Examples Driver for VLSI: Moore's law Evolution of Design Approaches (leading upto HDLs), Simulator and Synthesizers Specification formation to Micro - architecture Hardware Modeling Overview, Verilog language concepts Modules and Ports Dataflow Modeling Introduction to Test benches Operators Procedural Statements Controlled Operation Statements Coding for Finite State Machines Coding For Synthesis Tasks and Functions Advanced Verilog Test benches Introduction to Verification Introduction to Verification Plan Verification Tools Stimulus and Response Introduction to Bus Function Models Verification environment and its components Advanced Simulation and Synthesis Introduction to Design Verification RTL design,

(5Days) System Design

C2 Chip Design (2 Days) Methodology - I

C3 Digital System (8Days) Design with Verilog

C4 Functional (5 Days) Verification

C5 Chip Design (3Days) Methodology - II

synthesis, verification, regression System Verilog Basics - Introduction to System Verilog, Enhancement Made in System Verilog over Verilog, Interface and Modports System Verilog for Verification - System Verilog Event Ordering,

Clocking block and Program bloc,OOP's Concept of System Verilog - Parameterized classe, Virtual interface, Constrained Randomization techniques, Functional Coverage (Coverage Driven Verification) System Verilog Assertions - Introduction to Assertion, Properties, Sequences, Checkers, Assertions in design, Verification (for Coverage Analysis) FPGA Architecture - Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB), FPGA Architecture Optimal FPGA Design - HDL Coding Techniques for FPG, FPGA Design Techniques Synthesis Techniques, Implementation, Options - Overview, Achieving Timing Closure, Path Specific Constraints, Introduction to Advanced IO Timing C7 Digital System FPGA Design Flow - Xilinx tool Flow, Reading (8 Days) Design using FPGAs Reports, Implementing IP cores, Pin Planning using Plan Ahead, Global Timing Constraints, Debugging Using Chipscope Pro

C6 Verification using (15 System Verilog Days)

Static Timing Analysis - Introduction Reset Techniques, Clock Domain Crossing, Multiple Clock Domains, Dual Synchronization Design and Verification Guidelines SoC Verification Methodology Physical Design, Manufacturing, Silicon validation

C8 Chip Design (2 Days) Methodology - III C7 (15 Course Project Days)

Course project