HCF4052B

DIFFERENT 4-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER

s

s s

s s s

s s

LOW ON RESISTANCE : 125 (Typ.) OVER 15V p.p SIGNAL-INPUT RANGE FOR VDD - VEE = 15V HIGH OFF RESISTANCE : CHANNEL LEAKAGE 100pA (Typ.) at VDD - VEE = 18V BINARY ADDRESS DECODING ON CHIP HIGH DEGREE OF LINEARITY : < 0.5% DISTORTION TYP. at fIS = 1KHz, VIS = 5 Vpp, VDD - VSS > 10V, RL = 10K VERY LOW QUIESCENT POWER DISSIPATION UNDER ALL DIGITAL CONTROL INPUT AND SUPPLY CONDITIONS : 0.2 W (Typ.) at VDD - VSS = VDD - VEE =10V MATCHED SWITCH CHARACTERISTICS : RON = 5 (Typ.) FOR VDD - VEE = 15V WIDE RANGE OF DIGITAL AND ANALOG SIGNAL LEVELS : DIGITAL 3 to 20, ANALOG TO 20V p.p. QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES

DIP

SOP

ORDER CODES
PACKAGE DIP SOP TUBE HCF4052BEY HCF4052BM1 T&R HCF4052M013TR

DESCRIPTION The HCF4052B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor PIN CONNECTION

technology available in DIP and SOP packages. The HCF4052B analog multiplexer/demultiplexer is a digitally controlled analog switch having low ON impedance and very low OFF leakage current. This multiplexer circuit dissipate extremely low quiescent power over the full VDD - VSS and VDD VEE supply voltage range, independent of the logic state of the control signals. When a logic 1 is present at the inhibit input terminal all channel are off. This device is a differential 4-channel multiplexer having two binary control inputs, A and B and an inhibit input. The two binary input signals selects 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs.

September 2001

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HCF4052B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 10, 9 6 12, 14, 15, 11 1, 5, 2, 4 3 13 7 8 16 SYMBOL A, B INH 0X to 3X CHANNEL IN/OUT 0Y to 3Y CHANNEL IN/OUT COM Y OUT/ IN NAME AND FUNCTION Binary Control Inputs Inhibit Inputs X channels Input/Output

Y channels Input/Output Y Common Output/Input

COM X OUT/ X Common Output/Input IN VEE VSS VDD Supply Voltage Negative Supply Voltage Positive Supply Voltage

TRUTH TABLE
INHIBIT 0 0 0 0 1
X : Dont Care

B 0 0 1 1 X

A 0 1 0 1 X 0x, 0y 1x, 1y 2x, 2y 3x, 3y NONE

FUNCTIONAL DIAGRAM

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ABSOLUTE MAXIMUM RATINGS
Symbol V DD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

Symbol V DD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C

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HCF4052B
DC SPECIFICATIONS
Test Condition Symbol Parameter VIS (V) VEE (V) VSS (V) VDD (V) 5 10 15 20 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 470 180 125 10 10 5 0.1 Max. 5 10 20 100 1050 400 280 Value -40 to 85C -55 to 125C Min. Max. 150 300 600 3000 1200 520 360 Min. Max. 150 300 600 3000 1200 520 360 Unit

IL

Quiescent Device Current (all switches ON or all switches OFF)

SWITCH R ON Resistance

0 < VI < VDD 0 < VI < VDD

ON

Resistance RON (between any 2 of 4 switches) Channel Leakage Current (All Channel OFF) (COMMON O/I) Channel Leakage Current (Any Channel OFF) Input Capacitance Output Capacitance Feed through

0 0

0 0

100 1000 1000 nA

OFF*

OFF*

18

0.1

100

1000

1000

nA

CI CO C IO

5 -5 -5 5 18 0.2 VEE = VSS RL = 1K to VSS IIS < 2A (on all OFF channels) 5 10 15 5 10 15 18 1.5 3 4 3.5 7 11 10 -3 5 0.1 7.5 3.5 7 11 1 1.5 3 4 3.5 7 11 1 1.5 3 4 pF

CONTROL (Address or Inhi bit) V IL Input Low Voltage = VDD thru 1K

VIH

Input High Voltage

V A pF

IIH, IIL CI

Input Leakage Current Input Capacitance

V I = 0/18V

* Determined by minimum feasible leakage measurement for automating testing.

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HCF4052B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, all input square wave rise and fall time = 20 ns )
Test Condition Parameter Propagation Delay Time (signal input to output) Frequency Response Channel ON (sine wave input) at 20 log VO /VI = - 3dB Feed through (all channels OFF) at 20 log VO /VI = - 40dB VEE (V) RL (K) 200 fI (KHz) VI (V) VDD VSS (V) VDD (V) 5 10 15 V O at Common OUT/IN V O at any channel V O at Common OUT/IN V O at any channel Between Sections (measured on common) Between Sections (measured on any channel) Value Min. Typ. Max. 30 15 11 25 MHz 60 10 MHz 8 60 30 20 Unit

ns

= VSS

5(*)

10

= VSS

5(*)

10

6 MHz 10 0.3 0.2 0.12 360 160 120 225 360 160 120 200 200 90 70 130 720 320 240 450 720 320 240 400 450 210 160 300

Frequency Signal Crosstalk at 20 log VO /VI = -40dB

= VSS

5(*)

10

Sine Wave Distortion = VSS fIS = 1KHz Sine Wave

10

2(*) 3(*) 5(*) 0 0 0 0 0 0 0 0

5 10 15 5 10 15 5 5 10 15 5 5 10 15 5 10 VC = VDD-VSS (square wave)

CONTROL (Address or Inhi bit) Propagation Delay: 0 Address to Signal 0 OUT (Channels ON 0 or OFF) -5 Propagation Delay: 0 Inhibit to Signal OUT 0 1 (Channel turning ON) 0 -10 Propagation Delay: 0 Inhibit to Signal OUT 0 10 (Channel turning 0 OFF) -10 Address or Inhibit to Signal Crosstalk 0 10 (1)

ns

ns

ns

65

mV peak

(1 ) Both ends of channel. * Peak to Peak voltage symmetrical about (VDD - VEE ) /2

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HCF4052B
TYPICAL BIAS VOLTAGES

The ADDRESS (digtal-control inputs) and INHIBIT logic levels are : 0=VSS and 1=V DD. The analog signal (through the TG) may swing from VEE to VDD

TYPICAL APPLICATIONS (TYPICAL TIME-DIVISION APPLICATION)

SPECIAL CONSIDERATIONS Control of analog signals up to 20V peak to peak can be achieved by digital signal amplitudes of 4.5 to 20V (if VDD - VSS = 3V, a VDD - VEE of up to 13V can be controlled; for VDD - VEE level differences above 13V, a VDD - VSS of at least 4.5V is required. For example, if VDD = +5, VSS = 0, and VEE = -13.5, analog signals from -13.5V to 4.5V can be controlled by digital inputs of 0 to 4.5V. In certain applications, the external load resistor

current may include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0,8V (calculated from RON values shown in DC SPECIFICATIONS). No VDD current will flow through RL if the switch current flows into leads 3 and 13.

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HCF4052B
TEST CIRCUIT

C L = 50pF or equivalent (includes jig and probe capacitance) R L = 200K R T = ZOUT of pulse generator (typically 50)

WAVEFORM 1 : CHANNEL BEING TURNED ON (RL = 1K, f=1MHz; 50% duty cycle)

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HCF4052B
WAVEFORM 2 : CHANNEL BEING TURNED OFF (RL = 1K, f=1MHz; 50% duty cycle)

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HCF4052B

Plastic DIP-16 (0.25) MECHANICAL DATA

mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch

P001C
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HCF4052B

SO-16 MECHANICAL DATA

DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010

PO13H
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HCF4052B

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