ORDER NO.

MTNC010309G1 B1 & B5

Technical Guide
NA7D/A CHASSIS
COLOR TELEVISION SYSTEM

Please file and use this TECHNICAL GUIDE for the NA7D/A CHASSIS together with the Main Service Manuals and other publications related to models based on the NA7D/A chassis.

Copyright 2001 by Matsushita Electric Corporation of America. All rights reserved. Unauthorized copying and distribution is a violation of law.

Notes

The purpose of this Technical Guide is to present an overall view of the circuits used in the NA7D/A Chassis. The guide can assist the service technician in troubleshooting a receiver. By using general block diagrams, the guide provides the technician with an overall view of the entire system. The block diagrams include a general description of circuits. The purpose of the descriptions is to help the technician understand how particular circuits operate. By using block diagrams and circuit descriptions, the Technical Guide will help the technician develop knowledge about this Chassis.

Table of Contents
Description of Boards ....................................... 4

New Technology
MPU ..................................................................... 6 Analog Front-end Block ................................... 9 Y/C Separation ................................................ 9 ACC............................................................... 10 Luminance Processor.................................... 11 Blackstretch Circuits ...................................... 11 Sharpness Control......................................... 12 Chroma Processor Block............................... 12 Killer .............................................................. 12 Color.............................................................. 12 Cb/Cr to R-Y/B-Y Conversion........................ 12 RGB Matrix Block .......................................... 13 ACL ............................................................... 13 Gamma () Correction ................................... 13 Mute .............................................................. 13 OSD Function................................................ 13 Analog Back-end Block ................................. 14 Deflection Block............................................. 14 Sync Separation ............................................ 14 H SYNC SEPA (auto slicer) .......................... 14 V SYNC SEPA .............................................. 14 AFC1 ............................................................. 14 AFC2 ............................................................. 15 V Counter ...................................................... 15

Mono or L+R Signal ...................................... 24 LR Signal .................................................... 24 Secondary Audio Program (SAP) mode ....... 24 dbx Effect.................................................... 24 Matrix Circuit ................................................. 24 AGC Audio Control Surround ......................... 26 IC2501 Audio Controller................................ 26 AGC .............................................................. 26 AI Sound ....................................................... 26 Audio Multiplex System................................... 27 Abstract......................................................... 27 The North American System......................... 27 Audio Amplifiers ............................................ 28

Deflection
Deflection Circuit ............................................ 30 Vertical Output Circuit .................................. 30 Sawtooth Wave Generating Circuit .............. 30 Drive Circuit ................................................. 30 Vertical Output Pulse Amplifying Circuit ...... 31 Vertical Output Circuit Operation ................. 31 Pulse Amplifier Circuit (Pump Up) Operation ............................... 31 Horizontal Output Circuit............................... 32 Horizontal Output .......................................... 32 Horizontal Drive Circuit ................................. 33

Power Supply
Power Supply Overview (US Models) ...................................................... 36 Power Supply Overview (CT-G3349L)...................................................... 37 Protection Circuits ........................................... 38 Over Current Protection ................................ 38 Spot Killer...................................................... 38 Neck Protector .............................................. 38

Functional Block Diagrams

Audio Signal Path............................................. 18 Video & Sync Signal Path ................................ 19 I2C Bus Line System ........................................ 20 MPU Control...................................................... 21

Audio
MTS Sound Detection and Separation .......... 24 Composite Signal .......................................... 24

Description of Boards Used on the NA7 Chassis

Table 1 lists the various boards and their functions which may be used on any of the receivers based on the NA7 Chassis.

A-PANEL (TNP2AH031 & TNP2AH024)

AUDIO/VIDEO AND S-VHS INPUT TERMINALS VIDEO SWITCHING MTS PROCESSING HALFTONE SWITCHING POWER SUPPLIES MICRO PROCESSOR CONTROLS AUDIO AMPLIFICATION VERTICAL AND HORIZONTAL DEFLECTION CONTROLS PROTECTION CIRCUITRY

B-PANEL (TNP2AA079)
SURROUND SOUND CONTROL BASS/TREBLE/BALANCE CONTROL

C-PANEL (TNP2AA075 & TNP2AA086)

RGB DRIVES

J-PANEL (TNP2AA093)
HALF TONE SWITCHING

P-PANEL (TNP2AA014)
DC - DC CONVERTOR POWER SUPPLY

Z-PANEL (TNP2AA010)
PINCUSHION CORRECTION

TABLE 1: PANEL DESCRIPTIONS

NEW TECHNOLOGY
COLOR TELEVISION SYSTEM

NA7D/A CHASSIS

M65580MAP100 (MPU/VCJ)
The MPU/VCJ employed in the NA7D/A chassis incorporates processes that on other chassis are performed by other ICs. These functions include synchronization, TV, EXT, Y/C switching, Video Chroma Jungle (VCJ) and filtering. Fig. 2 & Fig. 3 display the block diagram for the IC as a whole and in detail respectively.

Figure 1: MPU/VCJ Pinout

Figure 2: MPU/VCJ Block Diagram 7

Figure 3: MPU/VCJ Block Diagram (for Signal Processing)

Analog Front End Block (Fig. 4)

The MPU, via the Bus data, selects the appropriate input from the TV_In, EXT_In or Y/C_In. CVBS or Y signal is amplified to twice the input signal and output from pin 18 to pin 17 for Sync Separation block and to pin 77 for CC DEC. When Standard Analog Composite (CVBS) signal is selected for input, it is input to the first 8bit ADC. When Y/C signal is selected for input, the Y portion is input to the first 8bit ADC and the Chroma is input I2 C to the second 8bit ADC. The signals are then converted to digital signals. The reference voltage can be either 1.7V (1.2Vp-p), 1.8V (1.3Vp-p) or 1.9V (1.4Vp-p), selected by the MPU, via the I2C BUS data. The timing of the ADC and Logic CLK can be changed by the MPU, via the I2C Bus data.

Figure 4: Analog Front End Block

Y/C Separation (Fig. 5)

A two-dimensional YC separation is performed using 1 line memory and an algorithm. Input CVBS signal is fed in to a filter (H-BPF) in the horizontal direction and the filter (HV-BPF) in the horizontal-vertical direction for detecting in which direction (H or V) the input signal correlates. When there is no correlation in the vertical direction the filter is changed from HVBPF to H-BPF. The sensitivity of the correlation detection can be adjusted by the MPU, via the I2C BUS. Regardless of correlation detection H-BPF or HV-BPF can be selected by the MPU, via the I2C BUS. This circuit is effective only when input CVBS is larger than a determined level. If the level is small, the Luminance signal is filtered by Trap around FSC frequency and the Chrominance is filtered by Y/C separator. In case of Y/C input, the circuit will bypass the process by the MPU, via the I2C BUS. Y&C signals are passed to the Y processing block and the C processing block respectively.

Figure 5: Y/C Separation 9

ACC (Fig. 6a & Fig. 6b)

This IC contains digital ACC to boost input. If burst level is smaller than the level of MPU, via the I2C BUS, three analog ACC amps, each of 10dB operate in order. The on/off status is also controlled by the MPU, via the I2C BUS, as follows: 0 = amp off: 0dB 1 = ampx1 on: 10.5dB 2 = ampx2 on: 21dB 3 = ampx3 on: 31.5dB When the third analog ACC amp is on, digital ACC circuit can be set to off by the MPU, via the I2C BUS. It can also be forced to be in the off state by the MPU, via the I2C BUS.

Figure 6a: ACC Processing

Figure 6b: ACC Processing

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Luminance Processor (Fig. 7)

In this process, the Y/C delay timing, blackstretch, YNR, sharpness of input luminance signal is controlled by the MPU, via the I2C data, the following way: YC Separation Normal Weak Signal 2 Line Comb Filter Y: Trap Filter (Digital) C: Band Pass Filter (BPF, Digital) Input Block Amp is ON Small Burst Signal (Chroma) Y/C delay adjustment: luminance signal can be delayed to adjust to chroma signal delay time by MPU, via the I2C BUS data. The YNR function subtract noise at around fsc frequency from luminance signal.

Figure 7: Y/C Separation

Blackstretch Circuits
The IC has detection for input Y signal in dot, field and time dimension. Fig. 8 details the process.

Figure 8: Blackstretch Circuits One of the status can be selected for white area of Y the I2C Bus, or IM (Intelligent Monitor) terminals input signal. Each status is determined by the upper (pin 11). Fig. 9 displays the process of the black system, and it can also be checked by the MPU, via stretch.

11

Figure 9: Blackstretch Process

Sharpness Control
Preshoot and overshoot signals are added to the input luminance signal to emphasis on the outline of the picture. The width and gain of the preshoot and overshoot can be controlled by the MPU, via the I2C BUS, as well as the upper limit of the sharpness level.

Chroma Processor Block (Fig. 10)

Input chroma is converted to R-Y & B-Y signals by offset canceller, demodulator ACC, Color, Tint and Killer circuits. When color signal is present, input chroma is demodulated by 4fsc CLK to input burst signal and calculation of its components. Tint is controlled by the MPU, via the I2C BUS data.

Figure 10: Chroma processing

Killer
When the burst level is smaller than Killer level set by the MPU, via the I2C BUS, in succession of two fields, it is switched to Killer-on (Chroma output OFF). It can also be forced to switch by the MPU, via the I2C BUS. The switching between on and off is done on a condition of hysteresis and interval. Killer detection is also done by noise detection and V coincidence.

Color
Color level is controlled by the MPU via the I2 C BUS.

Cb/Cr to R-Y/B-Y Conversion

Following is the conversion formula in which the normalized Cb/Cr signals are converted to R-Y/B-Y: R-Y=1.14 x Cr B-Y=2.03 x Cb

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RGB Matrix Block (Fig. 11)

The Y, R-Y & B-Y signals that are input to the IC are processed by the RGB matrix to generate the R, G & B signals by the following formula: R = 1 x Y + 0 x (B-Y) + r x (R-Y) G = 1 x Y - (13/16) x (B-Y) - (7/16) x (R-Y) B = 1 x Y + 1 x (B-Y) + 0 x (R-Y) where r = 12/8, 13/8, 14/8 If the result is negative, the output is clipped to 000h. Level can be fixed to 0 (LSB) by Mute of MPU, via the I2C BUS.

Figure 11: RGB Matrix

ACL
The R/G/B signals are multiplied with ACL data and Contrast data (6 & 7 bit respectively). The signals are clipped when they exceed a maximum level, then data is divided by a constant. Contrast and ACL data are set to fixed levels in standard case. Data below a certain level is fixed to a predetermined level for only OSD signal when F.B. signal = 1.

Gamma () Correction
Gamma points (16 kinds) and on/off/inverse/noinverse mode of R/G/B signals are controlled by the MPU, via the I2C BUS. See Fig. 12.

Note:

Gamma on/off can be controlled by MPU via the I2C. Gamma Point (circle) can be adjusted by 64LSB steps from 64LSB to 960LSB by MPU via the I2C It has inverse mode (Line-B) and non inverse mode (Line-A).

Figure 12: Gamma () Correction

Mute
On/off of R/G/B is controlled by the MPU, via the I2C BUS data.

OSD Function
Input picture data R/G/B are overlaid by RGB OSD (through Q050 ~ Q052) F.B. and half tone signals from the MCU block through IC050. OSD overlay and halftone (transparent) are two kinds of display modes in OSD function.

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Analog Back-end Block

9 bit Cut-off DACs and 7 bit Drive DACs control the 3 channels 10 bit high speed video DACs for main R/G/B signals. R/G/B output are also controlled for Spot killer. See Fig. 13.

Figure 13: Analog Back-end Block

Deflection Block
The signal for synchronization of the input video is generated in this area as well as the horizontal and vertical synchronization. It contains two phase locked loops, AFC1 & AFC2. AFC1 generates the horizontal and vertical timing pulse. Phase and frequency are synchronized by the input sync. The H SYNC generated at AFC1 is the reference timing for all data related to display. AFC2 is used to adjust the phase of the horizontal drive pulse and compensation for the delay of the horizontal output stage such as FBT.

Sync Separation:
The Sync Separation is composed of H SYNC SEPA which extracts COMPOSITE SYNC from input CVBS signal and V SYNC SEPA which extracts V SYNC from COMPOSITE SYNC.

H SYNC SEPA (auto slicer)

The input CVBS signal is clamped to pedestal level by BGP (burst gate pulse) generated at DEF LOGIC block. The center voltage of the pedestal voltage During the period H of COMPOSITE SYNC (negative polarity), the capacitor is charged, and in the period L, it is discharged with the determined current in the IC. The wave like triangle is generated AFC1 is composed of freerun frequency adjustment and fH pulse. Free running frequency of HVCO is adjusted to around 15.73KHz by VCO control circuit of which standard frequency is 4fsc (=14.32MHz). The free running frequency can be changed by MPU, via the I2C BUS. fH pulse generated by and the sync tip voltage is generated. COMPOSITE SYNC can be separated by comparing the center voltage with the input CVBS. in the horizontal period. V SYNC can be separated by comparing the triangle waveform with the determined voltage. Only the pulse over the determined time is identified as V PULSE. division of the HVCO, is compared in phase with the input H SYNC to synchronize. BGP for SYNC SEPA, HD pulse for signal processing, timing pulses for AFC2 are generated in this stage. The gain of AFC1 can be changed by the MPU, via the I2C BUS data, and the state of COINCIDENCE. See Fig. 14.

V SYNC SEPA

AFC1

Figure 14: AUTO ADJ & AFC1 14

AFC2
Two timing pulses for H-RAMP (corresponding to the rising and falling edges of HOUT) generated in AFC1 stage are applied to the delay circuit controlled by the voltage. H-pulse (HOUT) is generated by this circuit. HOUT is fed back to this stage as a reference pulse (FBP) through the horizontal drive circuits (H drive Tr, FBT, etc.). The phase of HOUT can be adjusted by comparing FBP with the output of divider in AFC1 and control the threshold voltage of delay circuit. The phase of FBP is adjusted to be in the blanking period of the input CVBS signal.

Coincidence In the period of SYNC SEPA and for FBP is H, a capacitor is charged by the current. During L the capacitor is discharged. The voltage at the capacitor is check. During LOCK, the output of the detector is H. During UNLOCK the output of the detector is L. The detector has a fast and slow modes. The slow mode is output by the MPU, via the I2C BUS, and the killer circuit is set to on. Fast mode is used for skew distortion of VTR at the upper side of the TV screen. Loop gain is controlled by AFC1 by the skew and unlock detection. If AFC is in LOCK and phase is not within acceptable range then the skew at the upper side of the screen is compensated by selecting a higher AFC1 gain.

V COUNTER In the vertical period, the counter by 2fH CLK rate is used. The circuit extracts only pure vertical timing pulse from V SYNC SEPA signal is generated in V SYNC SEPA stage. When abnormal vertical pulses are encountered they are ignored. The counter is reset by the input vertical signal and output the reference pulse to Vramp circuit. In that process the counter is operated by 2fH clock and when the number of counter is over a predetermined limit, the next V pulse is not ignored. When V SYNC SEPA output is missing, V pulse is regenerated by the determined timing (window function). V counter is reset by itself when no V SYNC SEPA signal is received and stop receiving the signal for a determined period. This circuit also has a function of V shift to adjust vertical position of screen and V COINCIDENCE to detect if V counter is locked or unlocked.

X-ray and Neck Protector The X-ray protector can be set to non-active state by the MPU, via the I2C BUS. When the voltage at pin 36 is higher than the first threshold voltage (VthHD), the frequency of Hout is fixed to about 16.5KHz. When it is higher than the second threshold voltage (VthSD), Hout is stopped (no signal). The threshold voltages can be selected by the MPU, via the I2C BUS. If the horizontal high voltage circuit is malfunctioning and the X-ray protector does not work properly, the electron beam may overheat and melt the CRT neck. Therefore this circuit detects these abnormal states and shuts down the RGB output. When pin 40 is low (0V) the output of the R/G/B is set to zero (no signal).

Intelligent Monitor One analog or digital signal can be monitored (Vdd, input of ADCs, Hsync output, etc.) through pin 11. The signal is selected by the MPU, via the I2C BUS.

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Notes

16

FUNCTIONAL BLOCK DIAGRAMS

COLOR TELEVISION SYSTEM

NA7D/A CHASSIS

This section describes the flow diagrams for main functions. Fig. 15 provides the audio signal flow. Fig. 16 provides the video/sync signal flows. Fig. 17 details the I2C operation and Fig. 15 ~ Fig. 18 include various MPU functions and control.

Other sections provide details and other aspects of the operation, such as audio, deflection, power supplies and protection.

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Figure 15: Audio Signal Path

See

Fig. 30

for

19
*

Figure 16: Video & Sync signal path

I2C Bus Line System

The NA7D/A incorporates an Inter-Integrated Circuit (I2C) double polarity bus (see Fig. 17). The I2C bus carries information between devices connected to the bus using two lines, the Serial Data (SDA) and Serial Clock (SCL). Each device has an unique address for data transfer called the Slave Address. When data is transmitted or received, the devices on the bus are either a Master or a Slave. For NA7D/ A chassis, the Master device is the IC001 Microprocessor Unit (MPU). The MPU initiates a data transfer on the bus line and generates the clock signal that permits data to be sent. The MPU then addresses the Slave devices, which receive the transmitted data and return an acknowledgment to the MPU. The I2C bus system performs control functions that replaces many of the mechanical controls needed in a television receiver. Instead of adjusting individual mechanical controls, electronic control functions can be performed using the On Screen Display Menu in Serviceman Mode.

SIGNAL PROCESSOR MCU SIGNAL PROCESSOR MCU

SCL

SDA

Figure 17: I2C Bus 20

See Fig. 30 for details

Figure 18: MPU/VCJ Control

21

Notes

22

AUDIO

COLOR TELEVISION SYSTEM

NA7D/A CHASSIS

MTS Sound Detection And Separation

Composite Signal The composite audio signal from the tuner inputs to MTS Decoder IC2201 pin 14 (MPX in) (see Fig. 19). The signal is processed by a low pass Stereo Filter which passes signals below 15.75kHz. The output from the Stereo Filter contains the L+R signal (mono) and may also contain the L-R signal (stereo) plus the Stereo Pilot signal (stereo broadcast indicator). The signal is then applied to four circuits: Pilot detector Stereo PLL L+R Demod (FM) L-R Demod (AM) Mono or L+R Signal The L+R signal is FM demodulated and then sent to the L+R Filter. The high frequency components of the signal are de-emphasized and sent to the Matrix circuit for left and right channel simulation. LR Signal When the 15.75kHz stereo pilot signal is detected at pin 6, indicating AM stereo broadcast, the stereo PLL switches on the L-R Demod to demodulate the AM signal. The signal is then passed to the L-R Filter which removes the high frequency noise components. The signal is then passed to the L-R/SAP switch, which is controlled by I2C bus user input (Stereo or SAP), and output to pin 15. The signal from pin 15 is coupled via an external capacitor to pin 16 and applied to the dbx circuit. Secondary Audio Program (SAP) mode The input signal applied at MTS IC2201 pin 14 (MPX in) is fed to the SAP Filter and the Noise band pass filter (BPF). The Noise BPF removes components around 240 kHz. If Stereo is selected, the signal is passed through the SAP Noise Detector to the SAP Demod to mute the SAP demodulator. If SAP is selected, the SAP signal is demodulated, filtered for noise components, output via pin 13, and applied to the dbx circuit via pin 12. dbx Effect dbx is a compression, expansion, pre-emphasis, deemphasis system that reduces the overall audio noise level. As the overall level in the audio chain increases, the noise level increases also. With dbx, the audio level increases, but by only half as much. Using a 2 to 1 compression ratio, the input signal is compressed and a shelving filter is referenced to the input level to set the pre-emphasis. A shelving filter is a circuit with a flat frequency response that has two bands of frequencies that are separated by a third band. This third band has either a downward or upward sloping frequency response. The output signal is decompressed and the high frequencies are rolled off by the de-emphasis filter. The output audio signal now has a greater S/N then the input signal. It has a flat frequency response and up to 30 dB less noise. Note:

MTS IC2201 pin 10 is the timing current setting of the dbx rms value detection, and is set at about 1.3V. Pin 6 is the reference power supply stabilization voltage, and is set at about 4.5V.

dbx is a registered trademark of Carillon Electronics Corp. Matrix Circuit The matrix circuit switches the output audio signal according to the selection received from MPU IC001 through the I2C bus at pins 19 (SDA) and 18 (SCL). The signals are output through pins 21 (L-out) and 22 (R-out) to the sound switching circuit.
Selection Mono Stereo SAP Matrix Effect L+R or mono to output to pins 21 & 22 ( L + R ) + ( L R ) to pin 22 ------------------------------------------2 ( L + R ) ( L R ) to pin 21 -----------------------------------------2 SAP to output to pins 21 & 22

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 25 Figure 19: Multiplex Television Sound (MTS)

Figure 20: AGC Audio Path

AGC Audio Control Surround

IC2501 Audio Controller IC2501 Audio Controller/Sound Processor controls all aspects of the sound via the MPU: bass, treble, balance, AGC, AI Sound, and Mute (see Fig. 20). AGC At times the received audio signal level is too high or too low, so special circuits are needed to equalize audio levels across various programming. AGC is designed to detect and compensate for the large variations in audio input levels across TV channels and other sound sources connected to the AV jacks. When AGC is on, the input/output gain is boosted for low signal levels and reduced for high signal levels (see Fig. 21). AGC circuits. At a level predetermined by the RC network on IC2501 pin 5, the internal switch toggles the contacts and adjusts the gain to the output terminals. Bass, Treble, Balance When a user makes an adjustment to the audio output via the front keyboard or the remote control, data from the MPU is clocked (at 12 MHz) via the I2C bus to the IC2501 I2C interface at pins 16 and 17. Pulse width modulation switching controls which DAC will be applied to the audio signal. AI Sound The IC2501 AI Sound circuit uses an algorithm based on the difference in frequency characteristics between music and speech (see Fig. 22 and Fig. 23). The circuit is incorporated by simple hardware and microprocessor control to equalize the sound level across inputs and automatically controls bass and treble to the optimum degree. Continuous speech consists of repetitions of a consonant, a vowel and silence. Power levels change rapidly. Consonants have large changes in power level and spectrum; vowels are steadier, with smaller changes. Musical sounds have relatively small changes in power and spectrum, with longer steady parts.

Figure 21: AGC Effect on Sound The circuit detects level changes via AGC Det 1, which outputs to AGC Det 2 (Control circuit) to provide a gain factor for both left and right channel

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microprocessor samples the waveform and sets threshold values, then makes judgements whether to boost bass and treble for music or reduce them for speech.

Figure 22: AI Audio Algorithm The original waveform (speech or music) is sent to a level rectifying circuit, a waveshaping circuit, and then is fed to the microprocessor. The Figure 23: AI Audio Frequency Response

Audio Multiplex System

Abstract In audio multiplex broadcasting, a separate sound signal, unrelated to the broadcast content, is sent in addition to the monaural sound. This is done in order to accomplish transmission of stereo signals and is achieved via frequency multiplex technology. In todays broadcast, the traditional L + R and L - R signals are sent. The signals are monitored, cleaned, decompressed and finally separated in the matrix circuit to the L and R components. Matrix: (L+R) + (L-R) = 2L (L+R) - (L-R) = 2R The North American System The North American Television sound system is composed of three types of modulation: FM, FM Multiplex (stereo and SAP) and AM (see Fig. 24). Monaural Broadcasting: Monaural sound (L + R) is sent as 25kHz FM signal in the 4.5MHz audio carrier wave. Multiplex Broadcasting: The L (left) and R (right) signals are sent in two different packets in addition to other required signals. The multiplex signal has four components: L + R - identical to the monaural signal. L - R - amplitude modulated with a center frequency of 35.1kHz (twice the horizontal frequency of 15.75kHz.) Secondary Audio Programming (SAP) - FM modulated (+/- 15kHz) with a center frequency of 78.75kHz (5fh).

Stereo pilot - FM signal at 15.75kHz ( 5kHz).

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AM 50kHz

Carrier Deviation

FM 25kHz ST Pilot Signal 5kHz 2 (L - R) FM 15kHz SAP fH fH = 15.75kHz Figure 24: North American Multiplex 2fH 3fH 4fH 5fH f (Hz)

L+R

Audio Amplifiers Fig. 25 depicts the process in which the audio amplifiers operate. The MPU controls the volume and mute operation. The amplified signals output at pin 10 and is sent to the speakers. Note that on a mono receivers only the left audio amplifier is operational, sending the signal to the single speaker.

Figure 25: Audio Amplifiers

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DEFLECTION

COLOR TELEVISION SYSTEM

NA7D/A CHASSIS

Deflection Circuit
Vertical Output Circuit
Sawtooth Wave Generating Circuit The vertical sync pulse at pin 2 creates a timing sawtooth wave in C452 (see Fig. 26). This determines the amplitude of the voltage at pin 4, which is controlled by pin 68 of the MPU. This adjustment is available in service mode. The voltage at pin 4 sets the 50-60 Hz amplitude for the voltage at pin 5. The vertical drive corrects the rectilinear straightness, vertical amplitude and pulse amplitude in the same IC. Drive Circuit 1. The sawtooth wave is sent to the vertical drive circuit. The wave current in the vertical deflection coil is fed back to pin 7 to improve the vertical straightness of the signal. The vertical drive section of IC451 amplifies the sawtooth wave to correct for straightness of the wave so the vertical output circuit will operate. The corrected wave is sent to the vertical output circuit.

2.

Figure 26: IC451 - Vertical Deflection Circuit

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Vertical Output Pulse Amplifying Circuit

Vertical Output Circuit Operation 1. The sawtooth wave voltage from the vertical drive circuit is inverted in Q1 and input to Q2 and Q3 (see Fig. 27). The Q2 and Q3 threshold voltage is set to the center of the sawtooth wave. The first half of the wave turns on Q2, resulting in the charging current (a) being sent to C1 (see Fig. 28). The second half of the wave turns on Q3, resulting in the discharge current (b) being output from C1. A sawtooth wave current is sent to the deflection coil. However, to reverse the current within the vertical flyback period, the pulse from the pulse amplifier circuit is added to the collector of Q2. This results in a large voltage input to the deflection coil during the instant after Q2 is turned on. Pulse Amplifier Circuit (Pump Up) Operation 1. When currents (a) and (b) are sent (during the vertical scanning period), Q4 is off because no voltage is input to its base. A negative pulse from the vertical deflection coil is fed back to the base of Q5, which turns Q5 on. 26V are sent through D1, which inputs a 26V charge to C2. The differentiated pulse during the flyback period is added to the base of Q4 and Q5, turning Q4 on and Q5 off. 26V is input to C2 negative (-) pin through Q4 and added to the 26V C2 charge, resulting in a 52V pulse at pin 13 (see Fig. 29). The 52V pulse is input to the deflection coil, raising the electron beam in one instant.

2.

3.

2.

4.

3.

Figure 27: IC451 - Vertical Output Pulse Amplifying Circuit

Voltage input to the Deflection Coil Q1 Collector Differential

Pin13 voltage
Q2 ON Q3 ON

Waveform of Q4-Q5 base

Pin 9 voltage

Figure 28: IC451 pin 12 Voltage

Figure 29: Pump Up Wave

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Horizontal Output Circuit

Horizontal Output The square wave of the horizontal signal sent by the MPU is applied to Q501, the horizontal drive. That turns Q501 on (see Fig. 30). 130 volts flows through the primary of T501 and the horizontal drive, Q501. A horizontal pulse is induced into the secondary windings of T501. This pulse drives the horizontal output Q551 to make the sawtooth wave current in H-DY (horizontal deflection coil) and EHT (extra high tension voltage).

Figure 30: Horizontal Drive and Output Circuit

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Horizontal Drive Circuit

Figure 31: Horizontal Drive Circuit

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Notes

34

POWER SUPPLY

COLOR TELEVISION SYSTEM

NA7D/A CHASSIS

 36 Figure 32: Power Supply Overview (NA7D)

 37 Figure 33: Power Supply Overview (NA7A)

Protection Circuits
Over Current Protection
The over current protection circuit is designed to prevent damage to the Receiver due to shorts in the 130V line. During normal operation, current flowing through R821 & R822 produces low voltage across the resistors that is not sufficient to turn Q820 ON. When a short occurs, the current through R821 & R822 increases, causing a rise in the voltage across the resistors. When the voltage drop reaches the point where Vbe is high enough to turn Q820 ON, a signal is sent by Q820 to the MPU pin 9 (KEY2). The MPU then shuts the Receiver OFF.

Spot Killer
The spot killer circuit is designed to prevent the high intensity beam that could form at the center of the screen in an event of abnormal power loss. The circuit is made up of Q605, Q606 and related components. During normal operation, the high voltage at the base of the PNP transistor, Q605, keeping it OFF. When Q605 is off, it keeps Q606 OFF. Under these conditions, C606 is charged when Q606 is OFF. That prevents D607 ~ D609 from conducting. That also allows the only path for the RGB current to flow (from Q006 ~ Q008) to the C board, the CRT driver. When the 12V line goes low due to an abrupt loss of power, Q605 & Q606 turn ON and C606 discharges allowing the output from Q006 ~ Q008 to flow through D607 ~ D609. Therefore the RGB output signal is prevented from flowing to the C board. See Fig. 34.

Figure 34: Spotkiller Protector Circuit

Neck Protector (Fig. 35)

The neck protector protects the CRT in an event of shorting in the V-out or DY circuits. The circuit consists of Q451 & Q452 and related components. During normal operation, the vertical out from IC451 conducts through the Zener diode, D452. That keeps Q451 ON and Q452 OFF. A high signal is sent to the MPU pin 40 indicating normal conditions. When the Vert out of IC451 is low (damage to the IC), it turns Q451 OFF. The base of Q452 is at ~9V, turning it ON. Q452 starts conducting, lowering the voltage at MPU pin 40. The MPU senses the change that occurred and it shuts down the RGB output, resulting in a black screen

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Figure 35: Neck Protector Circuit

Figure 36: Standby Voltage

130V DC Voltage Supply

Power

Figure 37: DC Operation (AC/DC Models Only)

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Figure 38: Degaussing Coil (AC/DC Models Only)

Printed in USA K01032593ZR0330

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