ON/OFF DELAY TIMERS

ChandraKanth P, 11110024, 2nd year.

Function Description:
Delay timers are of two types. They are On delay timer and Off delay timer. On delay timer will give the output only for one clock after the delay given by the user. Similarly, Off delay timer will be high for the given delay after that it will be low. This timer will have inputs like type to select which function to perform based on the input delay time given by the user. Note: Dealy can only integer multiples of clock cycles only.

Verilog Code:
module onoffdelay(in, type, delay, clk, out); input in, type, clk; input [3:0]delay; output out; reg out; integer count; always @(negedge in) begin if (type) count=0; else count=delay; end always @(posedge clk) begin if (type) begin //type =1 for on delay //type =0 for off delay

if (count==delay) begin out=1'b1; count=count+1; end else begin out=1'b0; count=count+1; end end else begin if (count==0) begin out=1'b0; count=count; end else begin out=1'b1; count=count-1; end end end endmodule

1] Test bench for on delay timer:

module test_delay; reg in, type, clk; reg [3:0] delay; wire out; onoffdelay dut(in, type, delay, clk, out); initial begin clk=0; #5 forever #5 clk=!clk; end initial begin in=1'b0; #5; in=1'b1; #5; in=1'b0; #5; end initial begin delay=4'b0011; type=1'b1; end endmodule

Simulation results for on delay timer:

2] Test bench for Off delay timer:

module test_delay; reg in, type, clk; reg [3:0] delay; wire out; onoffdelay dut(in, type, delay, clk, out); initial begin clk=0; #5 forever #5 clk=!clk; end initial begin in=1'b0;

#5; in=1'b1; #5; in=1'b0; #5; end initial begin delay=4'b0011; type=1'b1; end endmodule

RTL Schematic:

Technology RTL Schematic:

Synthesis Report:
========================================================================= HDL Synthesis Report

Macro Statistics # Adders/Subtractors 4-bit adder carry out # Counters 32-bit up counter # Registers 1-bit register # Comparators 33-bit comparator equal :1 :1 :1 :1 :1 :1 :1 :1

========================================================================= * Advanced HDL Synthesis *

Macro Statistics # Adders/Subtractors 4-bit adder carry out # Counters 32-bit up counter # Registers Flip-Flops # Comparators 33-bit comparator equal :1 :1 :1 :1 :1 :1 :1 :1

========================================================================= Final Register Report

Macro Statistics # Registers Flip-Flops : 33 : 33

========================================================================= Design Statistics # IOs :8

Cell Usage : # BELS # # # # # # # # # GND INV LUT1 LUT2 LUT3 LUT4 MUXCY VCC XORCY : 120 :1 :1 : 31 :3 :1 : 10 : 40 :1 : 32 : 33 :1 : 31 :1 :1 :1 :7 :6 :1

# FlipFlops/Latches # # # FDE FDRE FDRSE

# Clock Buffers # BUFGP

# IO Buffers # # IBUF OBUF

========================================================================= Clock Information: Clock Signal clk | Clock buffer(FF name) | Load | | BUFGP | 33 |

-----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -4 Minimum period: 5.204ns (Maximum Frequency: 192.160MHz) Minimum input arrival time before clock: 4.807ns Maximum output required time after clock: 4.283ns Maximum combinational path delay: No path found

Timing Detail: -------------All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 5.204ns (frequency: 192.160MHz) Total number of paths / destination ports: 560 / 33 ------------------------------------------------------------------------Delay: Source: Destination: Source Clock: 5.204ns (Levels of Logic = 32) count_1 (FF) count_31 (FF) clk rising

Destination Clock: clk rising Data Path: count_1 to count_31

Gate Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)