MSP 430

MSP (Mixed signal processor) It is much more than a CPU. This is the reason why we call it the Mixed Signal Processor. 430 (April 30 ) release Developed by Texas instruments Designed to create a microcontroller that consumes very little current in sleep mode and performs a task as fast as possible in active mode. 16-bit , 27 instructions , 16 registers Includes on-chip memory, flash memory as well as RAM, and a host of peripherals. It range from 20 pin ( 1K of ROM and 128 bytes of RAM) to 100 pin ( 60K and 2K RAM) Part Numbering Part number is determined on the basis of its capabilities All devices have M S P 4 3 0 Mt Fa Fb Mc Mt Memory Type (ROM , Flash , OTP(One time programmable), EPROM) (C,F,P,E) Fa , Fb Family and Features 1. (10,11) Basic 2. (12,13) Hardware UART (Universal Asynchronous Reciever/Transmitter) 3. (14) Hardware UART, Hardware Multiplier 4. (31,32) LCD Controller 5. (33) LCD Controller , Hardware UART, Hardware Multiplier 6. (41) LCD Controller 7. (43) LCD Controller , Hardware UART 8. (44) LCD Controller , Hardware UART, Hardware Multiplier Mc Memory capability 1. (0) 1KB ROM , 128 B RAM 2. (1) 2KB ROM , 128 B RAM 3. (2) 4KB ROM , 256 B RAM 4. (3) 8KB ROM , 256 B RAM 5. (4) 12KB ROM , 512 B RAM 6. (5) 16KB ROM , 512 B RAM 7. (6) 24KB ROM , 1 KB RAM 8. (7) 32KB ROM , 1 KB RAM 9. (8) 48KB ROM , 2 KB RAM 10. (9) 60KB ROM , 2 KB RAM Example MSP430F435

Architecture

CPU

The MSP430 includes a 16-bit RISC architecture which has only 27 instructions. The instruction set is orthogonal which means that there are no restrictions on the operand addressing modes are permitted for an instruction. 16-bit RISC architecture, which is capable of processing instructions on either bytes or words.
The CPU has a 16-bit ALU, four dedicated registers and twelve working registers, which makes the MSP430 a high performance microcontroller suitable for low power applications.

ALU The 430 processor includes a typical ALU (arithmetic logic unit).The ALU handles addition, subtraction, comparison and logical (AND, OR,XOR) operations.

The CPU incorporates sixteen 16-bit registers: Four registers (R0, R1, R2 and R3) have dedicated functions; There are 12 working registers (R4 to R15) for general use. (BOOK) Status register

Addressing modes Register Mode MOV R4, R5 First operand is in register mode but second can be in any mode

Indexed Mode

Symbolic Move content of XPT(X pointer) to YPT(Y pointer)

Absolute

Indirect Register Mode

Indirect Auto Increment Mode

Immediate Mode

Instruction set
There are three core-instruction formats: Double operand;

 Single operand; Program flow control - Jump. Double operand instructions

Memory Structure
The MSP430 is available with any one of several different memory types. The memory type is identified by the letter immediately following MSP430 in the part numbers.

ROM
ROM devices, also known as masked devices, are identified by the letter C in the part numbers. They are strict ROM devices, shipped pre-programmed.

OTP
OTP is an acronym for one time programmable, which pretty well describes the functionality of these devices. Identified by the letter P in the part number. OTPs are ideal for low and medium volume applications.

EPROM
They are identified by the letter E in the part number. These devices are electrically programmable, and UV-erasable.

Flash
Flash devices, identified by the letter F in the part number, have become very popular in the past few years. They are more expensive, but code space can be erased and reprogrammed, thousands of times if necessary.

Interrupts
The 430 offers numerous interrupt sources, both external and internal. Interrupts are prioritized, with the reset interrupt having the highest priority. All maskable interrupts are turned off by resetting of the GIE (Global Interrupt Enable) flag in the Status Register. Each maskable interrupt also has an individual enable/disable flag, located in peripheral registers or the individual module. When an interrupt occurs, the program counter of the next instruction and the status register are pushed to the stack. Return to program flow is accomplished by the reti instruction. Reti automatically pops the status register and program counter.

Watchdog Timer
The Watchdog Timer is designed primarily as an error recovery mechanism. It is an independent counter, which, upon overflow, issues an interrupt request. All control of he WDT is performed through the Watchdog Timer Control Register. Its main function is to protect the system against malfunctions but it can be used as an interval timer .

Timer A

In compare mode, the value to be compared to is loaded into the CCR register. When the timer value is equal to the value in the CCR register, an interrupt is generated. When using CCR0, the timer has a selectable mode in which the timer register resets to zero after reaching the compare value.

Timer A Register
TAR, Timer A Register Address: 0x0170h All bits are readable and writable. This register is the location of the Timer A count. TACTL, Timer A Control Register. Address: 0x0160h All bits are readable and writable. TACCTLx, Capture/Compare Control Registers. TAIV, Timer A Interrupt Vector Register. Address: 0x012E