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PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2XK20/4XK20 DEVICES Address Name Address
PIC18F2XK20/4XK20 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2XK20/4XK20 DEVICES Address Name Address

TABLE 5-1:

SPECIAL FUNCTION REGISTER MAP FOR PIC18F2XK20/4XK20 DEVICES

Address

Name

Address

FFFh

TOSU

FD7h

FFEh

TOSH

FD6h

FFDh

TOSL

FD5h

FFCh

STKPTR

FD4h

FFBh

PCLATU

FD3h

FFAh

PCLATH

FD2h

FF9h

PCL

FD1h

FF8h

TBLPTRU

FD0h

FF7h

TBLPTRH

FCFh

FF6h

TBLPTRL

FCEh

FF5h

TABLAT

FCDh

FF4h

PRODH

FCCh

FF3h

PRODL

FCBh

FF2h

INTCON

FCAh

FF1h

INTCON2

FC9h

FF0h

INTCON3

FC8h

FEFh

INDF0 (1)

FC7h

FEEh

POSTINC0 (1)

FC6h

FEDh

POSTDEC0 (1)

FC5h

FECh

PREINC0 (1)

FC4h

FEBh

PLUSW0 (1)

FC3h

FEAh

FSR0H

FC2h

FE9h

FSR0L

FC1h

FE8h

WREG

FC0h

FE7h

INDF1 (1)

FBFh

FE6h

POSTINC1 (1)

FBEh

FE5h

POSTDEC1 (1)

FBDh

FE4h

PREINC1 (1)

FBCh

FE3h

PLUSW1 (1)

FBBh

FE2h

FSR1H

FBAh

FE1h

FSR1L

FB9h

FE0h

BSR

FB8h

FDFh

INDF2 (1)

FB7h

FDEh

POSTINC2 (1)

FB6h

FDDh

POSTDEC2 (1)

FB5h

FDCh

PREINC2 (1)

FB4h

FDBh

PLUSW2 (1)

FB3h

FDAh

FSR2H

FB2h

FD9h

FSR2L

FB1h

FD8h

STATUS

FB0h

Name

TMR0H

TMR0L

T0CON

(2)

OSCCON

HLVDCON

WDTCON

RCON

TMR1H

TMR1L

T1CON

TMR2

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

ADCON2

CCPR1H

CCPR1L

CCP1CON

CCPR2H

CCPR2L

CCP2CON

PSTRCON

BAUDCON

PWM1CON

ECCP1AS

CVRCON

CVRCON2

TMR3H

TMR3L

T3CON

SPBRGH

Address

Name

FAFh

FAEh

FADh

FACh

FABh

FAAh

FA9h

FA8h

FA7h

FA6h

FA5h

FA4h

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADRH (4)

EEADR

EEDATA

EECON2 (1)

EECON1

RCSTA EEADRH ( 4 ) EEADR EEDATA EECON2 ( 1 ) EECON1 — ( 2 )

(2)

(2)

FA3h (2)

IPR2

FA1h

PIE2

F9Fh

PIR1

F9Dh

F9Ch (2)

PIE1

IPR1

FA2h

PIR2

FA0h

F9Eh

PIR1 F9Dh F9Ch — ( 2 ) PIE1 IPR1 FA2h PIR2 FA0h F9Eh F9Bh F9Ah F99h

F9Bh

F9Ah

F99h

F98h

F97h (2)

F96h

F95h

F94h

F93h

F92h

F91h

F90h

TRISE

OSCTUNE

( 2 ) F96h F95h F94h F93h F92h F91h F90h TRISE OSCTUNE — ( 2 )

(2)

(2)

(2)

(3)

TRISD

(3)

TRISC

TRISB

TRISA

2 ) — ( 2 ) ( 3 ) TRISD ( 3 ) TRISC TRISB TRISA

(2)

(2)

F8Fh

F8Eh (2)

F8Dh

F8Ch

F8Bh

F8Ah

(2)

LATE

(3)

LATD

(3)

LATC

LATB

F89h

F88h (2)

LATA

3 ) LATD ( 3 ) LATC LATB F89h F88h — ( 2 ) LATA Address

Address

F87h

F86h

F85h

F84h

F83h

F82h

F81h

F80h

F7Fh

F7Eh

F7Dh

F7Ch

F7Bh

F7Ah

F79h

F78h

F77h

F76h

F75h

F74h

F73h

F72h

F71h

F70h

F6Fh

F6Eh

F6Dh

F6Ch

F6Bh

F6Ah

F69h

F68h

F67h

F66h

F65h

F64h

F63h

F62h

F61h

F60h

Name

(2)

(2)

(2)

PORTE

PORTD (3)

PORTC

PORTB

PORTA

ANSELH

ANSEL

IOCB

WPUB

CM1CON0

CM2CON0

CM2CON1

SLRCON

SSPMSK

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

Note 1:

This is not a physical register.

2:

Unimplemented registers are read as ‘0’.

3:

This register is not available on PIC18F2XK20 devices.

4:

This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET Mnemonic,     16-Bit Instruction Word Status
PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET Mnemonic,     16-Bit Instruction Word Status

TABLE 24-2:

PIC18FXXXX INSTRUCTION SET

Mnemonic,

   

16-Bit Instruction Word

Status

 

Operands

Description

 

Cycles

MSb

LSb

Affected

Notes

BYTE-ORIENTED OPERATIONS

 

ADDWF

f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d

Add WREG and f Add WREG and CARRY bit to f AND WREG with f

1

0010

01da0

ffff

ffff

C, DC, Z, OV, N

1, 2

ADDWFC

1

0010

0da

ffff

ffff

C, DC, Z, OV, N

1, 2

ANDWF

1

0001

01da

ffff

ffff

Z, N

1,2

CLRF

Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f

1

0110

101a

ffff

ffff

Z

2

COMF

1

0001

11da

ffff

ffff

Z, N

1, 2

CPFSEQ

1

(2 or 3)

0110

001a

ffff

ffff

None

4

CPFSGT

1

(2 or 3)

0110

010a

ffff

ffff

None

4

CPFSLT

1

(2 or 3)

0110

000a

ffff

ffff

None

1, 2 1, 2, 3, 4

DECF

1

0000

01da

ffff

ffff

C, DC, Z, OV, N

DECFSZ

1

(2 or 3)

0010

11da

ffff

ffff

None

1, 2, 3, 4 1, 2 1, 2, 3, 4

DCFSNZ

1

(2 or 3)

0100

11da

ffff

ffff

None

INCF

1

0010

10da

ffff

ffff

C, DC, Z, OV, N

INCFSZ

1

(2 or 3)

0011

11da

ffff

ffff

None

4

INFSNZ

1

(2 or 3)

0100

10da

ffff

ffff

None

1, 2

IORWF

1

0001

00da

ffff

ffff

Z, N

1, 2

MOVF

1

0101

00da

ffff

ffff

Z, N

1

MOVFF

Move f s (source) to

1st word

2

1100

ffff

ffff

ffff

None

 

f d (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f

1111

ffff

ffff

ffff

MOVWF

f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a

1

0110

111a

ffff

ffff

None

MULWF

1

0000

001a

ffff

ffff

None

1, 2

NEGF

1

0110

110a

ffff

ffff

C, DC, Z, OV, N

RLCF

1

0011

01da

ffff

ffff

C, Z, N

1, 2

RLNCF

1

0100

01da

ffff

ffff

Z, N

RRCF

1

0011

00da

ffff

ffff

C, Z, N

RRNCF

1

0100

00da

ffff

ffff

Z, N

SETF

1

0110

100a

ffff

ffff

None

1, 2

SUBFWB

1

0101

01da

ffff

ffff

C, DC, Z, OV, N

SUBWF

f, d, a f, d, a

1

0101

11da

ffff

ffff

C, DC, Z, OV, N

1, 2

SUBWFB

1

0101

10da

ffff

ffff

C, DC, Z, OV, N

SWAPF

f, d, a f, a f, d, a

1

0011

10da

ffff

ffff

None

4

TSTFSZ

1

(2 or 3)

0110

011a

ffff

ffff

None

1, 2

XORWF

1

0001

10da

ffff

ffff

Z, N

Note

1:

When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

2:

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

3:

assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

4:

executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic,     16-Bit Instruction Word
PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic,     16-Bit Instruction Word

TABLE 24-2:

PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

   

16-Bit Instruction Word

 

Status

 

Operands

Description

 

Cycles

MSb

LSb

Affected

Notes

BIT-ORIENTED OPERATIONS

 

BCF

f, b, a f, b, a f, b, a f, b, a f, d, a

Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f

1

1001

bbba

ffff

ffff

None

1, 2

BSF

1

1000

bbba

ffff

ffff

None

1, 2

BTFSC

1

(2 or 3)

1011

bbba

ffff

ffff

None

3, 4

BTFSS

1

(2 or 3)

1010

bbba

ffff

ffff

None

3, 4

BTG

1

0111

bbba

ffff

ffff

None

1, 2

CONTROL OPERATIONS

 

BC

n

Branch if Carry

1

(2)

1110

0010

nnnn

nnnn

None

 

BN

n

Branch if Negative

1

(2)

1110

0110

nnnn

nnnn

None

BNC

n

Branch if Not Carry

1

(2)

1110

0011

nnnn

nnnn

None

BNN

n

Branch if Not Negative

1

(2)

1110

0111

nnnn

nnnn

None

BNOV

n

Branch if Not Overflow

1

(2)

1110

0101

nnnn

nnnn

None

BNZ

n

Branch if Not Zero

1

(2)

1110

0001

nnnn

nnnn

None

BOV

n

Branch if Overflow

1

(2)

1110

0100

nnnn

nnnn

None

BRA

n

Branch Unconditionally

2

1101

0nnn

nnnn

nnnn

None

BZ

n

Branch if Zero

1

(2)

1110

0000

nnnn

nnnn

None

CALL

n, s

Call subroutine

1st word

2

1110

110s

kkkk

kkkk

None

 

2nd word

1111

kkkk

kkkk

kkkk

CLRWDT

Clear Watchdog Timer

1

0000

0000

0000

0100

TO, PD

DAW

Decimal Adjust WREG

1

0000

0000

0000

0111

C

GOTO

n

Go to address

1st word

2

1110

1111

kkkk

kkkk

None

 

2nd word

1111

kkkk

kkkk

kkkk

NOP

No Operation

1

0000

0000

0000

0000

None

NOP

No Operation

1

1111

xxxx

xxxx

xxxx

None

4

POP

Pop top of return stack (TOS)

1

0000

0000

0000

0110

None

PUSH

Push top of return stack (TOS)

1

0000

0000

0000

0101

None

RCALL

n

Relative Call Software device Reset

2

1101

1nnn

nnnn

nnnn

None

RESET

1

0000

0000

1111

1111

All

RETFIE

s

Return from interrupt enable

2

0000

0000

0001

000s

GIE/GIEH,

   

PEIE/GIEL

RETLW

k

Return with literal in WREG

2

0000

1100

kkkk

kkkk

None

RETURN

s

Return from Subroutine

2

0000

0000

0001

001s

None

SLEEP

Go into Standby mode

1

0000

0000

0000

0011

TO, PD

Note

1:

When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.

2:

3:

4:

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic,       16-Bit Instruction
PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic,       16-Bit Instruction

TABLE 24-2:

PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

     

16-Bit Instruction Word

Status

 

Operands

Description

Cycles

MSb

LSb

Affected

Notes

LITERAL OPERATIONS

 

ADDLW

k

Add literal and WREG

1

0000

1111

kkkk

kkkk

C, DC, Z, OV, N

 

ANDLW

k

AND literal with WREG

1

0000

1011

kkkk

kkkk

Z, N

IORLW

k

Inclusive OR literal with WREG Move literal (12-bit) 2nd word

1

0000

1001

kkkk

kkkk

Z, N

LFSR

f, k

2

1110

1110

00ff

kkkk

None

 

to FSR(f)

1st word

1111

0000

kkkk

kkkk

MOVLB

k

Move literal to BSR<3:0>

1

0000

0001

0000

kkkk

None

MOVLW

k

Move literal to WREG

1

0000

1110

kkkk

kkkk

None

MULLW

k

Multiply literal with WREG

1

0000

1101

kkkk

kkkk

None

RETLW

k

Return with literal in WREG

2

0000

1100

kkkk

kkkk

None

SUBLW

k

Subtract WREG from literal

1

0000

1000

kkkk

kkkk

C, DC, Z, OV, N

XORLW

k

Exclusive OR literal with WREG

1

0000

1010

kkkk

kkkk

Z, N

DATA MEMORY

DATA MEMORY

PROGRAM MEMORY OPERATIONS

 

TBLRD*

Table Read Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write Table Write with post-increment Table Write with post-decrement Table Write with pre-increment

2

0000

0000

0000

1000

None

 

TBLRD*+

0000

0000

0000

1001

None

TBLRD*-

0000

0000

0000

1010

None

TBLRD+*

0000

0000

0000

1011

None

TBLWT*

2

0000

0000

0000

1100

None

TBLWT*+

0000

0000

0000

1101

None

TBLWT*-

0000

0000

0000

1110

None

TBLWT+*

0000

0000

0000

1111

None

Note

1:

When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

2:

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

3:

assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

4:

executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 24.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W Syntax: ADDLW   k Operands: 0
PIC18F2XK20/4XK20 24.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W Syntax: ADDLW   k Operands: 0

24.1.1 STANDARD INSTRUCTION SET

ADDLW

ADD literal to W

Syntax:

ADDLW

 

k

Operands:

0

Operands: 0 k 255

k

k

255

Operation:

(W) + k

Operation: (W) + k W

W

Status Affected:

N, OV, C, DC, Z

 

Encoding:

 

0000

 

1111

kkkk

kkkk

Description:

The contents of W are added to the 8-bit literal ‘k’ and the result is placed in

W.

 

Words:

1

Cycles:

1

Q Cycle Activity:

 

Q1

Q2

Q3

Q4

Decode

Read

Process

Write to W

literal ‘k’

Data

Example:

ADDLW

15h

Before Instruction

W

=

10h

After Instruction

W

=

25h

ADDWF

ADD W to f

Syntax:

ADDWF

 

f {,d {,a}}

Operands:

0

Operands: 0 f 255

f

f

255

d

[0,1]

 

a

[0,1]

Operation:

(W) + (f)

Operation: (W) + (f) dest

dest

Status Affected:

N, OV, C, DC, Z

 

Encoding:

 

0010

   

01da

ffff

ffff

Description:

Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction

Words:

Cycles:

Q Cycle Activity:

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

1

1

in Indexed Literal Offset Mode” for details. 1 1 95 (5Fh). See Q1 Q2 Q3 Q4

95 (5Fh). See

Q1

Q2

Q3

Q4

Decode

Read

Process

Write to

register ‘f’

Data

destination

Example:

ADDWF

Before Instruction

W

=

17h

REG

=

0C2h

After Instruction

W

=

0D9h

REG

=

0C2h

REG, 0, 0

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 ADDWFC ADD W and CARRY bit to f Syntax: ADDWFC f {,d {,a}}   Operands:
PIC18F2XK20/4XK20 ADDWFC ADD W and CARRY bit to f Syntax: ADDWFC f {,d {,a}}   Operands:

ADDWFC

ADD W and CARRY bit to f

Syntax:

ADDWFC

f {,d {,a}}

 

Operands:

0

Operands: 0 f 255  

f

f

255

 

d

[0,1]

 

a

[0,1]

Operation:

(W) + (f) + (C)

Operation: (W) + (f) + (C) dest  

dest

 

Status Affected:

N,OV, C, DC, Z

 

Encoding:

 

0010

00da

 

ffff

ffff

Description:

Add W, the CARRY flag and data mem-

Words:

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

in Indexed Literal Offset Mode” for details. 1 95 (5Fh). See Cycles: 1 Q Cycle Activity:

95 (5Fh). See

Cycles:

1

Q Cycle Activity:

 

Q1

Q2

Q3

Q4

Decode

Read

Process

Write to

register ‘f’

Data

destination

Example:

ADDWFC

REG, 0, 1

Before Instruction CARRY bit =

1

REG

=

02h

W

=

4Dh

After Instruction

CARRY bit =

0

REG

=

02h

W

=

50h

ANDLW

AND literal with W

Syntax:

ANDLW

 

k

Operands:

0

Operands: 0 k 255

k

k

255

Operation:

(W) .AND. k

Operation: (W) .AND. k W

W

Status Affected:

N, Z

 

Encoding:

 

0000

     

1011

kkkk

kkkk

Description:

The contents of W are AND’ed with the 8-bit literal ‘k’. The result is placed in W.

Words:

1

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

 

Decode

Read literal

Process

Write to W

‘k’

Data

Example:

ANDLW

05Fh

Before Instruction

W

=

A3h

After Instruction

W

=

03h

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 ANDWF AND W with f Syntax: ANDWF f {,d {,a}}   Operands: 0 f 255
PIC18F2XK20/4XK20 ANDWF AND W with f Syntax: ANDWF f {,d {,a}}   Operands: 0 f 255

ANDWF

AND W with f

Syntax:

ANDWF

f {,d {,a}}

 

Operands:

0

Operands: 0 f 255

f

f

255

d

[0,1]

 

a

[0,1]

Operation:

(W) .AND. (f)

(W) .AND. (f) dest

dest

 

Status Affected:

N, Z

 

Encoding:

 

0001

01da

ffff

ffff

Description:

The contents of W are AND’ed with

register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction

set

is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

(5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:

1

Cycles:

1

Q Cycle Activity:

 

Q1

Q2

 

Q3

 

Q4

Decode

Read

 

Process

Write to

 

register ‘f’

Data

destination

Example:

ANDWF

 

REG, 0, 0

 

Before Instruction

W

=

17h

REG

=

C2h

After Instruction

W

=

02h

REG

=

C2h

BC

Branch if Carry

Syntax:

BC

n

Operands:

-128

-128

n

n

127

Operation:

if CARRY bit is ‘1

 

(PC) + 2 + 2n

(PC) + 2 + 2n

PC

Status Affected:

None

Encoding:

1110

 

0010

nnnn

nnnn

Description:

If the CARRY bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Words:

1

Cycles:

1(2)

Q

Cycle Activity:

If

Jump:

 

Q1

Q2

Q3

Q4

Decode

Read literal

Process

Write to PC

‘n’

 

Data

No

No

 

No

No

operation

operation

operation

operation

If

No Jump:

 
 

Q1

Q2

Q3

Q4

Decode

Read literal

Process

No

‘n’

 

Data

operation

Example:

HERE

BC

5

Before Instruction

PC

=

address (HERE)

After Instruction

If CARRY

=

1;

PC

=

address (HERE + 12)

If CARRY

=

0;

PC

=

address (HERE + 2)

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 BCF Bit Clear f   BN   Branch if Negative   Syntax:   BCF f,
PIC18F2XK20/4XK20 BCF Bit Clear f   BN   Branch if Negative   Syntax:   BCF f,

BCF

Bit Clear f

 

BN

 

Branch if Negative

 

Syntax:

 

BCF

f, b {,a}

 

Syntax:

 

BN

n

Operands:

0

f b
f
b

255

7

 

Operands:

-128

Operands: 0 f b 255 7   Operands: -128 n 127

n

Operands: 0 f b 255 7   Operands: -128 n 127

127

 

0

Operation:

if NEGATIVE bit is ‘1

 

a

[0,1]

(PC) + 2 + 2n

(PC) + 2 + 2n

PC

Operation:

 

0

f<b>

f<b>

Status Affected:

 

None

 

Status Affected:

None

 

Encoding:

1110

 

0110

nnnn

nnnn

Encoding:

 

1001

bbba

ffff

ffff

Description:

If the NEGATIVE bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Description:

Bit ‘b’ in register ‘f’ is cleared.

 
 

If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction

 

set

is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

mode whenever f
 

95 (5Fh). See

Words:

 

1

Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed

Cycles:

1(2)

 

Literal Offset Mode” for details.

Q

Cycle Activity:

 

Words:

 

1

If

Jump:

Cycles:

1

 

Q1

Q2

 

Q3

Q4

       
 

Decode

Read literal

Process

Write to PC

Q Cycle Activity:

   

‘n’

   

Data

 

Q1

Q2

Q3

 

Q4

No

 

No

   

No

 

No

Decode

 

Read

Process

 

Write

operation

operation

 

operation

operation

 

register ‘f’

Data

register ‘f’

If

No Jump:

 
 

Q1

 

Q2

 

Q3

Q4

Example:

 

BCF

FLAG_REG,

7, 0

Decode

Read literal

Process

 

No

 

Before Instruction

   

‘n’

   

Data

operation

FLAG_REG =

C7h

 

After Instruction

 

Example:

 

HERE

 

BN

Jump

 

FLAG_REG =

47h

   
   

Before Instruction

 
 

PC

=

address (HERE)

 

After Instruction

 

If NEGATIVE

=

1;

PC

=

address (Jump)

 

If NEGATIVE

=

0;

PC

=

address (HERE + 2)

 

PIC18F2XK20/4XK20

PIC18F2XK20/4XK20 BNC Branch if Not Carry   BNN Branch if Not Negative   Syntax: BNC n
PIC18F2XK20/4XK20 BNC Branch if Not Carry   BNN Branch if Not Negative   Syntax: BNC n

BNC

Branch if Not Carry

 

BNN

Branch if Not Negative

 

Syntax:

BNC

n

Syntax:

BNN

n

Operands:

-128

Operands: -128 n 127 Operands: -128 n 127

n

Operands: -128 n 127 Operands: -128 n 127

127

Operands:

-128

Operands: -128 n 127 Operands: -128 n 127

n

Operands: -128 n 127 Operands: -128 n 127

127

Operation:

if CARRY bit is ‘0

 

Operation:

if NEGATIVE bit is ‘0

 

(PC) + 2 + 2n

(PC) + 2 + 2n

PC

(PC) + 2 + 2n

(PC) + 2 + 2n

PC

Status Affected:

None

 

Status Affected:

None

 

Encoding:

1110

 

0011

nnnn

nnnn

Encoding:

1110

 

0111

nnnn

nnnn

Description:

If the CARRY bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Description:

If the NEGATIVE bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Words:

1

Words:

1

Cycles:

1(2)

Cycles:

1(2)

 

Q

Cycle Activity:

Q

Cycle Activity:

 

If

Jump:

If

Jump:

 

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

Process

Write to PC

 

Decode

Read literal

Process

Write to PC