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Unit 4 MICRO CONTROLLER 8051 Functional block diagram - Instruction format and addressing modes Interrupt structure Timer I/O ports Serial communication. 4.1 Architecture of 8051 Signals and Operational Features A device that having microprocessor, memory and I/O signal lines on a single chip fabricated by using VLSI technique is called microcontroller. Comparison of Microprocessor and Microcontroller: MICROPROCESSOR MICROCONTROLLER

1. The functional blocks of a The microcontroller includes the microprocessor are ALU, functional blocks of a registers, timing and control microprocessor and in addition has unit. timer, parallel I/O port, serial I/O port, internal RAM and EPROM/EEPROM memory. Some controllers have even ADC and/or DAC.

PINS AND SIGNALS OF 8031/8051: The INTEL 805 F is an 8-bit microcontroller with 128 byte internal RAM and 4kb internal ROM. The INTEL 8031 is same, as 8051 except that it does not have internal ROM.

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The 8051 is a pin 40 pin IC available in Dual-In line package (DIP). Requires a single power supply of +5V. Its maximum internal clock frequency rating is 12 MHz.

Pin Diagram for 8051/8031 microcontroller Signals of 8031/8051 microcontroller

Alternate functions of port pins

Ports: (pin 1 to 8, pin 10 to 17, pin 21 to 28 and pin 32 to 39) The 8031/8051 microcontroller has 32 I/O pins and they are organized as four numbers of 8-bit parallel port. The ports are denoted as port-0, port-1, port-2 and port-3. Each port can be used as either 8-bit parallel port or 8 numbers of 1-bit ports. The ports behave as latches during output operation and behave as buffers during input operation.

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Port-1 can be used only for I/O operation When external memory is employed, the port-0 function as multiplexed low byte address or data lines, and port-2 function as high byte address lines. Therefore for accessing external memory the microcontroller uses 16-bit address and access the memory in bytes. Hence the addressable memory space is 64 kb (216 = 64kb). The 8031/8051 allows the external memory to be organized as two banks of 64 kb. One is program/code memory and the other is data memory. PSEN (low signal): pin 29 The signal PSEN (low) is used as read control/enable for program memory. RD (low signal) and WR (low signal): pin 17 and pin 16 The port pin P3.7 function as read control and the port pin P3.6 function as write control for data memory. When two external memory banks are not desirable, the PSEN (low) and RD (low) should be externally ANDed to provide a single read control signal. In such cases the controller will access a common memory space (of maximum capacity 64 kb) for program and data. ALE is used to demultiplex the low byte address or data using an external latch. EA (Low)/Vpp : pin 31 When the microcontroller access program from external memory, then this pin is low. ie. EA (low) is enabled. When the microcontroller access program from internal memory, then this pin is high. At that time this pin is used to supply programming voltage +12V to EPROM/ROM. XTAL 1 and XTAL2: pin 19 and pin18 The XTAL 1 and XTAL2 pins are provided for external quartz crystal connection, in order to generate the required clock for the microcontroller. The maximum frequency of quartz crystal that can be connected to 8031/8051 microcontroller is 12 MHz. RST (low): pin 9 The RST(low) signal is used to reset the microcontroller in order to bring the controller to a known state.

Contents of register after reset Interrupts: pin 12 to 15 The 803 1/8051 has five interrupts. In this two interrupts are external interrupt as INT0 (Low), INT1 (Low) and the remaining three are internal interrupts as timer-0, timer-1 and serial port.

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All interrupts are maskable and vectored interrupts.

Vector address and priority of interrupts ARCHITECTURE OF 8031/8051:

Architecture of 8031/8051 microcontroller Central processing Unit: 1. ALU: It performs the arithmetic operations such as addition, subtraction, multiplication and division. The unit can perform logical operations such as AND, OR; and Exclusive-OR, as well as rotate, clear, and complement. The ALU can also manipulate one bit as well as eight-bit data types.

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2.

3. 4.

Individual bits may be set, cleared, complemented, tested, and used in logic computation. Accumulator: It is an 8-bit register. It holds a data and receives the result of the arithmetic instructions. B register: An 8-bit general-purpose register. Program Status Word: Many instructions implicitly or explicitly affect (or are affected by) several status flags, which are grouped together to form the Program Status Word. It also used to select the memory bank.

5. Stack Pointer (SP): The stack pointer register is 8 bit wide. It is incremented before data is stored during PUSH and CALL instructions. After reset the value of SP is 07H. 6. Data Pointer (DPTR): The data pointer is a 16-bit register used to hold the 16-bit address of data memory. This can also be used as two numbers of 8-bit data pointer namely DPH and DPL. The 8-bit data pointers are used for accessing internal RAM and SFR. The 16-bit data pointer is used for accessing external data memory. The contents of data pointer are programmable using instructions. 7. Program Counter (PC): It is a 16 bit register.

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PC is used, as address pointer to access program instructions and it is automatically incremented after every byte of instruction fetch. I/O Devices: The 8051 has four numbers of 8-bit ports namely port-0, port- 1, port-2 and port-3. Each port has a latch and driver (or buffer). When external memory is employed the port-0 lines will function as multiplexed low byte address/data lines and port-2 lines will function as high byte address lines. Also the port pins P3.7 and P3.6 are used to output read and write control signals respectively. The port-1 is dedicated I/O port and does not have any alternate function. The ports are also mapped as internal memory in the controller and so they can be addressed as memory locations for 8-bit operation. Instruction Register (IR) & timing and control unit: The 8051 has 8-bit ALU, which performs arithmetic and logical operations on binary data. The A and B registers are used to hold the input data and the result of ALU operation. The controller will fetch the instructions one by one, starting from the address stored in PC and store in IR, which decodes the instructions and give information to timing and control unit. Using the information supplied by the IR unit the control signals necessary for internal and external operations are generated by the timing and control unit. Timer/Counter & Serial port: The 8031/8051 has two 16-bit programmable timer/counter namely timer-1 and timer 0. In the counter mode of operation they can count the number of high to low transitions of the signal applied to the timer pins. In timer mode of operation they can be independently programmed to work in any one of the four operation modes. They are called mode-0, mode-1, mode-2 and mode-3. In mode-0 the serial port can either receive or transmit at fixed baud rate. In mode-2 it can simultaneously transmit and receive at any one of the two selectable baud rate. In mode-1 and mode-3 it can work as full duplex serial port with variable baud rate, which is programmed using timer-1. Memory Organization: Since the size of address pointers are 16-bit they can address up to 216 = 64kb memory locations. A microcontroller based system requires both EPROM and RAM. The EPROM is required for permanent program and permanent data storage. The RAM is required for temporary data storage and stack. The 8031/8051 has 64kb program memory address space and 64kb data memory address space.

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The microcontroller can only read from program memory such as ROM/EPROM/ EEPROM and the signal PSEN (Low) is used as read control for reading program memory. The microcontroller can read and write with data memory RAM. It has separate read control signal RD(Low), and write control signal WR(Low) for reading and writing with data memory respectively. In 8031/8051 based system only memory mapped I/O is possible.

Program Memory: In 8031 there is no internal ROM/EPROM and so the entire 64 kb program memory space in the range 0000H to FFFFH is external. Therefore in 8031 based systems the pin EA(Low) is always tied low or grounded (0V). The 8051 has 4kb internal ROM which can be mapped to first 4kb address space of program memory. If EA(Low) pin is tied high or tied to VCC (+5V), then the internal 4kb ROM be mapped as program memory in the address range 0000H to 0FFFH and the external program memory 60kb will have the address range l000H to FFFFH If EA(Low) pin is tied low or grounded (0V), then the internal ROM is ignored or cannot be accessed. The entire 64 kb program memory address space is external with address range 0000H to FFFFH.

The 8051 Program Memory The PSEN (Low) signal is used to activate output enable signal to access the external ROM/EPROM, as shown.

Accessing External Program Memory The port 0 is used as a multiplexed address/bus. It gives lower order 8bit address in the initial T-cycle and later it is used as a data bus. The 8-bit address is latched using external latch and ALE signal generated by 8051. The port 2 provides the higher order 8-bit address.

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The lower part of program memory stores the vector addresses for various interrupt service routines. Each interrupt is assigned with a fixed location in program memory.

Interrupt/Vector location Data Memory: In 8031/8051 microcontroller the entire 64kb data memory space is external. The address range of external data memory is 0000H to FFFFH. Apart from external data memory the 8031/8051 has 256 bytes of internal data memory in which the first 128 bytes are called RAM and next 128 byte is called SFR. The address range of SFRs and internal RAM are 00H to FFH The MOVX instruction is used to access the external data memory. The internal data memory space for 8051 is divided into three blocks: Lower 128bytes, Upper 128 bytes and SFRs. The upper addresses and SFRs occupy the same block of address space, 80H through FFH, and they are physically separate entities. The upper address is accessible by indirect addressing only and SFRS are accessible by direct addressing only. Lower address space can be accessed either by direct addressing or by indirect addressing.

The 8051 Data Memory The circuit diagram for connecting external data memory is shown. The multiplexed address / data bus is provided by port 0.

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Port 2 gives the higher order address bus. The RD (Low) and WR (Low) signals from 8051 selects the memory read and memory write operation, respectively.

Accessing External Data Memory SPECIAL FUNCTION REGISTERS (SFR) : The SFRs include 21 internal registers listed in table. Each register of SFR has one byte address. Some of the registers are both byte and bit addressable (The registers whose address ends with 0H or 8H are bit addressable). The 8031/8051 has a separate 256 bytes internal RAM accessed by using 8-bit address. In this 256 bytes address space, first 128 byte addresses are allotted to internal RAM (00H to 7FH) and the next 128 bytes are allotted to SFR (80H to FFH). Using MOV instructions SFR can access.

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and B Registers: The A and B registers are called CPU registers. They are used to hold the data for most of the CPU (ALU) operations. The size of A and B registers are 8-bit. In ALU operation, the result is stored in A-register and so it is also known as accumulator. Data Pointer (DPTR): The data pointer is a 16-bit register used to hold the 16-bit address of data memory. This can also be used as two numbers of 8-bit data pointer namely DPH and DPL. The 8-bit data pointers are used for accessing internal RAM and SFR. The 16-bit data pointer is used for accessing external data memory. The contents of data pointer are programmable using instructions. Program Status Word (PSW): The PSW is also known as flag register. The flags are useful for the programmer to test the condition of the result and make decisions. The format of PSW of 8031/8051 microcontroller is shown in fig.

The PSW consists of four math flags and two register bank select bits. The math flags are Carry, Auxiliary Carry, and Overflow and Parity flags. The flags are altered after arithmetic and logical operations depending on the result. The carry flag is set when the result has a carry. When there is a carry from lower nibble to upper nibble the auxiliary carry is set. When the result has even parity, the parity flag is set. In certain mathematical operations if the size of the result exceeds the size of destination register then overflow flag is set. The register bank select bits RS1 and RS0 are used to select any one of the four register banks of the internal RAM. At any one time the microcontroller can work with (or access) only one register bank selected by these bits. The bank select bits are programmable and after reset the controller defaults to bank-0. The selection of register bank using the RS1 and RS0 bits are listed in table.

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Stack Pointer (SP): The stack pointer always holds the 8-bit address of the top of stack. The programmer can reserve any portion of RAM as stack. After a reset the stack pointer is initialized to 07H. The stack can be accessed using PUSH and POP instructions. During PUSH operation the stack pointer is automatically incremented by one and during POP operation the stack pointer is automatically decremented by one Power Control Register (PCON): The PCON register is used for power control and baud rate selection. It also consists of general-purpose user flags. The format of PCON is shown in figure. The controller can be driven to idle mode by setting IDL bit of PCON register. In idle mode the clock signal is stopped to CPU(ALU), but the clock signal is supplied to interrupt, timer and serial port blocks. The idle mode can be terminated either by an interrupt or by hardware reset. The power 12V can be reduced to 2V by setting PD bit. During power down mode the internal oscillator is stopped.

The power down mode can be terminated only by a hardware reset. The SMOD bit is used to decide the baud rate in serial port operating modes 1, 2 or 3. In mode 2, if SMOD =0, then the baud rate is 1/64 of oscillator frequency if SMOD = 1, then the baud rate is 1/32 of oscillator frequency. In mode 1 and 3, the baud rate depends on SMOD and timer-1 overflow rate. o The baud rate in mode 1 or 3 = (2 SMOD/32) x (Timer-1 Overflow Rate).

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The programmer, to indicate the status of certain events during program execution can use the general-purpose flag bits GF1 and GF.

Serial Data Buffer Register (SBUF): The SBUF register is used to hold the parallel data during transmission and reception. During serial reception, the serial data is received via RxD pin and converted to parallel data and stored in receive buffer. During serial transmission, the parallel data is stored in transmit buffer and then converted to serial data to transmit via TxD pin. The transmit and receive buffers are assigned the same internal address 99H but transmit buffer can be accessed only for write operation and receive buffer can be accessed only for read operation. When data is written to SBUF if goes to transmit buffer and when data is read from SBUF it comes from receive buffer. Timer Mode Control Register (TMOD): The TMOD register is used to select the operating mode and the timer/counter operation of the timers. The format of TMOD register is,

The lower four bits of TMOD register is used to control timer-0 and the upper four bits are used to control timer-1. The two timers can be independently program to operate in various modes. The TMOD register has two separate two bit field M0 and Ml to program the operating mode of timers. The operating modes of timers are mode-0, mode-1, mode-2 and mode-3. In all these operating modes the oscillator clock is divided by 12 and applied as input clock to timer.

Mode-0 1. In mode-0 the timer register is configured as 13-bit register. 2. For timer-1 the 8 bits of TH1 and lower 5 bits of TL1 are used to form 13-bit register. 3. For timer-0 the 8-bit of TH0 and lower 5 bits of TL0 are used to form 13-bit register. 4. The upper three bits of TL registers are ignored.

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5. For every clock input to timer the 13-bit timer register is incremented by one When the timer count rolls over from all 1s to all 0s, (i.e., 1 1111 1111 1111 to 0 0000 0000 0000) the timer interrupt flag in TCON register is set to one Mode-1 1. The mode-1 is same as mode-0 except the size of the timer register. In mode-1 the TH and TL registers are cascaded to form 16-bit timer register. Mode-2 1. In mode-2, the timers function as 8-bit timer with automatic reload feature. The TL register will function as 8-bit timer count register and the TH register will hold an initial count value. 2. When the timer is started, the initial value in TH is loaded to TL and for each clock input to timer the 8-bit timer count register is incremented by one. 3. When the timer count rolls over from all 1s to all 0s (i.e., 1111 1111 to 0000 0000), the timer interrupt flag in TCON register is set to one and the content of TH register is reloaded in TL register and the count process starts again from this initial value. Mode-3 1. In mode-3, the timer-0 is configured as two separate 8-bit timers and the timer-1 is stopped. 2. In mode-3 the TL0 will function as 8-bit timer controlled by standard timer-0 control bits and the TH0 will function as 8-bit timer controlled by timer-1 control bits. 3. While timer-0 is programmed in mode-3, the timer-0 can be programmed in mode-0, 1 or 2 and can be used for an application that does not require an interrupt. a. The C/T(Low) bit of TMOD register is used to program the counter or timer operation of the timer. When C/T bit is set to one, the timer will function as event counter. The C/T(Low) bit is programmed to zero for timer operation. b. The timer will run only if clock input is allowed. c. When GATE = 1, the clock input to timer is allowed only if the signal at pin is high and when GATE =0 the signal at INT (low) pin is ignored. Serial Port Control Register (SCON): The format of SCON register is shown.

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Mode 0: In this mode the serial port function as half duplex serial port with fixed baud rate. The 8- bit serial data is received and transmitted through RxD pin and the controller output the shift clock through TxD pin during reception and transmission. The baud rate is fixed at 1 / 12 of the oscillator frequency.

Mode 1: In this mode the serial port function as full duplex serial port with variable baud rate. In this mode one data consists of 10 bits, which includes one start bit, eight data bit and one stop bit. During reception the stop bit is stored as RB8 in SCON register. Baud rate in mode-1 depends on the value of SMOD bit in PCON register and the timer-1overflow rate. Mode 2: In this mode the serial port function as full duplex serial port with a baud rate of either 1/32 or 1/64 of the oscillator frequency. In this mode one data consists of 11 bits which includes one start bit, eight data bit, a programmable 9th data bit and one stop bit. During transmission the TB8 of SCON register is added as 9th data bit and during reception the 9th data bit is stored as RB8 in SCON register. The baud rate depends on the value of SMOD bit in PCON register. Mode 3: The mode-3 is same as mode-2, except the baud rate. In mode-3, the baud rate is variable. The baud rate depends on the value of SMOD bit in PCON register and the timer- 1 overflow rate. The serial mode bit-2 (SM2) has no effect in mode-0 and when programmed for mode-0, the SM2 should be equal to zero. In mode-1, SM2 is used to check a valid stop bit during reception. In mode-1, if SM2 = 1, then receive interrupt (RI) is activated only when a valid stop bit is received. In mode-2 and mode-3 the SM2 bit is used to enable multiprocessor communication.

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In multiprocessor communication the serial port of a number of microcontrollers can be connected to a common serial bus. One controller will act as a master and all other controller will act as slave. A unique 8-bit address is assigned to each slave and the SM2 bit in all the slaves is set to 1. When SM2 bit is one, the slaves will consider the received byte as address and when SM2 bit is zero the slaves will consider the received byte as data. For communication with a slave the master will first send as address byte and then a data byte. The master initiates communication with a slave by sending the address of the slave on the bus. All the slaves will receive the address byte. Since SM2 = 1 initially in all the slaves, the received byte will be considered as address and the slaves will verify whether the received address matches with assigned address. The slave whose assigned address matches with received address will clear its SM2 bit. Now SM2 bit of only one of the slave will be zero. Next the master will send a data byte which is also received by all the slave, but the data byte is accepted by the slave whose SM2 = 0 and so the receive interrupt is activated only in one of the slave whose SM2 = 0. After reading the received data from SBUF register, the SM2 bit of the slave should be set to one again to receive next data. The REN bit of SCON register can be used to enable or disable the serial reception. When REN = 1, the serial reception is enabled and when REN = 0, the serial reception is disabled. The bits TI and RI of SCON register are transmitting interrupt flag and receive interrupt flag respectively. The controller will set the TI bit during the transmission of stop bit of a data character in mode 1 to 3 and during the transmission 0 bit of a data character in mode-0. The controller will set the RI bit during the reception of stop bit of a data character in mode 1 to 3 and during the reception of 8th bit of a data character in mode- 0. Timer Control Register (TCON): 1. The TCON register consists of timer overflow flags, timer run control bits, external interrupt flags and external interrupt type control bits. 2. The format of TCON register is,

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When clock signal is applied, after reaching maximum value (i.e., the content of counter is all 1s), the content of counter will become zero (i.e., all 0s). This condition is called timer overflow and this is also the end of timing maintain by using the timer. The TCON register has a 1-bit flag, TF for each timer to indicate the timer overflow or end of timing. Whenever the timer/counter overflows, the TF flag is set to one. The TF flag is also used as an interrupt signal to initiate the execution of a subroutine. When the controller executes a subroutine, the TF flag is cleared. The TR bit is used to start/stop the timer/counter. When TR bit is set to one, the timer/ counter will start counting and continue the counting as long as TR bit is one. The timer/counter will stop counting when TR bit is cleared to zero. When a valid external interrupt signal is detected the IE flag is set to one. When the controller accepts the external interrupt and start processing it, the IE flag is cleared to zero. The IT = 1, when it recognize falling edge triggered external interrupt and IT = 0, when it recognize logic low level external interrupt. Interrupt Enable Register (IE): The IE register is used to enable/disable the interrupts of 8051. The interrupts are recognized by the controller only if they are enabled. The format of IE register is,

If EA = 0, then it disable all the five interrupts of 8051. If EA = 1, then it enable the interrupts. The EA bit is also called global enable. Interrupt Priority Register (IP): The 8051 has five interrupts. The normal priority of these interrupts from highest to lowest are external interrupt-0, Timer-0 interrupt, External interrupt- 1, Timer-1 interrupt and serial Port interrupt. The IP register can be programmed to make the priority of any of the interrupt as highest. When the priority bit of a particular bit is programmed as one then its priority will be highest. The format of IP register is,

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ADDRESSING MODES: Every instruction of a program has to operate on a data. The method of specifying the data to be operated by the instruction is called addressing. The 8031 has the following types of addressing. 1. Immediate Addressing 2. Direct Addressing 3. Register Addressing 4. Register Indirect Addressing 5. Implied Addressing 6. Relative Addressing 1. IMMEDIATE ADDRESSING: In immediate addressing mode, an 8/16 bit immediate data / constant is specified in the instruction itself. MOV A, #6CH:- Move the immediate data 6CH given in the instruction to A-register. (Accumulator) MOV DPTR, #0100H :- Load the immediate 16-bit constant given in the instruction in DPTR (Data pointer). This constant will be an address of data memory location. 2. DIRECT ADDRESSING : In direct addressing mode, the address of the data is directly specified in the instruction. The direct address can be the address of an internal data RAM location (00H to 7FH) or address of special function register (80H to FFH). MOV A, 07 H: - The address of R7 register of bank-0 is 07. This instruction will move the content of R7 register to A-register (Accumulator). 3. REGISTER ADDRESSING: In register addressing mode, the instruction will specify the name of register in which data available. MOV R2,A :- The content of A-register (accumulator) is moved to register R2. 4. REGISTER INDIRECT ADDRESSING: In this mode, the instruction specifies the name of the register in which the address of the data is available.

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The internal data RAM locations (00H to 7FH) can be addressed indirectly through registers R1 and R0. The external RAM can be addressed indirectly through DPTR.

MOV A, @R0:- The internal RAM Location R0 holds the address of data. The content of RAM location addressed by R0 is moved to A-register (Accumulator). 5. IMPLIED ADDRESSING: In implied addressing mode, the instruction itself specifies the data to be operated by the instruction. CPL C : - Complement carry flag. 6. RELATIVE ADDRESSING: In relative addressing mode, the instruction specifies the address relative to program counter. The instruction will carry an offset whose range is -l2810 to +l2710 . The offset is added to PC to generate 16-bit physical address. JC Offset: - If carry is one then the program control jump to an address obtained by adding the content of program counter and offset value in the instruction. INTERRUPTS: What Happens When an Interrupt Occurs? When an interrupt is triggered, the following actions are taken automatically by the The current Program Counter is saved on the stack, low-byte first. Interrupts of the same and lower priority are blocked. In the case of Timer and External interrupts, the corresponding interrupt flag is set. Program execution transfers to the corresponding interrupt handler vector address. The Interrupt Handler Routine executes. What Happens When an Interrupt Ends? An interrupt ends when the program executes the RETI (Return from Interrupt) instruction. When the RETI instruction is executed the following actions are taken by the microcontroller: Two bytes are popped off the stack into the Program Counter to restore normal program execution. Interrupt status is restored to its pre-interrupt status. Types of Interrupts: The 8051 provide 5 interrupt sources. They are, 1. External interrupt 0

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2. 3. 4. 5.

Timer interrupt 0 External interrupt 1 Timer interrupt 1 Serial port interrupt

Interrupt Destinations: The interrupts are stored in the lower addresses in program memory. Interrupt IEO TF0 IE1 TF1 SERIAL Address(HEX) 0003 000B 0013 001B 0023

Interrupt priority: The normal priority of the interrupts are, 1. External interrupt 0 2. Timer interrupt 0 3. External interrupt 1 4. Timer interrupt 1 5. Serial port interrupt The priority will be changed by the special function register IP and they are enabled by IE register. Interrupt Enable Register (IE): The IE register is used to enable/disable the interrupts of 8051. The interrupts are recognized by the controller only if they are enabled. The format of IE register is,

If EA = 0, then it disable all the five interrupts of 8051. If EA = 1, then it enable the interrupts. The EA bit is also called global enable. Interrupt Priority Register (IP): The 8051 has five interrupts.

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The normal priority of these interrupts from highest to lowest are external interrupt-0, Timer-0 interrupt, External interrupt- 1, Timer-1 interrupt and serial Port interrupt. The IP register can be programmed to make the priority of any of the interrupt as highest. When the priority bit of a particular bit is programmed as one then its priority will be highest. The format of IP register is,

REC, Dept of EEE, EC1362 p & c subject notes