Documente Academic
Documente Profesional
Documente Cultură
Revision History
Revision 0.10 1.00 1.01 Date 2008/07/30 2009/11/13 2010/03/01 Description Preliminary release. 1. Added AX88782/AX88613 EEPROM related information. 1. Added Section 3-2-6 about how to configure Non-802.1Q Port-Based VLAN Entry. 2. Added some FAQs about AX88613 EEPROM in Section 4-4, 4-5.
Contents
1. Introduction ........................................................................................... 5 2. EEPROM Device Selection .................................................................. 6 3. EEPROM Data Related Information .................................................. 7
3-1. EEPROM Data Format ..................................................................................... 7 3-2. EEPROM Write Command Examples .............................................................. 8 3-2-1. Configure Port 0/Port 1 MAC Addresses and Enable PHY0/PHY1 .......... 8 3-2-2. Indirectly Write PHY0/PHY1 Registers through MDIO Interface ............. 9 3-2-3. Set PCI Vendor/Device and Sub-Vendor/Sub-Device IDs (for AX88742 only) ............................................................................................................ 9 3-2-4. Configure L2 Routing Table for Source Port 0/Port 1............................. 10 3-2-5. Configure 802.1Q VLAN Entry ................................................................ 11 3-2-6. Configure Non-802.1Q Port-Based VLAN Entry ..................................... 12 3-2-7. Configure 802.1P QoS Mapping Table for Port 0/1/2 ............................. 13 3-2-8. Configure IGMP Multicast IP Group Table Entry .................................. 14 3-2-9. Configure RX Rate Limit Function ........................................................... 15 3-2-10. Configure TX Rate Limit Function ........................................................... 16
Appendix 1. AX88742 EEPROM Reference Setting ........................... 19 Appendix 2. AX88783/AX88782 EEPROM Reference Setting .......... 20 Appendix 3. AX88613 EEPROM Reference Setting ........................... 21
A3-1. Port 2 in MII Mode with External PHY (default setting for demo board) ..... 21 A3-2. Port 2 in Reverse MII Mode ........................................................................... 24 A3-3. Port 2 in RMII Mode with External PHY ....................................................... 26 A3-4. Port 2 in Reverse RMII Mode......................................................................... 29
Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. EEPROM Device Selection Table (PD: Pull-Down, PU: Pull-Up) .................................................................. 6 EEPROM Data Format ..................................................................................................................................... 7 AX88742 EEPROM Reference Setting .......................................................................................................... 19 AX88783/AX88782 EEPROM Reference Setting .......................................................................................... 20 AX88613 EEPROM Reference Setting (Port 2 in MII mode with external PHY) ......................................... 23 AX88613 EEPROM Reference Setting (Port 2 in Rev-MII mode) ................................................................ 25 AX88613 EEPROM Reference Setting (Port 2 in RMII mode with external PHY) ....................................... 28 AX88613 EEPROM Reference Setting (Port 2 in Rev-RMII mode) .............................................................. 31
1. Introduction
ASIX Electronics provides some multi-port embedded Ethernet controllers that support different processor host interfaces commonly used in embedded system applications. The supported processor host interfaces are PCI bus, non-PCI bus (SRAM-like) and Ethernet MACs MII/RMII bus. The following URL provides detailed online resource of ASIX Electronics multi-port embedded Ethernet solutions: (Refer to http://www.asix.com.tw/products.php?op=ProductList&PLine=65). This user guide applies specifically to the following multi-port Ethernet controllers, namely, AX88742, AX88783, AX88782 and AX88613. 2-Port PCI Fast Ethernet AX88742 -- 32-bit PCI 2-Port 10/100M Fast Ethernet Controller 2-Port Non-PCI Fast Ethernet AX88783 -- Non-PCI 8/16/32-bit 2-Port 10/100M Fast Ethernet Controller AX88782 -- Non-PCI 8/16-bit 2-Port 10/100M Fast Ethernet Controller 2-Port MII/RMII Fast Ethernet AX88613 -- 3-Port 10/100M Fast Ethernet Switch Controller This user guide provides the information about the EEPROM configuration of ASIX Electronics multi-port embedded Ethernet controllers.
SK PD PD PU PU
CS PD PU PD PU
Note: 1. The multi-port embedded Ethernet controllers can only support 8-bit mode 93C46, 93C56 and 93C66 EEPROM. Please make sure you select a correct EEPROM type on your target applications. 2. The EEPROM is optional for AX88783/AX88782 if the MAC addresses of Port 0 and Port 1 can be stored on the Flash memory of your embedded system. In this case, the AX88783/AX88782 driver should read the MAC addresses of Port 0 and Port 1 from the Flash memory and then configure the related Port 0/Port 1 MAC address registers for normal operation. 3. The EEPROM is optional for AX88742 if the MAC addresses of Port 0 and Port 1 can be stored on the Flash memory of your embedded system and the AX88742 PCI Vendor ID and Device ID of your application uses the AX88742 default Vendor ID (0x125B) and Device ID (0x7420). In this case, the AX88742 driver should read the MAC addresses of Port 0 and Port 1 from the Flash memory and then configure the related Port 0/Port 1 MAC address registers for normal operation. 4. The EEPROM is optional for AX88613 if your MCU supports the SPI interface and the MAC addresses of Port 0 and Port 1 can be stored on the Flash memory of your embedded system. In this case, your MCU firmware can read the MAC addresses of Port 0 and Port 1 from the Flash memory and then configure proper AX88613 registers through the SPI interface for normal operation. Please refer to Section 4.4 of AX88613 datasheet for more details about the AX88613 SPI Data Write command format.
Address [9:2]: MAC register address (Address[9:2] * 4) Data [31:24], Data [23:16], Data [15:8], Data [7:0]: MAC register written 32-bit value The EEPROM Write Command contains the MAC register address and four bytes of data because the MAC registers of the multi-port embedded Ethernet controllers are 32-bit wide. The Address [9:2] value 0x00 and 0xFF are reserved. If the Address [9:2] value is 0x00 or 0xFF, the multi-port embedded Ethernet controllers will ignore this write command and continue to run next write command. The EEPROM Write End Command is defined as Address [9:2] = 0x00 and Data [31:0] = 0x84149435. The EEPROM used space should be terminated by an EEPROM Write End Command. When the multi-port embedded Ethernet controllers decode this Write End Command, the multi-port embedded Ethernet controllers will stop the EEPROM auto-loading operation. If the Write End Command is not defined on the last field of EEPROM used space, the multi-port embedded Ethernet controllers will read through all 1K (93C46), 2K (93C56) or 4K (93C66) pre-defined EEPROM address space. In this case, the rest of EEPROM unused space should be filled in 00 or FF to avoid to run the wrong EEPROM write commands due to the unexpected data in the EEPROM unused space.
EEPROM Address 0 1 2 3 4 5 6 7 8 9 : : : EEPROM Contents Address [9:2] (1St Write Command) Data [31:24] Data [23:16] Data [15:8] Data [7:0] Address [9:2] (2nd Write Command) Data [31:24] Data [23:16] Data [15:8] Data [7:0] : : :
EEPROM Data Format
Table 2.
8D
9C
12 Port0 MAC Add[7:0] CC DD EE Port1 MAC Port1 MAC Port1 MAC Add[23:16] Add[31:24] Add[39:32]
00
00
9D
00
00
01
11 01 Port 1 PHY ID
50
33
00
00
84
14
0F
05 Data[15:8]
E1 Data[7:0]
00
84
14
94
35
3-2-3.
Addr[9:2] BD
BE
74
20
12
5B
00
84
14
94
35
07
06
07
00
24
00
07
FF
CF
25
00
04
14
0B
26
00
04
0C
0D
00
84
14
94
35
08
03
65
00
00
00
84
14
94
35
81
00
00
FA
50
91
00
00
FA
50
A1
00
00
FA
50
00
84
14
94
35
54
91
02
03
04
55
B5
06
07
08
56
DF
0A
0B
0C
00
84
14
94
35
90
00
01
01
99
A0
00
01
20
00
87
FF
FF
00
01
97
FF
FF
00
01
A7
FF
FF
00
01
00
84
14
94
35
90
00
02
01
99
A0
00
02
20
00
87
00
01
FF
FF
97
00
01
FF
FF
A7
00
01
FF
FF
00
84
14
94
35
4. EEPROM FAQs
4-1. Do we need to register our own PCI Vendor ID/Device ID and Subsystem Vendor ID/Subsystem Device ID for AX88742 applications?
The Vendor ID and Device ID registers identify the device, and are commonly called the PCI ID. The 16-bit vendor ID is allocated by the PCI SIG (http://www.pcisig.com/). The 16-bit device ID is then assigned by the vendor. There is an ongoing project to collect all known Vendor and Device IDs. (See http://www.pcidatabase.com/ for more details.) The Subsystem Vendor ID and the Subsystem Device ID further identify the device. The Vendor ID is that of the chip manufacturer, and the Subsystem Vendor ID is that of the card manufacturer. The Subsystem Device ID is assigned by the subsystem vendor, but is assigned from the same number space as the Device ID. The answer to above question really depends on the real requirements of your AX88742 target applications. If your AX88742 application doesnt have special requirements and can work with the standard AX88742 drivers, you can consider using ASIXs AX88742 default PCI Vendor ID (125Bh)/Device ID (7420h) and Subsystem Vendor ID (125Bh)/Subsystem Device ID (7420h) directly.
4-2. Do I have to assign two unique MAC addresses for Port 0 and Port 1 of every ASIX Multi-Port Ethernet Controller based devices?
Yes, every Ethernet device must have a unique MAC address. Users should assign two unique MAC addresses in the EEPROM for Port 0 and Port 1 of every ASIX Multi-Port Ethernet Controller based devices. You should refer to Section 4-2 to register a block of MAC addresses for your company.
ASIX Multi-Port Ethernet Controller EEPROM/Manufacture User Guide 4-4. Is the EEPROM device required for AX88613 applications?
The AX88613 supports 8-bit mode 93C46/93C56/93C66 EEPROM. The EEPROM is optional for AX88613 if the MCU on your target platform supports the SPI interface to configure AX88613 registers through AX88613 SPI interface directly. Otherwise, you should implement the EEPROM on your AX88613 applications to configure AX88613 to reach the specific requirements (such as routing table, VLAN, etc.) of your AX88613 applications.
8C Reg:230
C6 00 12 38 Port0 MAC Port0 MAC Port0 MAC Port0 MAC Add[23:16] Add[31:24] Add[39:32] Add[47:40]
8D Reg:234 9C Reg:270
00 Port0 MAC Add[7:0] C6 00 12 Port1 MAC Port1 MAC Port1 MAC Add[23:16] Add[31:24] Add[39:32]
00
00
9D Reg:274 BD Reg:2F4
00
00
74
20
BE Reg:2F8
74
20
12
5B
00
84
14
Table 3.
94
35
8C Reg:230
C6 00 12 38 Port0 MAC Port0 MAC Port0 MAC Port0 MAC Add[23:16] Add[31:24] Add[39:32] Add[47:40]
8D Reg:234 9C Reg:270
00 Port0 MAC Add[7:0] C6 00 12 Port1 MAC Port1 MAC Port1 MAC Add[23:16] Add[31:24] Add[39:32]
00
00
9D Reg:274 00
00
00
84
14
Table 4.
A3-1. Port 2 in MII Mode with External PHY (default setting for demo board)
The following is an example of the AX88613 EEPROM setting when the AX88613 Port 2 was set to MII mode with external PHY. The EEPROM of AX88613 demo board is set to MII mode by default. AX88613 Port 0 & Port 1 in internal PHY mode, Port 2 in MII mode with external PHY
Addr[9:2] 01 Reg:004 Data[31:24] Data[23:16] Data[15:8] 11 01 10 Data[7:0] 01 EEPROM Write Command
37 Reg:0DC
03
00
01
04
7C Reg:1F0
40
0C
00
00
00 52 Reg:148
00 07
00 FF
00 FF
00 FF
Delay about 1.3 second (0x07FFFFFF 134,217,727 * 10ns = 1.3 sec) to wait for PHY initialization completion
Write 0x07FFFFFF to MAC register address 0x148 (i.e. 0x52* 4 = 0x148)
Note: AX88613 BLCR register (address 0x148) works as a delay time counter (in 10ns unit) during auto-loading EEPROM operation. Users can fine tune this delay time counter to reach the real requirements on your AX88613 target applications.
Write PHY0 ANAR PHY register through MDIO Read/Write Control register
Write 0x900405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: The default PHY address of PHY 0 is 0x10 Delay for MDIO process (No operation)
00 0F Reg:03C
00 91
00 04
00 05
00 E1
Write PHY1 ANAR PHY register through MDIO Read/Write Control register
Write 0x910405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: The default PHY address of PHY 1 is 0x11 Delay for MDIO process (No operation)
00 0F Reg:03C
00 04
00 05
00 E1
Write Port 2 external PHY ANAR PHY register through MDIO Read/Write Control register
Write 0x950405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: Assume the PHY address of Port 2 external PHY is 0x15 Delay for MDIO process (No operation)
00 0F Reg:03C
00 90
00 00
00 33
00 00
00 0F Reg:03C
00 91
00 00
00 33
00 00
00
00
00
00
00
Restart Port 2 external PHY autonegotiation function through MDIO Read/Write Control register
Write 0x95003300 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Enable auto-polling function on internal PHY0/PHY1 and Port 2 external PHY Write 0x77151110 to MAC register address 0x140 (i.e. 0x50 * 4 = 0x140) The EEPROM Write End Command
50 Reg:140
77
11
10
00
84
Table 5.
94
35
AX88613 EEPROM Reference Setting (Port 2 in MII mode with external PHY)
ASIX Multi-Port Ethernet Controller EEPROM/Manufacture User Guide A3-2. Port 2 in Reverse MII Mode
The following is an example of the AX88613 EEPROM setting when the AX88613 Port 2 was set to Reverse MII mode. AX88613 Port 0 & Port 1 in internal PHY mode, Port 2 in Reverse MII mode
Addr[9:2] 01 Reg:004 Data[31:24] Data[23:16] Data[15:8] 11 01 10 Data[7:0] 01 EEPROM Write Command
37 Reg:0DC
03
00
01
04
7C Reg:1F0
04
08
00
00
00 52 Reg:148
00 07
00 FF
00 FF
00 FF
Delay about 1.3 second (0x07FFFFFF 134,217,727 * 10ns = 1.3 sec) to wait for PHY initialization completion
Write 0x07FFFFFF to MAC register address 0x148 (i.e. 0x52* 4 = 0x148)
0F Reg:03C
90
04
05
E1
Note: AX88613 BLCR register (address 0x148) works as a delay time counter (in 10ns unit) during auto-loading EEPROM operation. Users can fine tune this delay time counter to reach the real requirements on your AX88613 target applications. Write PHY0 ANAR PHY register through MDIO Read/Write Control register
Write 0x900405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: The default PHY address of PHY 0 is 0x10 Delay for MDIO process (No operation)
00
00
00
00
00
Write PHY1 ANAR PHY register through MDIO Read/Write Control register
Write 0x910405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: The default PHY address of PHY 1 is 0x11 Delay for MDIO process (No operation)
00 0F Reg:03C
00 90
00 00
00 33
00 00
00 0F Reg:03C
00 91
00 00
00 33
00 00
00 68 Reg:1A0
00 C0
00 00
00 00
00 12
A0 Reg:280
00
00
01
99
50 Reg:140
33
00
11
10
00
84
Table 6.
14
94
35
ASIX Multi-Port Ethernet Controller EEPROM/Manufacture User Guide A3-3. Port 2 in RMII Mode with External PHY
The following is an example of the AX88613 EEPROM setting when the AX88613 Port 2 was set to RMII mode with external PHY. AX88613 Port 0 & Port 1 in internal PHY mode, Port 2 in RMII mode with external PHY
Addr[9:2] 01 Reg:004 Data[31:24] Data[23:16] Data[15:8] 11 01 10 Data[7:0] 01 EEPROM Write Command
37 Reg:0DC
03
00
01
04
7C Reg:1F0
40
08
00
04
7C Reg:1F0
40
08
40
44
Note: Please set bit14 (CLK50_EN) when your AX88613 application needs to output 50MHz clock signals from AX88613 P2_REFCLKO pin.
00 52 Reg:148 00 07 00 FF 00 FF 00 FF Delay (No operation)
Delay about 1.3 second (0x07FFFFFF 134,217,727 * 10ns = 1.3 sec) to wait for PHY initialization completion
Write 0x07FFFFFF to MAC register address 0x148 (i.e. 0x52* 4 = 0x148)
Note: AX88613 BLCR register (address 0x148) works as a delay time counter (in 10ns unit) during auto-loading EEPROM operation. Users can fine tune this delay time counter to reach the real requirements on your AX88613 target applications.
26 Copyright (C) 2008-2010 Reserved by ASIX Electronics Corporation
Write PHY0 ANAR PHY register through MDIO Read/Write Control register
Write 0x900405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: The default PHY address of PHY 0 is 0x10 Delay for MDIO process (No operation)
00 0F Reg:03C
00 91
00 04
00 05
00 E1
Write PHY1 ANAR PHY register through MDIO Read/Write Control register
Write 0x910405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: The default PHY address of PHY 1 is 0x11 Delay for MDIO process (No operation)
00 0F Reg:03C
00 04
00 05
00 E1
Write Port 2 external PHY ANAR PHY register through MDIO Read/Write Control register
Write 0x950405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: Assume the PHY address of Port 2 external PHY is 0x15 Delay for MDIO process (No operation)
00 0F Reg:03C
00 90
00 00
00 33
00 00
00 0F Reg:03C
00 91
00 00
00 33
00 00
00
00
00
00
00
Restart Port 2 external PHY autonegotiation function through MDIO Read/Write Control register
Write 0x95003300 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Enable auto-polling function on internal PHY0/PHY1 and Port 2 external PHY Write 0x77151110 to MAC register address 0x140 (i.e. 0x50 * 4 = 0x140) The EEPROM Write End Command
50 Reg:140
77
11
10
00
84
Table 7.
94
35
AX88613 EEPROM Reference Setting (Port 2 in RMII mode with external PHY)
ASIX Multi-Port Ethernet Controller EEPROM/Manufacture User Guide A3-4. Port 2 in Reverse RMII Mode
The following is an example of the AX88613 EEPROM setting when the AX88613 Port 2 was set to Reverse RMII mode. AX88613 Port 0 & Port 1 in internal PHY mode, Port 2 in Reverse RMII mode
Addr[9:2] 01 Reg:004 Data[31:24] Data[23:16] Data[15:8] 11 01 10 Data[7:0] 01 EEPROM Write Command
37 Reg:0DC
03
00
01
04
7C Reg:1F0
00
08
00
04
7C Reg:1F0
00
08
40
44
Note: Please set bit14 (CLK50_EN) when your AX88613 application needs to output 50MHz clock signals from AX88613 P2_REFCLKO pin.
00 52 Reg:148 00 07 00 FF 00 FF 00 FF Delay (No operation)
Delay about 1.3 second (0x07FFFFFF 134,217,727 * 10ns = 1.3 sec) to wait for PHY initialization completion
Write 0x07FFFFFF to MAC register address 0x148 (i.e. 0x52* 4 = 0x148)
Note: AX88613 BLCR register (address 0x148) works as a delay time counter (in 10ns unit) during auto-loading EEPROM operation. Users can fine tune this delay time counter to reach the real requirements on your AX88613 target applications.
29 Copyright (C) 2008-2010 Reserved by ASIX Electronics Corporation
Write PHY0 ANAR PHY register through MDIO Read/Write Control register
Write 0x900405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: The default PHY address of PHY 0 is 0x10 Delay for MDIO process (No operation)
00 0F Reg:03C
00 91
00 04
00 05
00 E1
Write PHY1 ANAR PHY register through MDIO Read/Write Control register
Write 0x910405E1 to MAC register address 0x03C (i.e. 0x0F* 4 = 0x03C) Note: The default PHY address of PHY 1 is 0x11 Delay for MDIO process (No operation)
00 0F Reg:03C
00 90
00 00
00 33
00 00
00 0F Reg:03C
00 91
00 00
00 33
00 00
00 68 Reg:1A0
00 C0
00 00
00 00
00 12
A0 Reg:280
00
00
01
99
00
84
Table 8.
14
94
35
4F, No.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan, R.O.C. TEL: +886-3-5799500 FAX: +886-3-5799558 Email: support@asix.com.tw Web: http://www.asix.com.tw