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of which can provide data encryption and decryption using only an encryption primitive. It is hoped that this design will open up new opportunities for the AES in resource-sensitive applications, where it was not considered previously. ACKNOWLEDGMENT The authors would like to thank J. Spreutels and E. Deumens of the Interuniversity Microelectronics Centre (IMEC), and L. Wong and M. Wilmott at the Microelectronic Support Unit, Rutherford-Appleton Laboratory, Chilton, U.K., for assistance with the design ow and foundry service.

A Chip-Area Efcient Voltage Regulator for VLSI Systems

Ka Nang Leung, Yuan Yen Mai, and Philip K. T. Mok

AbstractThis paper presents an error amplier structure to improve load regulation of low-voltage low-dropout regulators. The proposed error amplier has ultrawide swing to extend the high-gain region so that the size of power transistor can be reduced. Experimental results show that the required power transistor size is reduced by 25% to achieve similar performance in load regulation. Moreover, extra power consumption and increase of silicon area are not signicant. Index TermsLoad regulation, low-dropout regulator.

I. INTRODUCTION

REFERENCES
[1] Nat. Inst. Standards Technol. (NIST), Federal Information Processing Standards (FIPS) Publication 197, Advanced Encryption Standard, Nov. 2001. [2] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, A compact Rijndael hardware architecture with S-box optimization, in Proc. ASIACRYPT, Gold Coast, Qld., Australia, Dec. 2001, vol. 2248, Lecturer Notes in Computer Science, pp. 239254. [3] T. Good and M. Benaissa, Very small FPGA application-specic instruction processor for AES, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 7, pp. 14771486, Jul. 2006. [4] M. Feldhofer, J. Wolkerstorfer, and V. Rijmen, AES implementation on a grain of sand, Proc. Inst. Electr. Eng. Inf. Security, vol. 1, pp. 1320, 2005. [5] NIST, Recommendation for block cipher modes of operation, Special Publication SP-800-38A, 2001. [Online]. Available: http://csrc.nist.gov/publications/PubsSPs.html [6] D. Whiting, R. Housley, and N. Ferguson, Counter With CBC-MAC (CCM), Jun. 2002. [Online]. Available: http://csrc.nist.gov/ groups/ST/toolkit/BCM/documents/proposedmodes/ccm/ccm.pdf [7] V. Rijmen, Efcient Implementation of the Rijndael S-Box, 2000. [Online]. Available: http://www.iaik.tu-graz.ac.at/research/krypto/ AES/old/~rijmen/rijndael/sbox.pdf [8] D. Canright, A very compact S-box for AES, in Proc. CHES, Edinburgh, U.K., 2005, vol. 3659, LNCS, pp. 441456. [9] C. Paar, Efcient VLSI architectures for bit-parallel computation in Galois elds,, Ph.D. dissertation, Inst. Exp. Math., Univ. Essen, Essen, Germany, Jun. 1994. [10] T. Good and M. Benaissa, ASIC Hardware Performance. Berlin, Germany: Springer-Verlag, 2008, vol. 4986, Lecture Notes in Computer Science State-of-the-Art-Survey, pp. 267293. [11] J.-P. Kaps and B. Sunar, Energy comparison of AES and SHA-1 for ubiquitous computing, in Proc. Embedded Ubiquitous Comput. (EUC), Seoul, Korea, Aug. 2006, pp. 372381. [12] H. Kuo, I. Verbauwhede, and P. Schaumont, A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V 0.18 um CMOS technology, in Proc. CICC, Orlando, FL, 2002, pp. 147150. [13] S.-F. Hsaio, M.-C. Chen, and C.-S. Tu, Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 615626, Mar. 2006. [14] S.-Y. Lin and C.-T. Huang, A high-throughput low-power AES cipher for network applications, in Proc. ASP-DAC, Yokohama, Japan, Jan. 2007, pp. 595600.

Integrated power management is a pivotal issue in VLSI systems. In particular, low-dropout voltage regulator (LDO) can achieve local on-chip regulation for VLSI systems [1]. This motivates recent LDO researches focusing on lower minimum supply voltage [2], faster dynamic response [3], higher stability [4], [5], higher steady-state accuracy [6], and less silicon consumption. In general, all LDO specications constrain each other [2][6]. It is difcult to improve all of them simultaneously. Load regulation ( VOUT = IOUT ) of an LDO shown in Fig. 1 is determined by the low-frequency loop gain (LO ) [2][5]. LO depends on both the gain of the error amplier (AEA ) and the gain of the power transistor (APT ). From Fig. 1, VOUT is given by

RF 1 RF 1 LO 1 + LO 1 + RF 2 VREF  1 + RF 2 VREF (1) where LO = AEA APT RF 2 =(RF 1 + RF 2 ). From (1), VOUT is independent of input voltage (VIN ), and is set by RF 1 =RF 2 and VREF when LO  1. A higher loop gain enables a better load regulation, VOUT =

but it cannot be increased by just increasing the gain of the error amplier due to stability problem [7]. Therefore, a low-frequency zero is generated in [7] by inserting a large value RC network in the error amplier structure. Although the LDO stability and the load regulation are both enhanced, the large-signal response is limited due to the added large on-chip capacitance inside the low-power error amplier. For example, when an error amplier has a bias current of 2  , a 5-pF on-chip capacitance to create a zero for compensation seriously degrades the response time in the submicrosecond range. Therefore, a single-sided gain-retained method to extend the highgain region of the error amplier and retain the voltage gain at large load current is proposed in this paper. The major contribution of the

Manuscript received April 06, 2008; revised June 25, 2008. First published January 12, 2010; current version published November 24, 2010. This work was supported by the Research Grant Council of Hong Kong Special Administrative Region (SAR) Government under Project HKUST 617707. K. N. Leung was with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong. He is currently with the Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong (e-mail: knleung@ee.cuhk. edu.hk). Y. Y. Mai was with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong. He is currently with Supertex, Inc., Kowloon, Hong Kong (e-mail: eemyy@ece. ust.hk). P. K. T. Mok is with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong (e-mail: eemok@ece.ust.hk). Digital Object Identier 10.1109/TVLSI.2009.2026176

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Fig. 1. Structure of an LDO.

Fig. 3. Plot of size ratio versus

at different

current. Referring to Fig. 1, the output current is therefore approximated by (the approximation is based on the fact that VSG 0jVTHP j  VIN 0 VOUT in low-voltage LDO design)

IOUT

 p COX

W L

(VSG 0 jVTHP j) (VIN 0 VOUT ) :

(2)

Fig. 2. Simulated load regulations of LDO using the same amplier with different aspect ratios of power transistor.

W=L

The power transistor size is determined at the maximum IOUT (the worst case). The ideal maximum VSG for providing the maximum IOUT is VIN . As a result, the ideal aspect ratio (W=L)IDEAL of the power transistor has a relation given by

proposed idea is to improve the load regulation without adding any RC components to the LDO. II. RELATIONSHIP BETWEEN LOAD REGULATION AND OUTPUT SWING OF AN ERROR AMPLIFIER Fig. 2 shows simulations of the load regulation of an LDO with different power-transistor sizes providing a preset VOUT = 1:3 V. Fig. 2 shows that the load regulation is poor at high IOUT (denoted as critical region in Fig. 2). As depicted in Fig. 2, larger aspect ratio can enhance load regulation. There is clearly a tradeoff between the load regulation and the chip area. This phenomenon can be explained by the VSG of the power transistor at different IOUT . The error amplier operates in the low-gain region due to the high VSG of the power transistor to deliver more IOUT . Thus, a larger aspect ratio of the power transistor helps to improve the load regulation, since relatively lower VSG is needed for providing equal amount of IOUT . However, the gain reduction cannot be solved by a high-gain cascade or cascade error amplier since LDO is unstable when the loop gain is too high [5]. Therefore, the gain of the error amplier is needed to be retained throughout the whole range of IOUT . From this analysis, the design of the output stage of the error amplier has a substantial impact on the required size of the power transistor for the improvement of load regulation, especially when the supply voltage of the VLSI systems is low. III. POWER TRANSISTOR SIZE REQUIREMENT The power transistor of an LDO generally operates in the linear region when the sourcegate voltage is large for the maximum output

(3) However, the effective VSG is reduced by the nonzero lower output swing (dened as VOL ) of the error amplier. The actual required aspect ratio (W=L)ACT of the power transistor is

W IOUT(MAX)  p COX (V 0 jVTHP j) (VIN 0 VOUT ) : L IDEAL IN

(4) Based on (3) and (4), when providing equal maximum IOUT , the size relationship due to the nonzero VOL is given by

W IOUT(MAX)  p COX (V 0 V 0jVTHPj) (VIN 0 VOUT): L ACT IN OL

(W=L)ACT VOL (W=L)IDEAL  1 + VIN 0 jVTHPj 0 VOL :

(5)

A simple analysis can be done by considering an LDO design. Suppose jVTHP j = 0:8 V, then the required size ratio given in (5) as a function of VOL at different VIN (1.5, 2, and 3 V) is shown in Fig. 3. The reference size ratio is 1, which indicates the ideal transistor size when VOL = 0 V. Fig. 3 shows that the required size ratio increases as VOL increases. The increasing size ratio becomes more serious when the LDO operates at low input voltage. For example, when VIN = 1:5 V, the size ratios are about 1.2 and 1.4 for VOL = 0:1 and 0.2 V, respectively. By considering an LDO implemented in a 0.35-m CMOS technology, suppose that the power transistor size is 14 000 m/0.35 m when VOL = 0:2V, then the required size will be signicantly reduced to 12 000 m/0.35 m when VOL = 0:1 V. It can be concluded that there is substantial size reduction of the power transistor when the VOL of the error amplier can be reduced. Smaller transistor size enables faster transient response since slew-rate limit at the gate of the power transistor is relatively not serious [2].

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Fig. 5. Noncascode structure and gain-retained structure at high I tion. (a) Gain retained. (b) Noncascode. (c) Three possible cases. Fig. 4. Proposed error-amplier structure.

condi-

IV. PROPOSED SINGLE-SIDED GAIN-RETAINED METHOD The key requirements of the error amplier are wide output swing to maximize the VSG of the power transistor and simple frequency response to ease frequency compensation of the LDO. A current-mirror amplier is a good choice. It is applied to the LDO in Fig. 1. The proposed error amplier structure in Fig. 4 is a modied current-mirror amplier. N1 , N2 , N3 , N4 , and the auxiliary amplier with a voltage gain of A form the proposed single-sided ultrawide-swing gain-retained output stage. Both N1 and N2 are designed to operate in the linear region. This can be done by the transistor sizing of N2 and N4 to dene VX . In general, when the body effect of N4 is taken into account, W=L N4 > W=L N2 W=L N2 is needed to make N2 operate in the saturation region. Therefore, the condition that makes N2 operate in the linear region is suggested to be

than RONC [8]. Therefore, the gain is retained and mainly dened by P1 . Case II) ( 0 : Saturation) versus ( 1 : Linear, 2 : Linear): When VDS and rds a MOSFET operates in the linear region, gm  VGS VTH VDS 01 , where  COX W=L . For the singlesided gain-retained structure, both 1 and 2 operate in the linear region. Thus

[(

0 )]

M = M

( M

M =

M M M M M ) ! 6(

ROGR

 rds1Agm2rds2 DS2 = 1 (VGS1 0 VTH 0 VAV : DS1 )(VGS2 0 VTH 0 VDS2 )

5(

(7)

Since both

M1 and M2 operate in the linear region, we have VGS1 0 VTH  VDS1(sat) > VDS1
VGS2 ROGR

(8)

and

2 M M

W L N2

W W <5 : L N4 L N2

(6)

0 VTH  VDS2(sat) > VDS2:

(9)

Therefore, (7) can be approximated to

Smaller size of N4 can lower VX and extend the lower swing. However, it is suggested that the size of N4 is at least two times larger VX is therefore conthan that of N2 due to design reliability. VY tinuously regulated by the auxiliary amplier. The key purpose of the proposed structure is to retain the gain of the error amplier when VOEA is low, but not to increase the voltage gain. Therefore, as shown in Fig. 4, it is necessary to make sure that the output resistance achieved by the proposed structure is sufciently large, so that the effective output resistance of the error amplier will be mainly controlled by P1 . The voltage gain of the error amplier is expected to be about gm(A1) rds(P1) . However, the operation of the proposed structure is dynamically affected by IOUT . An analysis is needed to show that the proposed structure extends the lower output swing when compare to the noncascode structure. The analysis is done by using Fig. 5. There are three possible cases, and they are tabulated in Fig. 5(c). The output resistances of the proposed noncascode and gain-retained structures are RONC and ROGR , respectively. The voltage gain of the error amplier using the proposed gain-retained structure is preserved when VOEA (Fig. 4) decreases, provided that ROGR > RONC in all the three cases. Case I) ( 0 : Saturation) versus ( 1 : Linear, 2 : Saturation): When 2 operates in the saturation region, ROGR is always larger

DS2  1 (VGS1 0 VAV : TH )(VGS2 0 VTH )

(10)

The output resistance of the noncascode structure is

RONC

The condition for ROGR > RONC can be obtained by (10) and (11), which resulted in

2 = I1 = : DS0 0 (VGS0 0 VTH )2

(11)

A>

1 (VGS1 VTH )(VGS2 VTH ) 0 (VGS0 VTH )2

For the same drain current of 0 , 1 , and 2 with the same power consumption of the error amplier, VGS 1 > VGS 0 and VGS 2 > VGS 0 , since 1 and 2 operate in the linear region while 0 , 1 operates in 0 , (12) is approximated the saturation region. Moreover, when 1 to

M M

VDS2

(12)

M M

: (13) VDS2 From (13), it is obvious that when VDS 2 increases, the required A is decrease. The gain-retained structure is more effective when M2 provides higher gain. This is, in fact, the case when M2 trends to operate

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in the saturation region (i.e., a higher VDS2 ). Therefore, the worst case occurs when 0 is at the boundary of the linear region and the saturation region (i.e., VDS0 VDS( ) ). The minimum A is determined based on the channel length as well. The improvement can be shown by a case study. Assuming that IDS0 IDS1 IDS2 : V,  , VDS0(sat) VGS0 0 VTH VDS0 : ; and VDS1 : V, VDS1(sat) VGS1 0 VT H : V < VDS1(sat) . 0 operates in the saturation region, but both 1 and 2 operate in the linear region. The values of 0 and 1 are found to be 1 mA/V and 667  =V, respectively. When the gain of the aux: V01 , based on (10) and (11), iliary amplier is 1 k V/V and  ROGR : is larger than RONC . Case III) ( 0 : Linear) versus ( 1 : Linear, 2 : Linear): For the noncascode structure, when 0 operates in the linear region

sat

= = = 10 A = = 02 V = 02 = 01 M M A = 0 05 = 3 7 M
= 2 M
M M M M 1 RONC = : 0 (VGS0 0 VTH 0 VDS0 )

=01 = M

(14)
Fig. 6. Simulated loop gain versus I amplier. for different output stages of the error

The condition for ROGR > RONC can be obtained by (7) and (14), which resulted in

AVDS2 1 (VGS1 0 VTH 0 VDS1 )(VGS2 0 VTH 0 VDS2 ) 1 : (15) > 0 (VGS0 0 VTH 0 VDS0 )
This expression can be rewritten as

V 0V 0V VDS2 > GS1 TH DS1 VGS0 0 VTH 0 VDS0

1 (VGS2 0 VTH 0 VDS2 ) : A0

(16)

Similarly, for the same drain current of o , 1 , and 2 with the same power consumption of the error amplier, VGS 1 > VGS 0 since VDS0 > VDS1 (see to Fig. 5). Therefore, when

M M

1  0

(17)

it is approximated to

V 0 VTH 0 VDS2 VDS2 > GS2 : A

(18)
Fig. 7. Frequency response for the output impedance.

This expression gives

uration voltage divided by the gain of the auxiliary amplier. The earlier analysis and conclusion are veried by simulations shown in Fig. 6. The simulations were performed by BSIM3v3 models from austriamicrosystems (AMS) 0.35-m CMOS technology. The loop gain LO , which relies on the gain of the error amplier, is the best when using the single-sided gain-retained method on both the magnitude and also the gain drop at higher IOUT (corresponding to lower VOEA ). At the designed maximum IOUT of 110 mA, LO is about 14 dB higher when the single-sided gain-retained error amplier is used. The frequency response of the proposed structure can be studied by the output impedance of the error amplier ZOEA shown in Fig. 7. The capacitance CGPT models the gate capacitance of the power transistor. It is always much larger than the parasitic capacitances in the proposed structure. The auxiliary amplier is a single-stage amplier and has a transconductance of gma . From Fig. 7, the output impedance is given by

V 0 VTH VDS2(sat) VDS2 > GS2 (19) = A+1 : A+1 From (19), ROGR is larger than RONC until VDS 2 is less than its sat-

where Cg2 is the gate capacitance of 2 . It is noted that there is a polezero doublet (at the same frequency) equal to the unity-gain frequency (UGF) of the auxiliary amplier. A rst-order single-pole error amplier is generally preferred in LDO design for simple and easy frequency compensation. Therefore, the nondominant pole should be located at a much higher frequency than the UGF of the open-loop response of the error amplier. Thus, the following relationship is set:

gmA1 CGPT rds1 Agm2 gma UGF = C  Cg2 Cgd2 GPT

(21)

where gmA1 is the transconductance of the input stage of the error amplier ( A1 and A2 in Fig. 4). Equation (21) is rewritten as

2 CGPT Cg2 Cgd2

rds1 Agm2 gma gmA1

 1:

(22)

ZOEA

ds1 Agm2 rds2  (1+sCGPTrds1 Agm2 rds2r)(1+ sCg2 Cgd1 =CGPT rds1 Agm2 gma )

(20)

This condition in (22) always holds when the local loop gain by 2 and A is higher than 0 dB, since the capacitance ratio is always much greater than 1 due to the large gate capacitance of the power transistor. In addition, gma , which corresponds to the required power needed by the auxiliary amplier, does not need to be high to make the condition stated in (22) valid. Thus, the power consumption of the auxiliary amplier can be neglected.

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Fig. 8. Micrograph of the proposed LDO using single-sided gain-retained method.

TABLE I SUMMARY OF LDO PERFORMANCE

Fig. 9. Measured load regulations.

V. EXPERIMENTAL RESULTS Two LDOs have been implemented in an AMS CMOS 0.35-m technology. Both of them have equal size of power transistor (i.e., 9000 m/0.35 m). One uses the error amplier with a noncascode output stage (denoted as the classical LDO) and another uses the one proposed in Fig. 4 (denoted as the proposed LDO). The micrograph of the proposed LDO is shown in Fig. 8. The increase of the chip area due the proposed structure is very small when compare to the integrated power transistor. The overall performances of the two LDOs are listed in Table I for comparison. The ground currents are similar, since the current consumption of the auxiliary amplier is not signicant and the gain-retained structure is always stable in the LDO design. The measured load regulations of the two LDOs at VIN = 1:5 V and VOUT = 1:3 V are plotted in Fig. 9. The testing range of the output current is from 1 to 130 mA. The load regulations in Fig. 9 can be separated into three regions for studies. When IOUT  90 mA, the proposed LDO shows a better regulation due to the slightly higher loop gain. When 90 mA < IOUT  110 mA, VOUT of the proposed LDO slightly drops, while VOUT of the classical LDO relatively drops much larger. This shows that the proposed high-swing gain-retained structure can retain the voltage gain of the error amplier even when the IOUT is high (i.e., VSG of the power transistor is large). Lastly, when IOUT > 110 mA, VOUT of both LDOs drop similarly, since both output stages cease to provide high output resistances. From this result, the load regulation of the proposed LDO is better, which corresponds to the reduction of the steady-state error of VOUT by 0.55%. The difference with the simulated result shown in Fig. 6 is due to the accuracy of the device models. This improvement is very signicant to typical LDO

Fig. 10. Measured load transient responses.

products of 0.6%2% accuracy budget. As a remark, according to the simulations for further analysis, the size of the power transistor needed to achieve similar load regulation by the classical LDO is about 12000 m/0.35 m. This corresponds to 25% size reduction of the power transistor when the proposed method to improve the load regulation is use. Finally, the transient response is not affected by the proposed structure since there is no difference in the loop bandwidth and the slew rate at the gate of the power transistor [2]. Fig. 10 shows the load transient responses of the conventional and the proposed LDOs under the same change of the output current (1110 mA). The load capacitance is 100 pF to model the capacitance of the power-supply routings. The proposed LDO provides a similar load transient response as the conventional LDO. In addition, there is an improvement of the load regulation shown in the steady state.

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VI. CONCLUSION Single-sided ultrawide-swing gain-retained method for the error amplier design has been proposed to improve the load regulation of an LDO. Theoretical study and experimental results have been introduced to prove the idea. The idea can be extended to the analog-driver design for maximizing the output capability.

Diagnosis of MRAM Write Disturbance Fault

Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen-Ching Wu, Chien-Chung Hung, and Ming-Jer Kao

REFERENCES
[1] D. D. Buss, Technology in the internet age, in Dig. IEEE Int. SolidState Circuits Conf., 2002, pp. 1821. [2] G. A. Rincon-Mora and P. E. Allen, A low-voltage, low quiescent current, low drop-out regulator, IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 3644, Jan. 1998. [3] H. Lee, P. K. T. Mok, and K. N. Leung, Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 9, pp. 563567, Sep. 2005. [4] K. N. Leung and P. K. T. Mok, A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 16911702, Oct. 2003. [5] C. K. Chava and J. Silva-Martinez, A frequency compensation scheme for LDO voltage regulators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 6, pp. 10411050, Jun. 2004. [6] Y. H. Lam, W. H. Ki, and C. Y. Tsui, Adaptively biased capacitor less CMOS low dropout regulator with direct current feedback, in Proc. IEEE/ACM 11th Asia South Pacic Design Autom. Conf., Jan. 2006, pp. 104105. [7] G. A. Rincon-Mora and P. E. Allen, Optimized frequency-shaping circuit topologies for LDOs, IEEE Trans Circuit Syst. II, Exp. Briefs, vol. 45, no. 6, pp. 703708, Jun. 1998. [8] B. Razavi, Design of Analog CMOS Integrated Circuits. Boston, MA: McGraw-Hill, 2001.

AbstractIn this paper, we propose a new test method to detect write disturbance fault (WDF) for magnetic RAM (MRAM). Furthermore, an adaptive diagnosis algorithm (ADA) is also introduced to identify and diagnose the WDF for MRAM. The proposed test method can evaluate process stability and uniformity. We also develop a built-in self-test (BIST) circuit that supports the proposed WDF diagnosis test method. A 1-Mb toggle MRAM prototype chip with the proposed BIST circuit has been designed and fabricated using a special 0 15- m CMOS technology. The BIST circuit overhead is only about 0.05% with respect to the 1-Mb MRAM. The test time is reduced by about 30% as compared with the test method without using the decision write mechanism. The chip measurement results show the efciency of our proposed method. Index TermsFault diagnosis, magnetic RAM (MRAM), memory testing, nonvolatile memory, write disturbance fault (WDF).

I. INTRODUCTION Many applications require a system-on-chip (SOC) to integrate nonvolatile memories. Although ash memory is widely used today, high voltage for program and erase operations, and some reliability issues are hard to handle[1]. In recent years, the industry has tried to nd an appropriate nonvolatile memory that can replace ash memory. MRAM is considered a good choice due to its high speed, low operating voltage, and virtually unlimited read/write endurance [2], [3]. We, therefore, see a growing need for MRAM testing and diagnosis methodologies [4][8]. In recent years, there are two different types of MRAM that have been proposed, i.e., the asteroid MRAM and the toggle MRAM. However, the asteroid MRAM devices have some problems such as the disturbance by half-selected cells and loss of data due to thermal agitation [9]. The toggle MRAM has been proposed to solve that issue [10]. In general, compared with conventional asteroid MRAM, the toggle MRAM has better write and read margins, higher reliability, better scalability, etc. However, this does not mean the reliability and test issues of toggle MRAM are solved [11]. There are only a few technical papers on MRAM testing so far. The authors in [4] propose some defect models based on SPICE simulation for asteroid MRAM. Later, the write disturbance fault (WDF) model for toggle MRAM is proposed [5], [8], which is a fault that affects the data stored in the MRAM cells due to excessive magnetic eld generated during the write operation. In general, March test algorithms, which are widely used for memory testing, have linear complexity and high coverage for conventional RAM faults; however,

Manuscript received October 25, 2008; revised April 05, 2009. First published September 01, 2009; current version published November 24, 2010. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 95-2221-E-007-258-MY3. C.-L. Su and C.-W. Tsai are with the R&D Department, Skymedi Corporation, Hsinchu 300, Taiwan (e-mail: clsu@larc.ee.nthu.edu.tw). C.-Y. Chen, W.-Y. Lo, and C.-W. Wu are with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan. J.-J. Chen, W.-C. Wu, and C.-W. Wu are with the SOC Technology Center, Industrial Technology Research Institute, Hsinchu 31040, Taiwan. C.-C. Hung and M.-J. Kao are with the Electronics and Opto-Electronics Research Laboratory, Industrial Technology Research Institute, Hsinchu 31040, Taiwan. Digital Object Identier 10.1109/TVLSI.2009.2026905 1063-8210/$26.00 2009 IEEE