Virtex-II V2MB1000 Development Board Users Guide

Version 3.0 December 2002

PN# DS-MANUAL-V2MB1000

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Table of Contents
1 2 OVERVIEW ....................................................................................................................1 THE VIRTEX-II SYSTEM BOARD ...................................................................................1 2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.7 2.8 2.8.1 2.9 2.9.1 2.9.2 2.10 VIRTEX -II SYSTEM BOARD D ESCRIPTION ......................................................................2 VIRTEX -II DEVICE .....................................................................................................2 DDR M EMORY .........................................................................................................3 CLOCK G ENERATION .................................................................................................4 R ESET C IRCUIT ........................................................................................................5 USER 7-S EGMENT D ISPLAY........................................................................................5 7-Segment Display Signal Description..................................................................6 USER LED...............................................................................................................6 USER PUSH B UTTON SWITCHES (SW5, AND SW6) ........................................................6 User Push Button Switch Signal Assignments.......................................................6 USER DIP SWITCH (SW2) .........................................................................................6 User DIP Switch Interface ...................................................................................6 User DIP Switch Signal Assignments ...................................................................7 RS232 PORT...........................................................................................................7 RS232 Interface..............................................................................................7 RS232 Signal Descriptions ..............................................................................8

2.10.1 2.10.2 2.11

JTAG PORT ............................................................................................................8 Standard JTAG Connector ..............................................................................8 Parallel Cable IV Port ......................................................................................8 JTAG Chain ...................................................................................................9 JTAG Chain Jumper Settings ..........................................................................9

2.11.1 2.11.2 2.11.3 2.11.4 2.12

SELECTMA P/SLAVE S ERIAL PORT ...............................................................................9 Slave SelectMap........................................................................................... 10 Master SelectMap......................................................................................... 10

2.12.1 2.12.2 2.13 2.14

SLAVE SERIAL PORT ............................................................................................... 11 BANK I/O VOLTAGE ................................................................................................. 11 Bank I/O Voltage Jumper Settings ................................................................. 11

2.14.1 2.15 2.16 2.17 2.18

VIRTEX -II POWER DOWN MODE ................................................................................ 12 VIRTEX -II VBAT..................................................................................................... 13 ISP PROM ........................................................................................................... 13 LVDS PORT .......................................................................................................... 14

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2.18.1 2.18.2 2.18.3 2.19 2.20

LVDS Interface ............................................................................................. 14 LVDS Port Signal Descriptions ...................................................................... 17 Packet Over SONET Level 4 (PL4) application ............................................... 19

PROGRAM SWITCH (SW2) ....................................................................................... 20 VOLTAGE R EGULATORS ........................................................................................... 20 Voltage Regulators Jumper Settings .............................................................. 21

2.20.1 2.21 2.22 3

VIRTEX -II CONFIGURATION M ODE S ELECT .................................................................. 22 P160 EXPANSION MODULE S IGNAL ASSIGNMENTS ....................................................... 23

DESIGN DOWNLOAD.................................................................................................. 25 3.1 3.1.1 3.1.2 3.2 3.3 3.4 JTAG INTERFACE ................................................................................................... 25 Configuring the Virtex-II FPGA........................................................................... 25 Programming the XC18V04 ISP PROM.............................................................. 25 SLAVE SERIAL INTERFACE ........................................................................................ 26 MASTER S ELECTMAP INTERFACE .............................................................................. 26 SLAVE SELECT MAP INTERFACE................................................................................. 26

REVISION HISTORY............................................................................................................ 27 APPENDIX A VIRTEX-II SYSTEM BOARD SCHEMATICS .................................................. 28

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Figures
FIGURE 1 V IRTEX -II SYSTEM BOARD .........................................................................................1 FIGURE 2 VIRTEX -II SYSTEM BOARD BLOCK D IAGRAM .................................................................2 FIGURE 3 DDR INTERFACE......................................................................................................3 FIGURE 4 R ESET CIRCUIT ........................................................................................................5 FIGURE 5 - 7-S EGMENT LED DISPLAY INTERFACE .........................................................................5 FIGURE 6 USER DIP SWITCH INTERFACE ...................................................................................7 FIGURE 7 RS232 INTERFACE ..................................................................................................7 FIGURE 8 J2 JTAG CONNECTOR .............................................................................................8 FIGURE 9 JP29 PARALLEL IV PORT..........................................................................................8 FIGURE 10 V IRTEX -II SYSTEM B OARD JTAG CHAIN ....................................................................9 FIGURE 11 S ELECTMAP/SLAVE SERIAL CONNECTOR ................................................................. 10 FIGURE 12 SLAVE SELECTMAP MODE C ONFIGURATION ............................................................. 10 FIGURE 13 MASTER S ELECTMAP M ODE CONFIGURATION........................................................... 11 FIGURE 14 SLAVE SERIAL MODE CONFIGURATION ..................................................................... 11 FIGURE 15 V IRTEX -II POWER D OWN MODE.............................................................................. 13 FIGURE 16 ISP PROM INTERFACE......................................................................................... 14 FIGURE 17 LVDS TRANSMIT PORT ......................................................................................... 15 FIGURE 18 LVDS RECEIVE PORT ........................................................................................... 16 FIGURE 19 LVDS TRANSMIT AND R ECEIVE C ONTROL PORTS ...................................................... 16 FIGURE 20 PACKET OVER SONET LEVEL 4 (PL4) INTERFACE ................................................... 20 FIGURE 21 V IRTEX -II DEVELOPMENT BOARD VOLTAGE R EGULATORS .......................................... 21 FIGURE 22 D OWNLOAD S ETUP ............................................................................................... 25

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Tables
TABLE 1 - DDR M EMORY INTERFACE S IGNAL DESCRIPTIONS ..........................................................3 TABLE 2 V IRTEX-II DEVELOPMENT BOARD MASTER CLOCKS .........................................................4 TABLE 3 - 7-S EGMENT D ISPLAY SIGNAL D ESCRIPTIONS ..................................................................6 TABLE 4 - USER P USH BUTTON SWITCH S IGNAL ASSIGNMENTS .......................................................6 TABLE 5 - USER DIP SWITCH S IGNAL ASSIGNMENTS ......................................................................7 TABLE 6 - RS232 S IGNAL D ESCRIPTIONS .....................................................................................8 TABLE 7 - JTAG CHAIN J UMPER S ETTINGS ..................................................................................9 TABLE 8 - BANK I/O VOLTAGE J UMPER S ETTINGS ........................................................................ 12 TABLE 9 - LVDS TRANSMIT P ORT S IGNAL DESCRIPTIONS ............................................................. 17 TABLE 10 - LVDS RECEIVE P ORT S IGNAL DESCRIPTIONS ............................................................. 18 TABLE 11- LVDS TRANSMIT CONTROL PORT SIGNAL D ESCRIPTIONS .............................................. 19 TABLE 12- LVDS RECEIVE C ONTROL PORT S IGNAL D ESCRIPTIONS ............................................... 19 TABLE 13 - VOLTAGE R EGULATORS J UMPER S ETTINGS ................................................................ 21 TABLE 14 - V IRTEX -II CONFIGURATION MODE S ELECT.................................................................. 22 TABLE 15 JX1 USER I/O CONNECTOR .................................................................................... 23 TABLE 16 JX2 USER I/O CONNECTOR .................................................................................... 24

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Overview

The Virtex-II V2MB1000 Development Kit provides a complete solution for developing designs and applications based on the Xilinx Virtex-II FPGA family. The kit bundles an expandable VirtexII based system board with a power supply, user guide and reference designs. Also available from Memec Design, optional P160 expansion modules enable further application specific prototyping and testing. Xilinx ISE software and a JTAG cable are available as kit options. The Virtex-II system board utilizes the 1-million gate Xilinx Virtex-II device (XC2V1000-4FG456C) in the 456 fine-pitch ball grid array package. The high gate density and large number of user I/Os allows complete system solutions to be implemented in the advanced platform FPGA. The system board includes a 16M x 16 DDR memory, two clock sources, RS-232 port, and additional support circuits. An LVDS interface is provided with a 16-bit transmit and 16-bit receive port plus clock, status, and control signals for each. The board also supports the Memec Design P160 expansion module standard, allowing application specific expansion modules to be easily added. The Virtex-II FPGA family has the advanced features needed to fit demanding, high-performance applications. The Virtex-II Development Kit provides an excellent platform to explore these features so that you can quickly and effectively meet your time-to-market requirements.

The Virtex-II System Board

The Memec Design Virtex-II System Board provides the FPGA, support circuits and the P160 expansion slot for application specific add-on cards. Figure 1 shows a picture of the board and its features.

Figure 1 Virtex-II System Board

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2.1

Virtex-II System Board Description

A high-level block diagram of the Virtex-II development board is shown in Figure 2 followed by a brief description of each sub-section.
User 7-Segment Display (2) User Switches

80-Pin Connector

P160 Module

User LEDs

RS232 Port

ISP PROM (XC18V04) JTAG Port

Virtex-II FPGA XC2V1000 (FG456)

SlaveSerial/ SelectMap 32MB DDR SDRAM 1.5V Regulator 16-bit LVDS Interface 2.5V Regulator 3.3V Regulator Voltage Regulators

Clock Generator (100 & 24Mhz)

Reset Circuit

Figure 2 Virtex-II System Board Block Diagram

2.2

Virtex-II Device

The Virtex-II board utilizes the Xilinx Virtex-II XC2V1000-4FG456C. The Virtex -II family is a platform FPGA developed for high performance, low to high-density designs utilizing IP cores and customized modules. The Virtex-II family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications. The performance and density of the Virtex-II family along with its supported I/O standards such as LVDS, PCI, and DDR enables FPGA designers to meet the design requirements of the next generation Networking and telecommunication applications. The Xilinx Virtex-II FPGA along with its supporting I/O devices on this development board, will assist FPGA designers to prototype high-performance memory and I/O interfaces such as complete high-performance Packet Over SONET Level 4 (PL4) over a 16-bit LVDS bus, high speed DDR memory interface, and a variety of other I/O interfaces via the on-board I/O module.

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80-Pin Connector

2.3 DDR Memory The Virtex-II development board provides 32MB of DDR memory on the system board. This memory is implemented using the Micron MT46V16M16TG -75 16Mx16 DDR device. A high-level block diagram of the DDR interface is shown below followed by a table describing the DDR memory interface signals.

OSC 100Mhz

clk_in

Data[15:0] Addr[12:0] BS[1:0]

reset LDM UDM clk_fb Virtex-II FPGA LDQS UDQS CSn RASn CASn WEn CLKE CLKn CLK 16M x 16 DDR (MT46V16M16TG-75)

Figure 3 DDR Interface

Table 1 - DDR Memory Interface Signal Descriptions Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Description Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Address 9 Address 10 Address 11 FPGA Pin # B18 A18 B17 A17 N17 P18 P17 M18 M19 M20 A19 N18 DDR Pin # 29 30 31 32 35 36 37 38 39 40 28 41

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A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 BS0 BS1 LDM UDM LDQS UDQS CSn RASn CASn WEn CLK CLKn CKE

Address 12 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Bank Select 0 Bank Select 1 Low Write Mask High Write Mask Low Write/Read Data Strobe High Write/Read Data Strobe Chip Select Row Address Strobe Column Address Strobe Write Enable Clock Clock Clock Enable

N20 Y21 Y22 W21 V21 V22 U21 U22 T21 R20 R19 T20 T19 U19 V20 V19 W20 M21 B19 R21 T22 P20 P19 N22 N21 P21 R22 D12 E12 N19

42 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 26 27 20 47 16 51 24 23 22 21 45 46 44

2.4 Clock Generation The Virtex-II system board provides two on-board oscillators running at 100Mhz (CLK.CAN2) and 24Mhz (CLK.CAN1). The 100Mhz oscillator is enabled when the JP24 jumper is open and disabled when JP24 is closed. JP23 controls the 24MHz oscillator, enabling it when open and disabling it when closed. A third user clock socket is provided for addition of a user specified oscillator device. The following table provides a brief description of these clock signals.

Table 2 Virtex-II Development Board Master Clocks Signal Name CLK.CAN2 CLK.CAN1 CLK.CAN3 Virtex-II Pin # B11 A11 F12 Direction Input Input Input Description On-board 100 MHz Oscillator On-board 24 MHz Oscillator User clock socket (2.5V supply)

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2.5 Reset Circuit The Virtex-II system board uses the TI TPS3125 voltage supervisory device to monitor the VirtexII FPGA core voltage (1.5V). This circuit asserts a reset signal (FPGA_RESETn) to the Virtex-II device when the 1.5V core voltage falls below its minimum specifications (1.425V). The reset signal to the FPGA is a fixed 100ms active low pulse. In addition to monitoring the core voltage, this circuit can be used to generate a reset pulse by activating the Master Reset (MRn) signal to the TPS3125 device via the on-board push-button switch (SW3). The following figure shows the reset circuit on the Virtex-II development board.

1.5V VDD

TPS3125

FPGA

FPGA_RESETn RESETn B6

SW3

MRn

Figure 4 Reset Circuit

2.6

User 7-Segment Display

The Virtex-II system board utilizes two common-cathode 7-segment LED displays that can be used during the test and debugging phase of a design. The user can turn a given segment on by driving the associated signal high. The following figure shows the user 7-segment display interface to the Virtex-II FPGA.

DISPLAY.1F DISPLAY.1G DISPLAY.1E DISPLAY.1D DISPLAY.1C DISPLAY.1B DISPLAY.1A

A1 F1 G1 B1 F2

A2 B2 G2 C1 E2 C2

DISPLAY.2F DISPLAY.2G DISPLAY.2E DISPLAY.2D DISPLAY.2C DISPLAY.2B DISPLAY.2A

E1

D1

D2

Figure 5 - 7-Segment LED Display Interface

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2.6.1 7-Segment Display Signal Description The following table shows the 7-Segment LED display pin descriptions. Table 3 - 7-Segment Display Signal Descriptions Signal Name DISPLAY.1A DISPLAY.1B DISPLAY.1C DISPLAY.1D DISPLAY.1E DISPLAY.1F DISPLAY.1G DISPLAY.2A DISPLAY.2B DISPLAY.2C DISPLAY.2D DISPLAY.2E DISPLAY.2F DISPLAY.2G Virtex-II Pin # D9 C9 F11 F9 F10 D10 C10 B9 A8 B8 E7 E8 E10 E9 Description 7-Segment LED Display1, Segment A 7-Segment LED Display1, Segment B 7-Segment LED Display1, Segment C 7-Segment LED Display1, Segment D 7-Segment LED Display1, Segment E 7-Segment LED Display1, Segment F 7-Segment LED Display1, Segment G 7-Segment LED Display2, Segment A 7-Segment LED Display2, Segment B 7-Segment LED Display2, Segment C 7-Segment LED Display2, Segment D 7-Segment LED Display2, Segment E 7-Segment LED Display2, Segment F 7-Segment LED Display2, Segment G

2.7

User LED

The Virtex-II system board provides a single user LED. Pin A9 of the Virtex -II FPGA is used to drive this active high signal.

2.8 User Push Button Switches (SW5, and SW6) The Virtex-II system board provides two user push button switch inputs to the Virtex-II FPGA. Each push button switch can be used to generate an active low signal. 2.8.1 User Push Button Switch Signal Assignments The following table shows the pin assignments for the user push button switches.

Table 4 - User Push Button Switch Signal Assignments Signal Name FPGA.PUSH1 FPGA.PUSH2 Virtex-II Pin # D7 A6 Description User Push Button Switch Input 1 (SW5) User Push Button Switch Input 2 (SW6)

2.9 User DIP Switch (SW2) The Virtex-II system board provides 8 user switch inputs. These switches can be statically set to a low or high logic level. 2.9.1 User DIP Switch Interface The following figure shows the user DIP switch interface to the Virtex-II FPGA.

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SW4 Switch
DIP8 DIP7 DIP6 DIP5 DIP4 DIP3 DIP2 DIP1

9 10 11 12 13 14 15 16

8 7 6 5 4 3 2 1

Figure 6 User DIP Switch Interface

2.9.2 User DIP Switch Signal Assignments The following table shows the user switch pin assignments.

Table 5 - User DIP Switch Signal Assignments

Signal Name DIP8 DIP7 DIP6 DIP5 DIP4 DIP3 DIP2 DIP1 Virtex-II Pin # C6 D6 A5 B5 C5 C4 A4 B4 Description User Switch Input 8 User Switch Input 7 User Switch Input 6 User Switch Input 5 User Switch Input 4 User Switch Input 3 User Switch Input 2 User Switch Input 1

2.10 RS232 Port The Virtex-II system board provides an RS232 port that can be driven by the Virtex-II FPGA. A subset of the RS232 signals is used on the Virtex-II development board to implement this simple interface (RD and TD signals). 2.10.1 RS232 Interface The Virtex-II system board provides a DB-9 connection for a simple RS232 port. The board utilizes the TI MAX3221 RS232 driver for driving the RD and TD signals. The user provides the RS232 UART code, which resides in the Virtex-II FPGA.
JDR1 Connector RXD TXD Din Rout RS232 Drivers MAX3221 Dout Rin RD TD 2 3

Figure 7 RS232 Interface

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2.10.2 RS232 Signal Descriptions The following table shows the RS232 signals and their pin assignments to the Virtex-II FPGA. Table 6 - RS232 Signal Descriptions Signal Name RXD TXD Virtex-II Pin # A7 B7 Description Received Data, RD to DB9 Transmit Data, TD from DB9

2.11 JTAG Port The Virtex-II development board provides a JTAG connector that can be used to program the onboard ISP PROM and configure the Virtex-II FPGA. Two connector options are provided, J2 is a 1 x 7 header used to connect standard JTAG cable fly leads, and JP29 is used for connection of the Xilinx Parallel IV JTAG cable. 2.11.1 Standard JTAG Connector The following figure shows the pin assignments for the J2 JTAG connector on the Virtex-II development board.
J2 JTAG Connector 1 2 3 4 5 6 7 3.3V GND TCK TDO TDI TMS

Figure 8 J2 JTAG Connector

2.11.2 Parallel Cable IV Port The following figure shows the pin assignments for the Parallel Cable IV connector. The Parallel Cable IV can also be used to configure the FPGA via Slave Serial configuration mode.
2.5V JP20 Parallel Cable IV 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TMS/PROG TCK/CCLK TDO/DONE TDI/DIN

Figure 9 JP29 Parallel IV Port

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2.11.3 JTAG Chain The following figure shows the JTAG chain on the Virtex-II development board. Jumper JP22 provides the ability to remove the ISP PROM from the JTAG chain for direct connection to the FPGA.
1 TDI 2 3 4 JP22

TDI XC18V04 ISP TDO PROM TMS TCK Virtex-II FPGA

TDI TMS TCK TMS TCK

TDO

TDO

Figure 10 Virtex-II System Board JTAG Chain

2.11.4 JTAG Chain Jumper Settings The following table shows the JTAG chain jumper setting on the Virtex-II development board.

Table 7 - JTAG Chain Jumper Settings Jumper JP28 JP22 Setting 1-2 Closed 2-3 Closed 1-2, 3-4 2-3 Description Disable PROM Enable PROM (normal setting) PROM in chain (normal setting) Remove PROM from chain (FPGA only)

2.12 SelectMap/Slave Serial Port In addition to the JTAG mode, the Virtex-II FPGA on the development board can be configured using the Slave Serial or the SelectMap mode of configuration. The following figure shows the connector pin assignments for the Slave Serial/SelectMap port.

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J3 SelectMap/Slave Serial Connector CSn 1 DONE 3 CCLK 5 I NI T n 7 PROGRAMn 9 11 RD/Wn 13 DOUT/BUSY 15 16 14 D7 10 D5 12 D6 8 D4 6 D3 4 D2 2 D1 D0

Figure 11 SelectMap/Slave Serial Connector 2.12.1 Slave SelectMap In the Slave SelectMAP configuration mode, a byte of configuration data is loaded into the VirtexII FPGA during each CCLK clock cycle. In this mode, an external source drives the CCLK clock and the data bus containing the configuration data. The following figure shows the Slave SelectMap configuration mode interface to the Virtex-II FPGA.

D[0:7] D[0:7] DONE DONE CCLK CCLK I NI T n INIT_B PROGRAMn PROG_B RD/Wn RDWR_B DOUT/BUSY BUSY CSn CS_B Virtex-II FPGA

Figure 12 Slave SelectMap Mode Configuration 2.12.2 Master SelectMap In the Master SelectMAP configuration mode, a byte of configuration data is loaded into the Virtex-II FPGA during each CCLK clock cycle. In this mode, the Virtex-II FPGA drives the CCLK clock while receiving configuration data from the PROM. The following figure shows the Master SelectMap configuration mode interface to the Virtex-II FPGA. The JP27 jumper must be installed when configuring the Virtex-II FPGA in the Master SelectMap mode.

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D[0:7] CE CCLK RESET/OE XC18V04 CF

D[0:7] DONE CCLK INIT_B PROG_B Virtex-II FPGA

JP27 Jumper

CS_B RDWR_B

Figure 13 Master SelectMap Mode Configuration

2.13 Slave Serial Port In the Slave Serial configuration mode, a bit of configuration data is loaded into the FPGA during each CCLK clock cycle. In this mode, an external source places the most significant bit of each byte on the DIN pin first and then drives the CCLK clock to store data into the FPGA. The following figure shows the Slave Serial configuration mode interface to the Virtex-II FPGA.
D0 DIN DONE DONE CCLK CCLK I NI T n INIT_B PROGRAMn PROG_B Virtex-II FPGA

Figure 14 Slave Serial Mode Configuration

2.14 Bank I/O Voltage The Virtex-II development board allows the Virtex-II I/O pins to be configured for 2.5V or 3.3V operation. All Virtex-II user I/O pins are grouped in 8 different banks. Each bank of I/O pins on the board can be configured to operate in the 2.5V or the 3.3V mode. 2.14.1 Bank I/O Voltage Jumper Settings The following table shows the jumper settings for the Virtex-II bank I/O voltage (VCCO) selection. Each bank can be set to 2.5V or 3.3V.

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Table 8 - Bank I/O Voltage Jumper Settings

Bank # Virtex-II VCCO Pin # 1-2 Closed Open FIXED JP26 1-2 Closed Open FIXED J19 1-2 Closed Open J20 1-2 Closed Open J21 1-2 Closed Open J21 1-2 Closed Open 2-3 Open Closed 3.3V 2.5V 2-3 Open Closed 3.3V 2.5V 2-3 Open Closed 3.3V 2.5V 2-3 Open Closed 2-3 Open Closed Jumper JP18 0 1 2-3 Open Closed 3.3V 2.5V 2.5V I/O Voltage

2 3

3.3V 2.5V 2.5V

3.3V 2.5V

2.15 Virtex-II Power Down Mode The Virtex-II FPGA family utilizes a dedicated pin called PWRDWN_B that can be used to place the Virtex-II FPGA into a low-power and inactive state. In the normal operating mode, the PWRDWN_B pin would be pulled up. Forcing the PWRDWN_B pin to logic 0 would place the Virtex-II FPGA in power-down mode. The following figure shows the Virtex-II Power Down on the Virtex-II development board.

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Virtex-II FPGA 3.3V

PWRDWN_B

Figure 15 Virtex-II Power Down Mode As shown in the above figure, the Virtex -II FPGA can be placed in the power-down mode on the Virtex-II system board by closing the JP16 jumper (permanently placing it in the power-down mode until the jumper is removed), or by forcing the pin 2 of the JP16 to a logic 0 under user control. The Virtex-II board users can use this pin to place the Virtex -II FPGA in the power-down mode momentarily. The Virtex-II FPGA provides Power-Down status information via the DONE pin if the PWRDWN_STAT option is selected using BitGen. The DONE pin is asserted upon entry to the power-down mode. After a successful wake-up, the DONE status pin is de-asserted (The wakeup sequence is the reverse of the power-down sequence). While in power-down mode, the only active pins are the PWRDWN_B and DONE. All inputs are off and all outputs are 3-stated. While in the Power-Down state, the Power On Reset (POR) circuit is still active, but it does not reset the device if VCCINT, VCCO, or VCCAUX falls below its minimum value. The POR circuit waits until the PWRDWN_B pin is released before resetting the device. Also, the PROG_B pin is not sampled while the device is in the Power-Down state. The PROG_B pin becomes active when the PWRDWN_B pin is released. Therefore, the device cannot be reset while in the PowerDown state.

2.16 Virtex-II VBAT The Virtex-II VBAT input pin (pin A21) is connected to the 3.3V supply on the Virtex-II development board through the JP15 jumper.

2.17 ISP PROM The Virtex-II system board utilizes the Xilinx XC18V04 ISP PROM, allowing FPGA designers to quickly download revisions of a design and verify the design changes in order to meet the final system-level design requirements. The XC18V04 ISP PROM uses two interfaces to accomplish the configuration of the Virtex-II FPGA.

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JP16 Jumper

13

The JTAG port on the XC18V04 device is used to program the PROM with the design bit file. Once the XC18V04 has been programmed, the user can configure the Virtex-II device in Master Serial or Master SelectMap mode. The configuration of the Virtex-II device is initiated by asserting the PROGn signal. Upon activation of the PROGn signal (by pressing the SW2 switch), the XC18V04 device will use its FPGA Configuration Port to configure the Virtex-II FPGA. If the Virtex-II configuration mode is set to Master Serial, the PROM D0, CE, CCLK, RESET/OE, and the CF signals are used to configure the Virtex-II FPGA. In the Master SelectMap mode, in addition to the above signals, the Virtex-II FPGA will use the PROM D1-7 to obtain a byte of configuration data during each CCLK clock cycle. The following figure shows the ISP PROM interface to the JTAG port and the Virtex-II FPGA configuration port.

XC18V04 ISP PROM TDI TMS JTAG Port TCK TDO

Virtex-II FPGA

D[0:7] CE CCLK RESET/OE CF

D[0:7] DONE CCLK INIT_B PROG_B

RDWR_B CS_B

Figure 16 ISP PROM Interface

2.18 LVDS Port The Virtex-II development board provides a complete high-performance differential signaling (LVDS) interface, enabling the designers to prototype high-speed serial communication links. The Virtex-II I/Os are designed to comply with the IEEE electrical specifications for LVDS to make system and board design easier. With the addition of an LVDS current-mode driver in the IOBs, which eliminates the need for external source termination in point -to-point applications, and with the choice of two different voltage modes and an extended mode, Virtex-II devices provide the most flexible solution for doing an LVDS design in an FPGA. 2.18.1 LVDS Interface The Virtex-II development board provides a 16-bit LVDS port (Transmit and Receive) with 6 additional control signals that can be used to implement a high-speed Packet Over SONET Level 4 (PL4) interface. The following figure shows the LVDS interface on the Virtex-II development board. LVDS termination networks are provided between the Virtex-II FPGA and the LVDS user connectors. It should be noted that no LVDS source terminations are needed when using the Virtex-II FPGA family in point-to-point applications.

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J4 LVDSOUT1N LVDSOUT1P LVDSOUT2N LVDSOUT2P LVDSOUT3N LVDSOUT3P LVDSOUT4N LVDSOUT4P LVDSOUT5N LVDSOUT5P LVDSOUT6N LVDSOUT6P LVDSOUT7N LVDSOUT7P LVDSOUT8N LVDSOUT8P LVDSOUT9N LVDSOUT9P LVDSOUT10N LVDSOUT10P LVDSOUT11N LVDSOUT11P LVDSOUT12N LVDSOUT12P LVDSOUT13N LVDSOUT13P LVDSOUT14N LVDSOUT14P LVDSOUT15N LVDSOUT15P LVDSOUT16N LVDSOUT16P 1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 21 22 23 24 25 26 27 28 31 32 33 34 35 36 37 38 LVDS Transmit Connector

Figure 17 LVDS Transmit Port

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J6 LVDSIN1P LVDSIN1N LVDSIN2P LVDSIN2N LVDSIN3P LVDSIN3N LVDSIN4P LVDSIN4N LVDSIN5P LVDSIN5N LVDSIN6P LVDSIN6N LVDSIN7P LVDSIN7N LVDSIN8P LVDSIN8N LVDSIN9P LVDSIN9N LVDSIN10P LVDSIN10N LVDSIN11P LVDSIN11N LVDSIN12P LVDSIN12N LVDSIN13P LVDSIN13N LVDSIN14P LVDSIN14N LVDSIN15P LVDSIN15N LVDSIN16P LVDSIN16N 3 4 5 6 7 8 9 10 13 14 15 16 17 18 LVDS Receive Connector J7 LVDSOUTCLKP LVDSOUTCLKN LVDSOUTSTATCLKP LVDSOUTSTATCLKN LVDSOUTSTAT1P LVDSOUTSTAT1N LVDSOUTSTAT2P LVDSOUTSTAT2N LVDSOUTCTRLP LVDSOUTCTRLN 1 2 5 6 9 10 11 12 13 14 LVDS Transmit Connector (Control Signals) J8 LVDSINCTRLN LVDSINCTRLP LVDSINSTAT2N LVDSINSTAT2P LVDSINSTAT1N LVDSINSTAT1P LVDSINSTATCLKN LVDSINSTATCLKP LVDSINCLKN LVDSINCLKP Source Termination Resistors 1 2 3 4 5 6 9 10 13 14 LVDS Receive Connector (Control Signals)

Source Termination Resistors

19 20 23 24 25 26 27 28 29 30 33 34 35 36 37 38 39 40

Figure 18 LVDS Receive Port

Figure 19 LVDS Transmit and Receive Control Ports

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2.18.2 LVDS Port Signal Descriptions The following table shows the LVDS port signal descriptions and the port signal assignments to the Virtex-II FPGA.

Table 9 - LVDS Transmit Port Signal Descriptions

Signal Name LVDSOUT1N LVDSOUT1P LVDSOUT2N LVDSOUT2P LVDSOUT3N LVDSOUT3P LVDSOUT4N LVDSOUT4P GND GND LVDSOUT5N LVDSOUT5P LVDSOUT6N LVDSOUT6P LVDSOUT7N LVDSOUT7P LVDSOUT8N LVDSOUT8P GND GND LVDSOUT9N LVDSOUT9P LVDSOUT10N LVDSOUT10P LVDSOUT11N LVDSOUT11P LVDSOUT12N LVDSOUT12P GND GND LVDSOUT13N LVDSOUT13P LVDSOUT14N LVDSOUT14P LVDSOUT15N LVDSOUT15P LVDSOUT16N LVDSOUT16P GND GND Virtex-II Pin # H2 H1 J2 J1 K2 K1 E4 E3 NA NA F4 F3 G4 G3 H4 H3 J4 J3 NA NA K4 K3 L3 L2 L5 L4 E6 E5 NA NA F5 G5 H5 J6 J5 K5 K6 L6 NA NA J4 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Description Negative Data Transmit Bit 1 Positive Data Transmit Bit 1 Negative Data Transmit Bit 2 Positive Data Transmit Bit 2 Negative Data Transmit Bit 3 Positive Data Transmit Bit 3 Negative Data Transmit Bit 4 Positive Data Transmit Bit 4 Ground Ground Negative Data Transmit Bit 5 Positive Data Transmit Bit 5 Negative Data Transmit Bit 6 Positive Data Transmit Bit 6 Negative Data Transmit Bit 7 Positive Data Transmit Bit 7 Negative Data Transmit Bit 8 Positive Data Transmit Bit 8 Ground Ground Negative Data Transmit Bit 9 Positive Data Transmit Bit 9 Negative Data Transmit Bit 10 Positive Data Transmit Bit 10 Negative Data Transmit Bit 11 Positive Data Transmit Bit 11 Negative Data Transmit Bit 12 Positive Data Transmit Bit 12 Ground Ground Negative Data Transmit Bit 13 Positive Data Transmit Bit 13 Negative Data Transmit Bit 14 Positive Data Transmit Bit 14 Negative Data Transmit Bit 15 Positive Data Transmit Bit 15 Negative Data Transmit Bit 16 Positive Data Transmit Bit 16 Ground Ground

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Table 10 - LVDS Receive Port Signal Descriptions

Signal Name GND GND LVDSIN1P LVDSIN1N LVDSIN2P LVDSIN2N LVDSIN3P LVDSIN3N LVDSIN4P LVDSIN4N GND GND LVDSIN5P LVDSIN5N LVDSIN6P LVDSIN6N LVDSIN7P LVDSIN7N LVDSIN8P LVDSIN8N GND GND LVDSIN9P LVDSIN9N LVDSIN10P LVDSIN10N LVDSIN11P LVDSIN11N LVDSIN12P LVDSIN12N GND GND LVDSIN13P LVDSIN13N LVDSIN14P LVDSIN14N LVDSIN15P LVDSIN15N LVDSIN16P LVDSIN16N Virtex-II Pin # NA NA M2 M1 N2 N1 P2 P1 R2 R1 NA NA T2 T1 U2 U1 V2 V1 W2 W1 NA NA Y2 Y1 M6 M5 M4 M3 N4 N3 NA NA P4 P3 R4 R3 T4 T3 U4 U3 J6 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Description Ground Ground Positive Data Receive Bit 1 Negative Data Receive Bit 1 Positive Data Receive Bit 2 Negative Data Receive Bit 2 Positive Data Receive Bit 3 Negative Data Receive Bit 3 Positive Data Receive Bit 4 Negative Data Receive Bit 4 Ground Ground Positive Data Receive Bit 5 Negative Data Receive Bit 5 Positive Data Receive Bit 6 Negative Data Receive Bit 6 Positive Data Receive Bit 7 Negative Data Receive Bit 7 Positive Data Receive Bit 8 Negative Data Receive Bit 8 Ground Ground Positive Data Receive Bit 9 Negative Data Receive Bit 9 Positive Data Receive Bit 10 Negative Data Receive Bit 10 Positive Data Receive Bit 11 Negative Data Receive Bit 11 Positive Data Receive Bit 12 Negative Data Receive Bit 12 Ground Ground Positive Data Receive Bit 13 Negative Data Receive Bit 13 Positive Data Receive Bit 14 Negative Data Receive Bit 14 Positive Data Receive Bit 15 Negative Data Receive Bit 15 Positive Data Receive Bit 16 Negative Data Receive Bit 16

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Table 11- LVDS Transmit Control Port Signal Descriptions

Signal Name LVDSOUTCLKP LVDSOUTCLKN GND GND LVDSOUTSTATCLKP LVDSOUTSTATCLKN GND GND LVDSOUTSTAT1P LVDSOUTSTAT1N LVDSOUTSTAT2P LVDSOUTSTAT2N LVDSOUTCTRLP LVDSOUCTRLN Virtex-II Pin # C1 C2 NA NA D1 D2 NA NA E1 E2 F1 F2 G1 G2 J7 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description Positive Transmit Clock Negative Transmit Clock Ground Ground Positive Transmit Status Clock Negative Transmit Status Clock Ground Ground Positive Transmit Status1 Negative Transmit Status1 Positive Transmit Status2 Negative Transmit Status2 Positive Transmit Control Negative Transmit Control

Table 12- LVDS Receive Control Port Signal Descriptions

Signal Name LVDSINCTRLN LVDSINCTRLP LVDSINSTAT2N LVDSINSTAT2P LVDSINSTAT1N LVDSINSTAT1P GND GND LVDSINSTATCLKN LVDSINSTATCLKP GND GND LVDSINCLKN LVDSINCLKP Virtex-II Pin # V3 V4 N5 N6 P5 P6 NA NA W11 V11 NA NA AA11 Y11 J8 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description Negative Receive Control Positive Receive Control Negative Receive Status2 Positive Receive Status2 Negative Receive Status1 Positive Receive Status1 Ground Ground Negative Receive Status Clock Positive Receive Status Clock Ground Ground Negative Receive Clock Positive Receive Clock

2.18.3 Packet Over SONET Level 4 (PL4) application One of the possible applications of the LVDS port on the Virtex-II development board is to prototype a high-speed Packet Over SONE T Level 4 (PL4) interface. PL4 is used in point-t o-point applications supporting OC-192 (10 Gbit/s) aggregate bandwidth. The following figure shows how the Virtex-II along with the LVDS port on the Virtex -II development board can be used to implement the PL4 interface. This interface supports 16 bits of data and various miscellaneous signals to control the flow of the data transmission in each direction. Specifically, the status_data_tx[1:0] and status_clk_tx signals are used to control the transmit FIFO, while the status_data_rx[1:0] and status_clk_rx signals are used to control the receive FIFO.

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data_tx[15:0] clk_tx Transmit Link Layer control_tx

data_tx[15:0] clk_tx control_tx

status_data_tx[1:0] status_clk_tx Virtex-II FPGA data_rx[15:0] clk_rx Receive Link Layer control_rx

status_data_tx[1:0] status_clk_tx PHY Device data_rx[15:0] clk_rx control_rx

status_data_rx[1:0] status_clk_rx

status_data_rx[1:0] status_clk_rx

Figure 20 Packet Over SONET Level 4 (PL4) Interface

2.19 Program Switch (SW2) The Virtex-II system board provides a push button switch for initiating the configuration of the Virtex-II FPGA. This switch is used when the XC18V04 ISP PROM configures the Virtex-II FPGA. After programming of the XC18V04 ISP PROM, this switch can assert the PROGn signal. Upon activation of the PROGn signal, the XC18V04 ISP PROM initiates the configuration of the Virtex-II FPGA. 2.20 Voltage Regulators The following figure shows the voltage regulators that are used on the Virtex-II development board to provide various on-board voltage sources. As shown in the following figure, JP1 connector is used to provide the main 5.0V voltage to the board. This voltage source is provided to all on-board regulators to generate the 1.5V, 2.5V, and 3.3V voltages.

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3.3V

2.5V

1.5V

3.3V Reg

2.5V Reg

1.5V Reg

JP6 Jumper

JP9 Jumper

JP12 Jumper

JP7 3.3V Connector

JP10 2.5V Connector

JP13 1.5V Connector

JP1 5.0V Connector

Figure 21 Virtex-II Development Board Voltage Regulators For any one of the on-board voltages (1.5V, 2.5V, and 3.3V), if the current provided by the onboard regulator is not sufficient for some applications, the user can directly drive the voltage source and bypass the on-board regulators. This can be accomplished by removing jumpers JP6, JP9, and JP12 for voltages 3.3V through 1.5V respectively.

2.20.1 Voltage Regulators Jumper Settings The following table shows the jumper setting for the 3.3V, 2.5V, and the 1.5V supply voltages on the Virtex-II development board.

Table 13 - Voltage Regulators Jumper Settings Jumper JP6 Jumper Setting Open Closed JP9 Open Closed JP12 Open Closed 3.3V Source External 3.3V supply via JP7 connector On-board 3.3V regulator NA NA NA NA NA NA External 2.5V supply via JP10 connector On-board 2.5V regulator NA NA 2.5V Source NA NA NA NA External 1.5V supply via JP13 connector On-board 1.5V regulator 1.5V Source

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2.21 Virtex-II Configuration Mode Select The following table shows the Virtex-II Configuration Mode Select jumper settings. The jumper position 7-8 (M3) is connected to the HSWAP_EN pin of the Virtex-II FPGA. When this jumper is closed, the Virtex-II internal I/O pull-ups are enabled during the configuration.

Table 14 - Virtex-II Configuration Mode Select Mode Master Serial Master Serial Slave Serial Slave Serial Master SelectMap Master SelectMap Slave SelectMap Slave SelectMap JTAG JTAG PC Pull-up No Yes No Yes No Yes No Yes No Yes 1-2 (M0) Closed Closed Open Open Closed Closed Open Open Open Open 3-4 (M1) Closed Closed Open Open Open Open Open Open Closed Closed J1 5-6 (M2) Closed Closed Open Open Open Open Closed Closed Open Open 7-8 (M3) Closed Open Closed Open Closed Open Closed Open Closed Open

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2.22 P160 Expansion Module Signal Assignments The following tables show the Virtex-II pin assignments to the P160 Expansion Module connectors (JX1 & JX2) located on the Virtex-II development board.

Table 15 JX1 User I/O Connector

FPGA Pin # I/O Connector Signal Name NC GND NC Vin NC GND NC 3.3V LIOA9 GND LIOA11 2.5V LIOA13 GND LIOA15 Vin LIOA17 GND LIOA19 3.3V LIOA21 GND LIOA23 2.5V LIOA25 GND LIOA27 Vin LIOA29 GND LIOA31 3.3V LIOA33 GND LIOA35 2.5V LIOA37 GND LIOA39 Vin I/O Connector Signal Name NC NC NC NC NC NC NC LIOB8 LIOB9 LIOB10 LIOB11 LIOB12 LIOB13 LIOB14 LIOB15 LIOB16 LIOB17 LIOB18 LIOB19 LIOB20 LIOB21 LIOB22 LIOB23 LIOB24 LIOB25 LIOB26 LIOB27 LIOB28 LIOB29 LIOB30 LIOB31 LIOB32 LIOB33 LIOB34 LIOB35 LIOB36 LIOB37 LIOB38 LIOB39 LIOB40 FPGA Pin #

JX1 Pin #

NA NA NA NA NA NA NA NA K22 NA J21 NA G22 NA F21 NA D22 NA C21 NA L20 NA K19 NA H20 NA G19 NA F20 NA F19 NA D11 NA C11 NA C8 NA D8 NA

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40

NA NA NA NA NA NA NA L22 L21 K21 J22 H22 H21 G21 F22 E22 E21 D21 C22 L18 L19 K18 K20 J20 J19 H19 G20 E19 E20 L17 K17 J17 J18 H18 G18 F18 E18 E11 A10 B10

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Table 16 JX2 User I/O Connector

FPGA Pin # I/O Connector Signal Name RIOA1 RIOA2 RIOA3 RIOA4 RIOA5 RIOA6 RIOA7 RIOA8 RIOA9 RIOA10 RIOA11 RIOA12 RIOA13 RIOA14 RIOA15 RIOA16 RIOA17 RIOA18 RIOA19 RIOA20 RIOA21 RIOA22 RIOA23 RIOA24 RIOA25 RIOA26 RIOA27 RIOA28 RIOA29 RIOA30 RIOA31 RIOA32 RIOA33 RIOA34 RIOA35 RIOA36 RIOA37 RIOA38 RIOA39 RIOA40 JX2 Pin # I/O Connector Signal Name GND RIOB2 Vin RIOB4 GND RIOB6 3.3V RIOB8 GND RIOB10 2.5V RIOB12 GND RIOB14 Vin RIOB16 GND RIOB18 3.3V RIOB20 GND RIOB22 2.5V RIOB24 GND RIOB26 Vin RIOB28 GND RIOB30 3.3V RIOB32 GND RIOB34 2.5V RIOB36 GND RIOB38 Vin RIOB40 FPGA Pin #

AB18 AA16 AA17 AB16 AB17 AA15 W17 AB15 Y17 AA14 W16 AB14 Y16 AA13 V16 AB13 W15 AA12 V14 AB12 U14 AB9 U13 AA9 U12 AB8 U11 AA8 U10 AB7 U9 AA7 V9 AB6 V8 AA6 V7 AB5 V6 AA5

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40

NA Y15 NA W14 NA Y14 NA W13 NA Y13 NA V13 NA Y12 NA W12 NA V12 NA V10 NA Y10 NA W10 NA Y9 NA W9 NA Y8 NA W8 NA Y7 NA W7 NA Y6 NA W6

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Design Download

The Virtex-II development board supports multiple methods of configuring the Virtex-II FPGA. The JTAG port on the Virtex-II development board can be used to directly configure the Virtex-II FPGA, or to program the on-board XC18V04 ISP PROM. Once the ISP PROM is programmed, it can be used to configure the Virtex -II FPGA. The SelectMap/Slave Serial port on this development board can also be used to configure the Virtex-II FPGA. The following figure shows the setup for all Virtex-II FPGA configuration modes that are supported on the Virtex-II development board.
Slave Serial/SelectMap

AC/DC Adapter

PC

Figure 22 Download Setup 3.1 JTAG Interface The J2 JTAG connector on the Virtex-II development board can be used to configure the Virtex -II or to program the on-board XC18V04 ISP PROM. The Memec Design JTAG cable is connected to the Virtex-II development board via J2 at one end and to the PC parallel port at the other end. 3.1.1 Configuring the Virtex-II FPGA

When the JTAG port is used to configure the Virtex-II FPGA, the following steps must be taken: Using Table 14 set the Configuration Mode of the Virtex-II FPGA to JTAG Mode. Use the Xilinx JTAG programmer utility (iMPACT) to load the design bit file into the Virtex-II FPGA. You will need to associate the ISP PROM with either a dummy .mcs file, or a .bsd file to allow the JTAG programming software to pass data through the ISP PROM. 3.1.2 Programming the XC18V04 ISP PROM

When the JTAG port is used to program the ISP PROM, the following steps must be taken: Using Table 14 set the Configuration Mode of the Virtex-II FPGA to Master Serial or Master SelectMap Mode. Use the Xilinx JTAG programmer utility (iMPACT) to load the design mcs file into the ISP PROM. You will need to associate the FPGA with either a dummy .bit file or a .bsd file to allow the JTAG programming software to pass data through the FPGA. Upon programming of the 18V04 ISP PROM, the on-board PROGn push button switch (SW2) is used to initiate the Virtex-II FPGA configuration.

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JP1

J2

Parallel Port

J3

JTAG Cable

Virtex-II Development Board

25

3.2 Slave Serial Interface In this mode, an external source provides the configuration bit stream and the configuration clock (CCLK) to the Virtex-II FPGA. Refer to Table 14 for setting up the Configuration Mode pins. 3.3 Master SelectMap Interface In this mode, the following steps must be taken: Using Ta ble 14 set the Configuration Mode of the Virtex-II FPGA to Master SelectMap Mode. Install the JP27 jumper Use the Xilinx JTAG programmer utility to load the design mcs file into the ISP PROM. You will need to associate the FPGA with either a dummy .bit file or a .bsd file to allow the JTAG programming software to pass data through the FPGA. Upon programming of the 18V04 ISP PROM, the on-board PROGn push button switch (SW2) is used to initiate the Virtex-II FPGA configuration. 3.4 Slave SelectMap Interface In this mode, an external source provides the configuration bit stream and the configuration clock (CCLK) to the Virtex-II FPGA. Refer to Table 14 for setting up the Configuration Mode pins.

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Revision History

V1.0 V1.1

Initial release Update Section 2.1 heading changed Section 5 references to table 17 corrected to table 15 Figure 19 corrected Update Figure 7 and table 6 corrected Update Figure 16-18 and table 10-11 corrected Table 15 corrected for PC Pull-up settings Removed P160 Module Documentation (Now as separate documents) Update Corrected 24MHz/100MHz wording in section 2.4 Updated Memec Design logo Update General updates, minor wording changes Updated section 2.3 to Micron DDR memory device Updated Figure 3 to Micron part number Updated Section 2.4 for user clock socket Updated Table 2 for user clock input Updated Section 2.11 for Parallel IV cable support Deleted Table 7 JTAG Signals Added Figure 9 Parallel IV Cable Update Table 15

12/5/01 12/19/01

V1.2

12/30/01

V1.3

2/14/02

V1.4

5/29/02

V3.0

12/2/02

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Appendix A Virtex-II System Board Schematics

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10
VOLTAGE INPUT JACK
JP1 1 2 PJ-002A-SMT

8
REGULATION

6
LED

4
TEST LOOP
VIN

2
GROUND TEST LOOPS

VRAW SW1 1 VRAW 2

JP2 R1 750 VIN JP3 3 JP5 DS1 LGT670-HK VIN Test Point Loop - Red Test Point Loop - Black Test Point Loop - Black

VIN
1X2 Header

JP4 1 2 1X2 VRAW SPDT Slide 6A

3.3V VIN JP6 1 1X2 JP7 1X2 Header 1 2 1X2 3.3V NE1 SHUNT-LO-CL 2 C1 2.2u + C2 150u 1 2 3 4 5 U1 EN IN GND OUTPUT FB/PG TPS76633KTT LITTLE RUBBER FEET

5A

HS

R2 330

3.3V JP8 Test Point Loop - Red

NE9

Little Rubber Feet -Thick

3.3V
F

NE10 Little Rubber Feet -Thick NE11 Little Rubber Feet -Thick

Pmax = (Tj-Ta)/Rth = (125 - 50) / 25C/W = 3W I = P/V = 3/(5-3.3) = 3/1.7 = 1765mA

DS2 LGT670-HK

NE12 Little Rubber Feet -Thick

3.3V

F
2.5V

Pmax = (Tj-Ta)/Rth = (125 - 50) / 30C/W = 2.5W

VIN

I = P/V = 2.5/(5-2.5) = =2.5/2.5 = 1A

U2 REG1117FA-2.5 DDPAK JP9

R3 130 2.5V JP11 C4 2.2u 2.5V DS3 LGT670-HK Test Point Loop - Red

2.5V
E

JP10 1X2 Header 1 2 1X2 NE2 2.5V

1 1X2

2 C3 2.2u

VIN

VOUT HS GND 3

2 4 HS2 TP2

SHUNT-LO-CL

3.3V

VIN U3 JP12 1 2 1X2 C6 2.2u 1 2 1X2 1.5V 1.5V R2 1.5V 1 1 2 3 4 5 + C5 150u EN IN GND OUTPUT FB/PG TPS75515KTT

R4 330

5A

HS

DS4

D
3 LGT670-HK 1.5V JP14 Q1 BCR133 Test Point Loop - Red

1.5V

JP13 1X2 Header

R1

C
NE3 SHUNT-LO-CL

3.3V

B
R65 3

1.25V

10k 4 1% C77 .1u 5

U13 TLV431ACDBV

C79 .1u 1.25V

2V1000 MICROBLAZE BOARD

POWER

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 1 of 9

MemecBoard
<OrgAddr1> <OrgAddr2> <OrgAddr3> <OrgAddr4>

10

10
BANK 0 - USER IO / EXPANSION VBANK0

8
BANK 1 - DDR / DDR CLOCK

7
2.5V 1.25V

5
BANK 2 - EXPANSION VBANK2 1.25V

3
BANK 3 - DDR

2
2.5V 1.25V

1.25V

U5A

Bank 0

U5B

Bank 1

U5C

Bank 2

T17 R17 P16 N16 M16

G11 G10 G9 F8 F7

G14 G13 G12 F16 F15

L16 K16 J16 H17 G17

U5D

Bank 3

VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0

VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1

VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2

DIP1 DIP2 DIP3 DIP4 DIP5 DIP6 DIP7 DIP8 FPGA.RESETn PUSH.USER.2 DISPLAY.2D DISPLAY.2E PUSH.USER.1 TXD LIO.A33 LIO.A35 CLK.CAN2 CLK.CAN1

B4 A4 C4 C5 B5 A5 D6 C6 B6 A6 E7 E8 D7 C7 B7 D11 C11 B11 A11

IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0 IO_L03N_0/VRP_0 IO_L03P_0/VRN_0 IO_L04N_0/VREF_0 IO_L04P_0

*2*IO_L22P_0 *2*IO_L24N_0 *2*IO_L24P_0 *1*IO_L49N_0 *1*IO_L49P_0 *1*IO_L51N_0 *4*IO_L51P_0/VREF_0 *1*IO_L52N_0 *1*IO_L52P_0 *1*IO_L54N_0 *1*IO_L54P_0 IO_L91N_0/VREF_0 IO_L91P_0 IO_L92N_0 IO_L92P_0 IO_L93N_0 IO_L93P_0 IO_L94N_0/VREF_0 IO_L94P_0

A7 D8 C8 B8 A8 E9 F9 D9 C9 B9 A9 E10 F10 D10 C10 B10 A10 E11 F11

RXD LIO.A39 LIO.A37 DISPLAY.2C DISPLAY.2B DISPLAY.2G DISPLAY.1D DISPLAY.1A DISPLAY.1B DISPLAY.2A LED.USER DISPLAY.2F DISPLAY.1E DISPLAY.1F DISPLAY.1G LIO.B40 LIO.B39 LIO.B38 DISPLAY.1C

C12 B12 A13 B13 C13 D13 E13 E14 A14 B14 C14 D14 A15 B15 C15 D15
clock feedback CLK.CAN3 MEM.CLK MEM.CLK n MEM.CLK

IO_L94N_1 IO_L94P_1/VREF_1 IO_L93N_1 IO_L93P_1 IO_L92N_1 IO_L92P_1 IO_L91N_1 IO_L91P_1/VREF_1

*2*IO_L24N_1 *2*IO_L24P_1 *2*IO_L22N_1 *2*IO_L22P_1 *3*IO_L21N_1/VREF_1 *2*IO_L21P_1 IO_L06N_1 IO_L06P_1 IO_L05N_1 IO_L05P_1 IO_L04N_1 IO_L04P_1/VREF_1 IO_L03N_1/VRP_1 IO_L03P_1/VRN_1 IO_L02N_1 IO_L02P_1 IO_L01N_1 IO_L01P_1

F14 E15 A16 B16 C16 D16 E16 E17 A17 B17 C17 D17 A18 B18 C18 D18 A19 B19
MEM.A3 MEM.A2

LIO.A19 LIO.B19 LIO.B37 LIO.B36 LIO.B18 LIO.A17 LIO.B28 LIO.B29 LIO.B17 LIO.B16 LIO.A31 LIO.A29 LIO.A15 LIO.B15 LIO.B35 LIO.B34 LIO.A27 LIO.B27 LIO.B14 LIO.A13 LIO.B26 LIO.A25

C21 C22 E18 F18 D21 D22 E19 E20 E21 E22 F19 F20 F21 F22 G18 H18 G19 G20 G21 G22 H19 H20

IO_L01N_2 IO_L01P_2 IO_L02N_2/VRP_2 IO_L02P_2/VRN_2 IO_L03N_2 IO_L03P_2/VREF_2 IO_L04N_2 IO_L04P_2

IO_L46N_2 IO_L46P_2 IO_L48N_2 IO_L48P_2 *1*IO_L49N_2 *1*IO_L49P_2 *1*IO_L51N_2 *4*IO_L51P_2/VREF_2 *1*IO_L52N_2 *1*IO_L52P_2 *1*IO_L54N_2 *1*IO_L54P_2 IO_L91N_2 IO_L91P_2 IO_L93N_2 IO_L93P_2/VREF_2 IO_L94N_2 IO_L94P_2 IO_L96N_2 IO_L96P_2

H21 H22 J17 J18 J19 J20 J21 J22 K17 K18 K19 K20 K21 K22 L17 L18 L19 L20 L21 L22

LIO.B13 LIO.B12 LIO.B32 LIO.B33 LIO.B25 LIO.B24 LIO.A11 LIO.B11 LIO.B31 LIO.B22 LIO.A23 LIO.B23 LIO.B10 LIO.A9 LIO.B30 LIO.B20 LIO.B21 LIO.A21 LIO.B9 LIO.B8

MEM.BS0 MEM.A9 MEM.A8 MEM.A7 MEM.A4 MEM.CSn MEM.RASn MEM.A12 MEM.CKE MEM.A11 MEM.A5 MEM.CASn MEM.LDQS MEM.UDQS MEM.WEn MEM.LDM MEM.D8 MEM.D9 MEM.A6

M21 M20 M19 M18 M17 N17 N22 N21 N20 N19 N18 P18 P22 P21 P20 P19 R22 R21 R20 R19 R18 P17

VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3

IO_L96N_3 IO_L96P_3 IO_L94N_3 IO_L94P_3 IO_L93N_3/VREF_3 IO_L93P_3 IO_L91N_3 IO_L91P_3

IO_L43N_3 IO_L43P_3 *2*IO_L24N_3 *2*IO_L24P_3 *2*IO_L22N_3 *2*IO_L22P_3 *3*IO_L21N_3/VREF_3 *2*IO_L21P_3 *2*IO_L19N_3 *2*IO_L19P_3 IO_L06N_3 IO_L06P_3 IO_L04N_3 IO_L04P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3/VRP_3 IO_L02P_3/VRN_3 IO_L01N_3 IO_L01P_3

T22 T21 T20 T19 U22 U21 U20 U19 T18 U18 V22 V21 V20 V19 W22 W21 Y22 Y21 W20 AA20

MEM.UDM MEM.D7 MEM.D10 MEM.D11 MEM.D6 MEM.D5 MEM.D12

IO_L05N_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L21N_0*2* IO_L21P_0/VREF_0*3* IO_L22N_0*2* IO_L95N_0/GCLK7P IO_L95P_0/GCLK6S IO_L96N_0/GCLK5P IO_L96P_0/GCLK4S

IO_L54N_1*1* IO_L54P_1*1* IO_L52N_1*1* IO_L52P_1*1* IO_L51N_1/VREF_1*4* IO_L51P_1*1* IO_L49N_1*1* IO_L49P_1*1* IO_L96N_1/GCLK3P IO_L96P_1/GCLK2S IO_L95N_1/GCLK1P IO_L95P_1/GCLK0S

MEM.A1 MEM.A0

IO_L06N_2 IO_L06P_2 IO_L19N_2*2* IO_L19P_2*2* IO_L21N_2*2* IO_L21P_2/VREF_2*3* IO_L22N_2*2* IO_L22P_2*2* IO_L24N_2*2* IO_L24P_2*2* IO_L43N_2 IO_L43P_2 IO_L45N_2 IO_L45P_2/VREF_2

IO_L54N_3*1* IO_L54P_3*1* IO_L52N_3*1* IO_L52P_3*1* IO_L51N_3/VREF_3*4* IO_L51P_3*1* IO_L49N_3*1* IO_L49P_3*1* IO_L48N_3 IO_L48P_3 IO_L46N_3 IO_L46P_3 IO_L45N_3/VREF_3 IO_L45P_3

MEM.D4 MEM.D3 MEM.D13 MEM.D14 MEM.D2 MEM.D1 MEM.D0 MEM.D15

F12 F13 E12 D12

MEM.A10/AP MEM.BS1

*#* See Chart on Core Power Symbol.

*#* See Chart on Core Power Symbol.

*#* See Chart on Core Power Symbol.

*#* See Chart on Core Power Symbol.

BANK 4 - EXPANSION / SELECTMAP

BANK 5 - LVDS CLOCKS / SELECTMAP / EXPANSION VBANK4 VBANK5

BANK 6 - LVDS RECEIVE VBANK.LVDS

BANK 7 - LVDS TRANSMIT

F
VBANK.LVDS

3.3V U16 U15 T14 T13 T12 U8 U7 T11 T10 T9 L7 K7 J7 H6 G6 T6 R6 P7 N7 M7

VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4

VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5

VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6

SM.DOUT/BUSY INITn FPGA.BITSTREAM

SM.D1 SM.D2 SM.D3 RIO.A1 RIO.A7 RIO.A9 RIO.A3 RIO.A5 RIO.A15 RIO.A11 RIO.B16 RIO.B14 RIO.A18 RIO.A20

AB19 AA19 V18 V17 W18 Y18 AA18 AB18 W17 Y17 AA17 AB17 V16 V15 W16 W12 Y12 AA12 AB12

IO_L01N_4/DOUT *3*IO_L21P_4/VREF_4 *2*IO_L22N_4 IO_L01P_4/INIT_B IO_L02N_4/D0 *2*IO_L22P_4 *2*IO_L24N_4 IO_L02P_4/D1 IO_L03N_4/D2/VRP_4 *2*IO_L24P_4 IO_L03P_4/D3/VRN_4 *1*IO_L49N_4 IO_L04N_4/VREF_4 *1*IO_L49P_4 IO_L04P_4 *1*IO_L51N_4 IO_L05N_4 *4*IO_L51P_4/VREF_4 *1*IO_L52N_4 IO_L05P_4 IO_L06N_4 *1*IO_L52P_4 *1*IO_L54N_4 IO_L06P_4 IO_L19N_4*2* *1*IO_L54P_4 IO_L19P_4*2* IO_L91N_4/VREF_4 IO_L91P_4 IO_L21N_4*2* IO_L95N_4/GCLK3S IO_L95P_4/GCLK2P IO_L96N_4/GCLK1S IO_L96P_4/GCLK0P IO_L92N_4 IO_L92P_4 IO_L93N_4 IO_L93P_4 IO_L94N_4/VREF_4 IO_L94P_4

Y16 AA16 AB16 W15 Y15 AA15 AB15 U14 V14 W14 Y14 AA14 AB14 U13 V13 W13 Y13 AA13 AB13 U12 V12

RIO.A13 RIO.A2 RIO.A4 RIO.A17 RIO.B2 RIO.A6 RIO.A8 RIO.A21 RIO.A19 RIO.B4 RIO.B6 RIO.A10 RIO.A12 RIO.A23 RIO.B12 RIO.B8 RIO.B10 RIO.A14 RIO.A16 RIO.A25 RIO.B18

RIO.A27 RIO.A29

RIO.B22 RIO.B24 RIO.B20 RIO.A33 RIO.A22 RIO.A24 RIO.B26 RIO.B28 RIO.A26 RIO.A28 RIO.B30 RIO.B32

U11 U10 AB10 AA10 Y10 W10 V10 V9 AB9 AA9 Y9 W9 AB8 AA8 Y8 W8 AA11 Y11 W11 V11

IO_L94N_5 IO_L94P_5/VREF_5 IO_L93N_5 IO_L93P_5 IO_L92N_5 IO_L92P_5 IO_L91N_5 IO_L91P_5/VREF_5

*2*IO_L24N_5 *2*IO_L24P_5 *2*IO_L22N_5 *2*IO_L22P_5 *3*IO_L21N_5/VREF_5 *2*IO_L21P_5 *2*IO_L19N_5 *2*IO_L19P_5

U9 V8 AB7 AA7 Y7 W7 AB6 AA6 Y6 W6 V7 V6 AB5 AA5 Y5 W5 AB4 AA4 Y4 AA3

RIO.A31 RIO.A35 RIO.A30 RIO.A32 RIO.B34 RIO.B36 RIO.A34 RIO.A36 RIO.B38 RIO.B40 RIO.A37 RIO.A39 RIO.A38 RIO.A40 SM.D4 SM.D5 SM.D6 SM.D7 SM.RDWRn SM.CSn

LVDSIN9P LVDSIN9N
LVDSINCTRLP LVDSINCTRLN

LVDSIN8P LVDSIN8N LVDSIN16P LVDSIN16N LVDSIN7P LVDSIN7N LVDSIN6P LVDSIN6N

V5 U5 Y2 Y1 V4 V3 W2 W1 U4 U3 V2 V1 U2 U1 T5 R5 T4 T3 T2 T1 R4 R3

IO_L01P_6 IO_L01N_6 IO_L02P_6/VRN_6 IO_L02N_6/VRP_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L04P_6 IO_L04N_6

IO_L46P_6 IO_L46N_6 IO_L48P_6 IO_L48N_6 *1*IO_L49P_6 *1*IO_L49N_6 *1*IO_L51P_6 *4*IO_L51N_6/VREF_6 *1*IO_L52P_6 *1*IO_L52N_6 *1*IO_L54P_6 *1*IO_L54N_6 IO_L91P_6 IO_L91N_6 IO_L93P_6 IO_L93N_6/VREF_6 IO_L94P_6 IO_L94N_6 IO_L96P_6 IO_L96N_6

R2 R1 P6 P5 P4 P3 P2 P1 N6 N5 N4 N3 N2 N1 M6 M5 M4 M3 M2 M1

LVDSIN4P LVDSIN4N LVDSINSTAT1P LVDSINSTAT1N LVDSIN13P LVDSIN13N LVDSIN3P LVDSIN3N LVDSINSTAT2P LVDSINSTAT2N LVDSIN12P LVDSIN12N LVDSIN2P LVDSIN2N LVDSIN10P LVDSIN10N LVDSIN11P LVDSIN11N LVDSIN1P LVDSIN1N

LVDSOUT10P LVDSOUT10N LVDSOUT11P LVDSOUT11N LVDSOUT3P LVDSOUT3N LVDSOUT9P LVDSOUT9N LVDSOUT16P LVDSOUT16N LVDSOUT15P LVDSOUT15N LVDSOUT2P LVDSOUT2N LVDSOUT8P LVDSOUT8N LVDSOUT1P LVDSOUT1N LVDSOUT7P LVDSOUT7N LVDSOUT14P LVDSOUT14N

L2 L3 L4 L5 K1 K2 K3 K4 L6 K6 K5 J5 J1 J2 J3 J4 H1 H2 H3 H4 J6 H5

VCCO_7 VCCO_7 VCCO_7 VCCO_7 VCCO_7

R7 330 1%

U5E

Bank 4

U5F

Bank 5

U5G

Bank 6

U5H

Bank 7

IO_L96P_7 IO_L96N_7 IO_L94P_7 IO_L94N_7 IO_L93P_7/VREF_7 IO_L93N_7 IO_L91P_7 IO_L91N_7

IO_L43P_7 IO_L43N_7 *2*IO_L24P_7 *2*IO_L24N_7 *2*IO_L22P_7 *2*IO_L22N_7 *3*IO_L21P_7/VREF_7 *2*IO_L21N_7 *2*IO_L19P_7 *2*IO_L19N_7 IO_L06P_7 IO_L06N_7 IO_L04P_7 IO_L04N_7 IO_L03P_7/VREF_7 IO_L03N_7 IO_L02P_7/VRN_7 IO_L02N_7/VRP_7 IO_L01P_7 IO_L01N_7

G1 G2 G3 G4 F1 F2 F3 F4 G5 F5 E1 E2 E3 E4 D1 D2 C1 C2 E5 E6

LVDSOUTCTRLP LVDSOUTCTRLN

LVDSOUT6P LVDSOUT6N LVDSOUTSTAT2P LVDSOUTSTAT2N LVDSOUT5P LVDSOUT5N LVDSOUT13P LVDSOUT13N LVDSOUTSTAT1P LVDSOUTSTAT1N LVDSOUT4P LVDSOUT4N
LVDSOUTSTATCLKP LVDSOUTSTATCLK N LVDSOUTCLKP LVDSOUTCLKN

IO_L54N_5*1* IO_L06N_5 IO_L54P_5*1* IO_L06P_5 IO_L52N_5*1* IO_L05N_5 IO_L52P_5*1* IO_L05P_5 IO_L51N_5/VREF_5*4* IO_L04N_5 IO_L51P_5*1* IO_L04P_5/VREF_5 IO_L49N_5*1* IO_L03N_5/D4/VRP_5 IO_L49P_5*1* IO_L03P_5/D5/VRN_5 IO_L96N_5/GCLK7S IO_L96P_5/GCLK6P IO_L95N_5/GCLK5S IO_L95P_5/GCLK4P IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B

IO_L06P_6 IO_L06N_6 IO_L19P_6*2* IO_L19N_6*2* IO_L21P_6*2* IO_L21N_6/VREF_6*3* IO_L22P_6*2* IO_L22N_6*2* IO_L24P_6*2* IO_L24N_6*2* IO_L43P_6 IO_L43N_6 IO_L45P_6 IO_L45N_6/VREF_6

IO_L54P_7*1* IO_L54N_7*1* IO_L52P_7*1* IO_L52N_7*1* IO_L51P_7/VREF_7*4* IO_L51N_7*1* IO_L49P_7*1* IO_L49N_7*1* IO_L48P_7 IO_L48N_7 IO_L46P_7 IO_L46N_7 IO_L45P_7/VREF_7 IO_L45N_7

LVDSINCLKN LVDSINCLKP LVDSINSTATCLKN LVDSINSTATCLKP

LVDSIN15P LVDSIN15N LVDSIN5P LVDSIN5N LVDSIN14P LVDSIN14N

LVDSOUT12P LVDSOUT12N

*#* See Chart on Core Power Symbol.

*#* See Chart on Core Power Symbol.

*#* See Chart on Core Power Symbol.

*#* See Chart on Core Power Symbol.

CONFIGURATION BLOCK

POWER BLOCK

P160 CLOCK TERMINATION

VBANK0

3.3V

3.3V JP15 1 3.3V 3.3V 1X2 2

3.3V

1.5V

VALUES TBD
R70 3.3k R71 3.3k

AB11 AA22 AA1 M22 L1 B22 B1 A12

R8 3.3k R9 3.3k R10 3.3k R11 3.3k R12 3.3k 1%

U17 U6 T16 T15 T8 T7 R16 R7 H16 H7 G16 G15 G8 G7 F17 F6

A21

U5J U5I
A2 Y19 AB20 M0 M1 M2
TCK TDI.FPGA TDO.FPGA.to.TDO.P ORT TMS

Core Power

LIO.A33 LIO.A35

C
VBANK4

VBATT

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

Configuration
PROG_B CCLK DONE M0 M1 M2 TCK TDI TDO TMS HSWAP_EN PWRDWN_B RSVD DXN DXP A22 A1 AB22 AB1 AA21 AA2 Y20 Y3 W19 W4 P14 P13 GND GND GND GND GND GND GND GND GND GND GND GND

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

VCCINT = 1.5V

Mode
Master-serial Master-serial Slave Serial Slave Serial Master SelectMAP Master SelectMAP Slave SelectMAP Slave SelectMAP Boundary-scan Boundary-scan

Pull-ups Yes No Yes No Yes No Yes No Yes No

PROGRAMn FPGA.CCLK DONE

Notes: 1000 *1* *2* *3* *4* IO IO VREF VREF 500 IO NC NC VREF 250 NC NC NC NC

AB2 W3 AB3 C19 D3 D20 B20 B3 AB21 A20 D5 A3

GND GND GND GND GND GND GND GND GND GND GND GND

2 4 6 8

J14 J13 J12 J11 J10 J9 D19 D4 C20 C3 B21 B2

R72 3.3k
RIO.B16 RIO.B14 RIO.A18 RIO.A20

R73 3.3k

R74 3.3k

R75 3.3k

C129 .1u

C130 .1u

C131 .1u

C132 .1u

C133 .1u

C134 .1u

012 3 1 3 5 7

2X4
Indicates jumper installed Indicates jumper removed FPGA.PWRDWN

M3 PWRDWN

P12 P11 P10 P9 N14 N13 N12 N11 N10 N9 M14 M13 M12 M11 M10 M9 L14 L13 L12 L11 L10 L9 K14 K13 K12 K11 K10 K9

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

J1

NE4 NE5 NE6

SHUNT-LO-CL SHUNT-LO-CL

R76 3.3k

R77 3.3k

R78 3.3k

R79 3.3k

R80 3.3k

R81 3.3k

JP16

1X2 SHUNT-LO-CL SHUNT-LO-CL 1

NE7

2V1000 MICROBLAZE BOARD

FPGA

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 2 of 9

MemecBoard
<OrgAddr1> <OrgAddr2> <OrgAddr3> <OrgAddr4>

10

10
XC18 PROM

6
PROGRAM PUSHBUTTON

4
PROGRAMMING DONE LED 3.3V

2
FPGA POWER SELECT

3.3V R14 330

2.5V

3.3V

H
DS5
DONE

3.3V 3.3V 3.3V

R13 3.3k Q2

LGT670-HK

3 2

JP18

8 16 26 36

17 35 38

C11 34 33 40 29 42 27 9 25 14 19 23 22 C12 .1u .1u

B SW2 Tl1105SP

PROGRAMn DONE 1 R1 1 R2

44 JTAG VCCO VCCO VCCO VCCO VCC VCC VCC 1 TDI.PROM TMS TCK TDO.PROM 3 5 7 31 10 13 15 21 43 TDI TMS TCK TDO

1X3 VBANK0

G
R15 PROGRAMn 0 1%

DONE FPGA.CCLK

GND GND GND GND

D0/DATA D1 U6 D2 D3 XC18V04VQ44C CF D4 OE/RESET D5 CE D6 CEO D7 CLK 6 18 28 41

FPGA.BITSTREAM
SM.D1 SM.D2 SM.D3 SM.D4 SM.D5 SM.D6 SM.D7

A'

B' BCR133 2

3.3V 3 2 1 PROM JTAG BYPASS JP26

11 12 INITn

1X3 VBANK2

3 2 1

JP28

F
PROM IN CHAIN 1X3 NE8 SHUNT-LO-CL TDI.PROM JP22 1 2 3 2 TDI.PORT.to.TDI.PROM TDI.FPGA 1 1X4 RA 4 PROM NOT IN CHAIN TDO.PROM 3 JP19

1X3 VBANK4

E
NE18 SHUNT-LO-CL NE19 SHUNT-LO-CL 3 JP20

JTAG CHAIN DIAGRAM

CLOCKS 2.5V 1 3.3V 3.3V 3.3V CLK.CAN3

1X3 VBANK5

TDO.FPGA.to.TDO.PORT

14

PROM

FPGA

EN GND 24MHz

VCC OUT

VCC

OUT

CLK.CAN1

OUT

1X2

11

JP23

Y3

C127 .1u

C125 .01u 6 0603

D
Y5 JP21

ENABLE

half full GND GND Clock Can

3 2 1

TDI.PROM TDI TDI.PORT.to.TDI.PROM TDO TDI.FPGA TDO.PROM JP22 JP24 2 1X2 2 GND 100MHz OUT 3 CLK.CAN2 1 1 Y4 EN VCC 4 C128 .1u TDI TDO 3.3V 3.3V 3.3V

1X3 VBANK.LVDS

C126 .01u 6 0603

C
2.5V 2.5V NE13 SHUNT-LO-CL C123 .1u C124 .01u 6 0603 NE14 SHUNT-LO-CL NE15 SHUNT-LO-CL NE16 SHUNT-LO-CL NE17 SHUNT-LO-CL

JTAG PORT

SELECTMAP PORT JP27

FPGA RESET CIRCUIT

VBANK0 1.5V 1.5V

PIV PORT 3.3V

B
J2 1 VCC 2 GND 3 NC 4 TCK 5 TDO 6 TDI 7 TMS JTAG7 RA

2 3.3V 1X2 RA R43 10k 1% J3

SM.CSn

1 R69 3.3k FPGA.RESETn 2 4 6 8 10 12 14 16

FPGA.BITSTREAM SM.D1 SM.D2 SM.D3 SM.D4 SM.D5 SM.D6 SM.D7

JP29 U11 1 2 3 RESET GND RESET TPS3125 VDD MR 5 4 PUSH.RESETn A R16 3.3k 1% B SW3 1.5V R1 1 C80 .1u Q3 BCR133 A' B' Tl1105SP 1 3 5 7 9 11 13 GND GND GND GND GND GND GND JTAG VREF TMS TCK TDO TDI NC NC SSer VREF PROG CCLK DONE DIN NC INIT 2 4 6 8 10 12 14 TMS TCK TDO.FPGA.to.TDO.PORT TDI.PORT.to.TDI.PROM

TCK TDO.FPGA.to.TDO.PORT TDI.PORT.to.TDI.PROM TMS

DONE FPGA.CCLK INITn PROGRAMn

SM.RDWRn SM.DOUT/BUSY

1 3 5 7 9 11 13 15

CSn DIN/D0 DONE D1 CCLK D2 INITn D3 PROGRAMn D4 NC D5 RDWRn D6 DOUT/BUSY D7 SelectMAP RA

Parallel IV RA

R2

R60 10k 1%

2V1000 MICROBLAZE BOARD

FPGA PERIPHERALS
PUSH.RESETn

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 3 of 9

MemecBoard
<OrgAddr1> <OrgAddr2> <OrgAddr3> <OrgAddr4>

10

10

F
2.5V 2.5V 1.25V

1 18 33

3 9 15 55 61 VDDIO VDDIO VDDIO VDDIO VDDIO

MEM.A0 MEM.A1 MEM.A2 MEM.A3 MEM.A4 MEM.A5 MEM.A6 MEM.A7 MEM.A8 MEM.A9 MEM.A10/AP MEM.A11 MEM.A12 MEM.LDM MEM.UDM MEM.LDQS MEM.UDQS MEM.WEn MEM.CASn MEM.RASn MEM.BS0 MEM.BS1 MEM.CSn

29 30 31 32 35 36 37 38 39 40 28 41 42 20 47 16 51 21 22 23 26 27 24

VREF

VDD VDD VDD

49

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 LDM UDM LDQS UDQS WE CAS RAS BS0 BS1 CS

U8 TC59WM815BFT

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CLK CLK CKE NC NC NC NC NC NC NC

2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 46 45 44 14 17 19 25 43 50 53

MEM.D0 MEM.D1 MEM.D2 MEM.D3 MEM.D4 MEM.D5 MEM.D6 MEM.D7 MEM.D8 MEM.D9 MEM.D10 MEM.D11 MEM.D12 MEM.D13 MEM.D14 MEM.D15 MEM.CLK n MEM.CLK MEM.CKE

34 48 66

6 12 52 58 64

GNDIO GNDIO GNDIO GNDIO GNDIO

GND GND GND

2V1000 MICROBLAZE BOARD

DDR MEMORY

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 4 of 9

MemecBoard
<OrgAddr1> <OrgAddr2> <OrgAddr3> <OrgAddr4>

10

10
LVDS TRANSMIT

J4 LVDSOUT16P LVDSOUT15P LVDSOUT14P LVDSOUT13P LVDSOUT12P LVDSOUT11P LVDSOUT10P LVDSOUT9P LVDSOUT8P LVDSOUT7P LVDSOUT6P LVDSOUT5P LVDSOUT4P LVDSOUT3P LVDSOUT2P LVDSOUT1P 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 2X20 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 LVDSOUT16N LVDSOUT15N LVDSOUT14N LVDSOUT13N LVDSOUT12N LVDSOUT11N LVDSOUT10N LVDSOUT9N LVDSOUT8N LVDSOUT7N LVDSOUT6N LVDSOUT5N LVDSOUT4N LVDSOUT3N LVDSOUT2N LVDSOUT1N

No transmit termination required for Virtex-II

J7 LVDSOUTCLKP LVDSOUTSTATCLKP LVDSOUTSTAT1P LVDSOUTSTAT2P

LVDSOUTCTRLP

1 3 5 7 9 11 13 2X7

2 4 6 8 10 12 14

LVDSOUTCLKN LVDSOUTSTATCLKN LVDSOUTSTAT1N LVDSOUTSTAT2N

LVDSOUTCTRLN

LVDS RECEIVE

LVDSIN8P R18 100 1% LVDSIN8N

LVDSIN8P

LVDSIN16P R19 100 1%

LVDSIN16P

LVDSIN8N LVDSIN7P R20 100 1%

LVDSIN16N LVDSIN15P R21 100 1%

LVDSIN16N LVDSIN15P

LVDSIN7P

LVDSIN7N LVDSIN6P R22 100 1% LVDSIN6N LVDSIN5P R24 100 1%

LVDSIN7N LVDSIN6P

LVDSIN15N LVDSIN14P R23 100 1%

LVDSIN15N LVDSIN14P LVDSIN16N LVDSIN15N LVDSIN14N LVDSIN13N LVDSIN14N LVDSIN13P R25 100 1% LVDSIN12N LVDSIN11N LVDSIN10N LVDSIN9N LVDSIN8N LVDSIN7N LVDSIN6N LVDSIN5N LVDSIN4N LVDSIN3N LVDSIN2N LVDSIN1N J6 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 2X20 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 LVDSIN16P LVDSIN15P LVDSIN14P LVDSIN13P LVDSIN12P LVDSIN11P LVDSIN10P LVDSIN9P LVDSIN8P LVDSIN7P LVDSIN6P LVDSIN5P LVDSIN4P LVDSIN3P LVDSIN2P LVDSIN1P

LVDSIN6N LVDSIN5P

LVDSIN14N LVDSIN13P

LVDSIN5N LVDSIN4P R26 100 1% LVDSIN4N LVDSIN3P R28 100 1% LVDSIN3N LVDSIN2P

LVDSIN5N LVDSIN4P

LVDSIN13N LVDSIN12P R27 100 1%

LVDSIN13N LVDSIN12P

LVDSIN4N LVDSIN3P

LVDSIN12N LVDSIN11P R29 100 1%

LVDSIN12N LVDSIN11P

LVDSIN3N LVDSIN2P R30 100 1%

LVDSIN11N LVDSIN10P R31 100 1%

LVDSIN11N LVDSIN10P

C
LVDSIN2N LVDSIN1P

C
LVDSIN10N LVDSIN9P

LVDSIN2N LVDSIN1P R32 100 1%

LVDSIN10N LVDSIN9P R33 100 1%

LVDSIN1N

LVDSIN1N

LVDSIN9N

LVDSIN9N

LVDSINCLKP

LVDSINCLKP R17 100 1%

LVDSINSTATCLKP R66 100 1%

LVDSINSTATCLKP J8 LVDSINCLKP LVDSINSTATCLKN LVDSINSTATCLKP LVDSINSTAT1P LVDSINSTAT2P 14 12 10 8 6 4 2 2X7 13 11 9 7 5 3 1 LVDSINCLKN LVDSINSTATCLKN LVDSINSTAT1N LVDSINSTAT2N
LVDSINCTRLN

B
LVDSINCLKN

LVDSINCLKN

LVDSINSTATCLKN

LVDSINSTAT1P R67 100 1% LVDSINSTAT1N

LVDSINSTAT1P

LVDSINSTAT2P R68 100 1%

LVDSINSTAT2P

LVDSINCTRLP

LVDSINSTAT1N

LVDSINSTAT2N

LVDSINSTAT2N

LVDSINCTRLP

LVDSINCTRLP R64 100 1%

A
LVDSINCTRLN

2V1000 MICROBLAZE BOARD

LVDSINCTRLN LVDS

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 5 of 9

MemecBoard
<OrgAddr1> <OrgAddr2> <OrgAddr3> <OrgAddr4>

10

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P160 SOCKET

G
2.5V VIN 3.3V 2.5V 3.3V VIN

JX1

P160 Left Header MB

JX2

P160 Right Header MB

LIO.A9 LIO.A11 LIO.A13 LIO.A15 LIO.A17 LIO.A19 LIO.A21 LIO.A23 LIO.A25

LIO.A27 LIO.A29 LIO.A31 LIO.A33 LIO.A35 LIO.A37 LIO.A39

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40

TCK GND TMS VIN TDI GND TDO 3.3V IO GND IO 2.5V IO GND IO VIN IO GND IO 3.3V IO GND IO 2.5V IO GND IO VIN IO GND IO 3.3V IO GND IO 2.5V IO GND IO VIN

DIN DOUT CCLK DONE INITn PROGRAMn NC IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40

LIO.B8 LIO.B9 LIO.B10 LIO.B11 LIO.B12 LIO.B13 LIO.B14 LIO.B15 LIO.B16 LIO.B17 LIO.B18 LIO.B19 LIO.B20 LIO.B21 LIO.B22 LIO.B23 LIO.B24 LIO.B25 LIO.B26 LIO.B27 LIO.B28 LIO.B29 LIO.B30 LIO.B31 LIO.B32 LIO.B33 LIO.B34 LIO.B35 LIO.B36 LIO.B37 LIO.B38 LIO.B39 LIO.B40

RIO.A1 RIO.A2 RIO.A3 RIO.A4 RIO.A5 RIO.A6 RIO.A7 RIO.A8 RIO.A9 RIO.A10 RIO.A11 RIO.A12 RIO.A13 RIO.A14 RIO.A15 RIO.A16 RIO.A17 RIO.A18 RIO.A19 RIO.A20 RIO.A21 RIO.A22 RIO.A23 RIO.A24 RIO.A25 RIO.A26 RIO.A27 RIO.A28 RIO.A29 RIO.A30 RIO.A31 RIO.A32 RIO.A33 RIO.A34 RIO.A35 RIO.A36 RIO.A37 RIO.A38 RIO.A39 RIO.A40

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

GND IO VIN IO GND IO 3.3V IO GND IO 2.5V IO GND IO VIN IO GND IO 3.3V IO GND IO 2.5V IO GND IO VIN IO GND IO 3.3V IO GND IO 2.5V IO GND IO VIN IO

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40

RIO.B2 RIO.B4 RIO.B6 RIO.B8 RIO.B10 RIO.B12 RIO.B14 RIO.B16 RIO.B18 RIO.B20 RIO.B22 RIO.B24 RIO.B26 RIO.B28 RIO.B30 RIO.B32 RIO.B34 RIO.B36 RIO.B38 RIO.B40

2V1000 MICROBLAZE BOARD

P160 SOCKET

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 6 of 9

MemecBoard
Suite 540, 1212 31st Ave. NE Calgary, Alberta Canada T2E 7S8

10

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DIP SWITCH

6
SERIAL PORT

3.3V VBANK0

H
C13 .1u 3.3V JDR1 1 U10 C14 .1u 1 2 3 4 5 6 7 8 C16 .1u C17 .1u EN C1+ V+ C1C2+ C2VRIN MAX3221 FORCEOFF VCC GND DOUT FORCEON DIN INVALID ROUT 16 15 14 13 12 11 10 9 6 2 7 3 8 4 9 5

R34 3.3k 1% R38 3.3k 1%

R35 3.3k 1% R39 3.3k 1%

R36 3.3k 1% R40 3.3k 1%

R37 3.3k 1%

DCD DSR RD RTS TD CTS DTR RI GND USE STANDARD STRAIGHT-THRU CABLE WHEN CONNECTING TO A PC

R41 3.3k 1%

C15 .1u

SW4
DIP1 DIP2 DIP3 DIP4 DIP5 DIP6 DIP7 DIP8

1 2 3 4 5 6 7 8 SWDIP08

16 15 14 13 12 11 10 9

DB9 RA

TXD RXD

F
LEDs SEVEN SEGMENT DISPLAYS
DISPLAY.2A DISPLAY.2B DISPLAY.2C DISPLAY.2D DISPLAY.2E DISPLAY.2F DISPLAY.2G LED.USER DISPLAY.1A DISPLAY.1B DISPLAY.1C DISPLAY.1D DISPLAY.1E DISPLAY.1F DISPLAY.1G

F
PUSHBUTTONS

VBANK0

VBANK0

R42 3.3k 1%

R53 3.3k 1%

E
B SW6 Tl1105SP

B SW5

R44 130 1% R45 130 1% DS7 R54 130 1% R46 130 1% R47 130 1% R55 130 1% R48 130 1% R58 130 1% R49 130 1% R56 130 1% R50 130 1% R51 130 1% R57 130 1% R52 130 1% R59 130 1%
PUSH.USER.1

Tl1105SP A' B' A' B'

LGT670-HK

10 DD1

10 DD2

PUSH.USER.2

Resistor Value Calculations Rupper = (3.3V - 2) / 5mA = 260 ohms Rlower = (2.5V - 2) / 5mA = 100 ohms Let R = 130 ohms

RED CC

f g

10

CC

CC

DP

DP

RED CC

2V1000 MICROBLAZE BOARD

USER IO

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 7 of 9

MemecBoard
Suite 540, 1212 31st Ave. NE Calgary, Alberta Canada T2E 7S8

10
FPGA Core Decoupling 1.5V 1.5V 1.5V 1.5V

7
FPGA IO Decoupling

4
FPGA Voltage Reference Decoupling

1.5V

1.5V

1.5V

1.5V

VBANK0

VBANK0

VBANK0

VBANK0

VBANK0 1.25V 1.25V 1.25V

H
C18 22n C19 22n C20 22n C21 22n C81 .22u 6 0402 C82 .22u 6 0402 C83 .22u 6 0402 C84 .22u 6 0402 C22 22n C23 22n C24 .22u 6 0402 C85 2.2u 10 1206 + C86 100u 6.3 C38 22n C39 22n C87 22n

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

VBANK.LVDS VBANK.LVDS VBANK.LVDS VBANK.LVDS VBANK.LVDS VBANK.LVDS VBANK.LVDS VBANK.LVDS VBANK.LVDS VBANK.LVDS 1.25V 1.25V

G
C29 22n C30 22n C31 22n C32 22n

C88 2.2u 10 1206

C89 2.2u 10 1206

C33 22n

C34 22n

C35 22n

C90 22n

C91 22n

C92 .22u 6 0402

C93 .22u 6 0402

C94 2.2u 10 1206

C95 2.2u 10 1206

+ C96 100u 6.3

G
C97 .22u 6 0402 C98 .22u 6 0402

VBANK2

VBANK2

VBANK2

VBANK2

VBANK2

1.5V

1.5V C40 22n C41 22n

F
+ C101 100u 6.3 + C102 100u 6.3

C42 .22u 6 0402

C99 2.2u 10 1206

Memory Decoupling + C100 100u 6.3 2.5V 2.5V 2.5V 2.5V

C46 .1u 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V

C47 .1u

C48 .1u

C49 .1u

FPGA AUX/Battery Decoupling

C50 22n

C51 22n

C52 22n

C103 22n

C104 22n

C105 .22u 6 0402

C106 .22u 6 0402

C107 2.2u 10 1206

C108 2.2u 10 1206

+ C109 100u 6.3

2.5V

2.5V

2.5V

2.5V

C53 .1u VBANK4 3.3V 3.3V 3.3V 3.3V VBANK4 VBANK4 VBANK4 VBANK4

C54 .1u

C55 .1u

C56 .1u

C57 22n C60 C61 22n C62 22n C112 22n

C58 22n

C59 .22u 6 0402

C110 2.2u 10 1206

+ C111 100u 6.3

22n

1.25V

VBANK5 3.3V 3.3V

VBANK5

VBANK5

VBANK5

VBANK5

C64 .1u

C65 22n C115 .22u 6 0402 C116 .22u 6 0402

C66 22n

C67 .22u 6 0402

C113 2.2u 10 1206

+ C114 100u 6.3

3.3V

3.3V

C117 2.2u 10 1206

+ C118 100u 6.3

2V1000 MICROBLAZE BOARD

DECOUPLING

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 8 of 9

MemecBoard
<OrgAddr1> <OrgAddr2> <OrgAddr3> <OrgAddr4>

10

10

REV2

REV3

CHANGED 1.5 DUAL REGULATORS TO SINGLE DEVICE

CHANGED 3.3V REGULATORS PER TI GUIDE ADDED DECOUPLING CAPACITORS TO OSCILLATORS INCREASED FPGA DECOUPLING ADDED OSCILLATOR SOCKET ADDED PARALLEL IV PORT ADDED P160 CLOCK TERMINATION

2V1000 MICROBLAZE BOARD

HISTORY

A
Last Modified Friday, October 11, 2002 Rev Size 3 C Sheet Designer Jim Elliott 9 of 9

MemecBoard
<OrgAddr1> <OrgAddr2> <OrgAddr3> <OrgAddr4>

10