IEEE Transactions on Power Delivery, Vol. 13, No.

4, October 1998

1453

UPFC - Unified Power Flow Controller: Theory, Modeling, and Applications

Kalyan K. Sen, Member, IEEE Eric J. Stacey Westinghouse Electric Corporation 1310 Beulah Road
Pittsburgh, PA 15235, USA
Abstract - This paper describes the theory and the modeling technique of a Flexible Alternating Current Transmission Systems (FACTS) device, namely, Unified Power Flow Controller (UPFC) using an Electromagnetic Transients Program (EMTP) simulation package. The UPFC, in this paper, consists of two solid-state voltage source inverters which are connected through a common DC link capacitor. Each inverter is coupled with a transformer at its output. The first voltage source inverter, known as STATic Synchronous COMpensator (STATCOM), injects an almost sinusoidal current, of variable magnitude, at the point of connection. The second voltage source inverter, known as Static Synchronous Series Compensator (SSSC) injects an almost sinusoidal voltage, of variable magnitude, in series with the transmission line. This injected voltage can be at any angle with respect to the line current. The exchanged real power at the terminals of one inverter with the line flows to the terminals of the other inverter through the common DC link capacitor. In addition, each inverter can exchange reactive power at its terminals independently. The functionalities of the models have been verified.

(Fig. Ib). The transmission lines sending-end voltage, the receiving-end voltage,

v,, by an angle 6 .

vs , leads

The resulting

current in the line is 1 and the real and reactive power flow at the receiving end are P, and Q,, respectively. With an injection of vdq in series with the transmission line, the transmission lines sending-end voltage, Vo ,still leads the receiving-endvoltage, 7 , ., but by a different angle 6 (Fig. IC). The resulting line current and - the amount of power flow change. With a larger amount of vdq injected in series with the transmission h e , the transmission lines sending-end voltage, To, now lags the receiving-end voltage, F,. ,by an angle 6 (Fig. Id). The resulting line current and the power flow now reverse. With this background, a set of power flow controllers will be described. The objective in this paper is to describe the fundamentals of a UPFC and its modeling technique using an Electromagnetic Transients Program (EMTP) simulation package.

Keywords - AC transmission, FACTS, power flow controller, power converter, inverter, thyristor, GTO, etc.

I. INTRODUCTION Electric power flow through an alternating current transmission line is a function of the line impedance, the magnitudes of the sending-end and receiving-end voltages, and the phase angle between these voltages. Essentially, the power flow is dependent on the voltage across the line impedance. Fig. l a shows a single line diagram of a simple transmission line with an inductive reactance, &, and a series insertion voltage, v d q , connecting a
sending-end voltage source
-

vs and a receiving-endvoltage source,

Fig. 1 A Unified Power Flow Controller Operating in a Voltage Injection Mode and the Related Phasor Diagrams

V,. , respectively.

The voltage across the transmission line

(4

where

7 is the current in the transmission line

The voltage,

vx,across the transmission line can be changed

by changing the insertion voltage, v d q , in series with the transmission line and, consequently, the line current and the power flow in the line will change. Consider the case where vdq = 0
PE-282-PWRD-0-12-1997 A paper recommended and approved by the IEEE Transmission and Distribution Committee of the IEEE Power Engineering Society for publication in the IEEE Transactions on Power Delivery. Manuscript submitted July 31, 1997; made available for printing December 12, 1997.

Flexible Alternating Current Transmission Systems (FACTS) devices, namely STATic Synchronous COMpensator (STATCOM), Static Synchronous Series Compensator (SSSC) and Unified Power Flow Controller (UPFC), are used to control the power flow through an electrical transrnission line connecting various generators and loads at its sending and receiving ends. The UPFC, in this paper and existing references, consists of two solid-state voltage source inverters which are connected through a common DC link capacitor. Each inverter is coupled with a transformer at its output. The first inverter, known as STATic Synchronous COMpensator (STATCOM), irijects an almost sinusoidal current, of variable magnitude, at the point of connection. The second inverter, known as Static Synchronous Series Compensator (SSSC) injects an almost sinusoidal voltage, of variable magnitude, in series with the transmission h e . When the STATCOM and the SSSC operate as stand-alone: devices, they exchange almost exclusivelyreactive power at their terminals. While operating both the inverters together as a UPFC, the exchanged power at the terminals of each inverter can be reactive as well as real. The exchanged real power at the terminals of one inverter with the line flows to the terminals of the other inverter through the common DC link capacitor.

0885-8977/98/$10,00 0 1997 IEEE

1454
Fig. 2 shows a basic W F C model which consists of a STATCOM and an SSSC. The SSSC injects a voltage, Vdq, in series with the transmission line which, in turn, changes the voltage, &, across the transmission line and hence the current and the power flow through the transmission line change. The phase angle, 4, (Fig. IC, d) between the injected voltage, T d q , and the line current, f , can be between 0 and 2n. The component of the injected voltage which is in or out of phase with the line current emulates a positive or negative resistance in series with the transmission line. The remaining component which is in quadrature with the line current emulates an inductive or a capacitive reactance in series with the transmission line. The exchanged real power, P,,,, and reactive power, Qlnv, by the SSSC with the line are = vdq 0 ?= v I C O S e (W d9 end and an inductive reactance, X,, and a voltage source, y, , at the receiving end, respectively. Since, the emphasis of modeling is purely on UPFC, the power system in which the UPFC is connected to has been modeled in a simplistic way. The UPFC model in EMTP consists of two harmonic neutralized voltage source inverters, VSZl and VSI2, two magnetic circuits, MC1 and MC2, two coupling transformers, TI and T2, four mechanical switches, MSl, MS2, MS3, and MS4, two electronic switches, ES2 and ES22, current and voltage sensors, and a controller. The voltage source inverters are connected through a common DC link capacitor. The STATCOM is operated by regulating the reactive current flow through it. The SSSC is operated by injecting a voltage in series with the transmission line. II. DESCRIPTION OF THE INVERTER Fig. 4 shows a single phase inverter circuit, referred to as a 3level pole, which consists of a positive valve, A+, a negative valve, A-, and an AC valve, AAc. when a pole is connected across a series of capacitors which are charged with a total DC voltage of v w and the valves are closed and opened alternately, the pole output voltage, vA0, at the midpoint of the pole A with respect to the midpoint, 0, of the capacitor is a quasi square wave containing a positive sequence fundamental component and all the odd harmonic components, such as the zero sequence third, the negative i f t h ,and the positive sequence seventh, etc. sequence f
OFF

en,,
Qjnv

vdq

I = Vd9 Z S h 4

(2b)

The real power is absorbed kom or delivered to the line through the STATCOM which injects a current at the point of connection. The current injected by the STATCOM has a real or direct component, Id, which is in phase or in opposite phase with the line voltage. The current injected by the STATCOM also has a reactive or quadrature component, I,, which is in quadrature with the line voltage, thereby emulating an inductive or a capacitive reactance at the point of connection with the transmission line. This reactive current can independently be controlled which, in turn, will regulate the line voltage.

ON
AAcOq OFF

I
E N

b-

OFF

sssc

Fig. 4 A 3-Level Inverter Pole and its Output Voltage The amplitude of any odd multiple of fundamental component is 2

Fig. 2 A Basic Unified Power Flow Controller Model Each of the STATCOM and the SSSC consists of a solid-state voltage source inverter with several Gate Turn Off (GTO) thyristor switch-based valves and a DC link capacitor, a magnetic circuit, and a controller. The number of valves and the various configurations of the magnetic circuit depend on the desired quality of AC waveforms generated by the FACTS devices. The inverter configuration described in this paper is one of many different possible configurations that can be used to build a voltage source inverter. The configurations of the two inverters used in this paper are identical.
IPFC

(3) cos n7t where y is the dead period during which the AC valve operates in each quarter cycle and the pole output voltage is zero and n = 2k + 1 for k = 0, 1,2,3, etc.

yAo,n

= -vDC

VAN

0.5v,-Pa,

2s

Fig. 5 A 6-Pulse Inverter with 3-Level poles and its Output Voltages Fig. 5 shows three poles A, B, and C which are connected across the same DC link capacitor and the pole outputs are connected to a 3-phase load whose neutral point, N, is not connected to the midpoint of the capacitor. The poles A, B, and C which form a 6-pulse inverter are operated in such a way that the
pole voltages, vA,, v,,,
and vco, are time shifted fiom one another

//rel lorC tn o -[

I!

Fig. 3 A Unified Power Flow Controller Model in EMTP The UPFC model in EMTP is shown in Fig. 3 . The UPFC is connected in series with the transmission line which has an inductive reactance, X,, and a voltage source, at the sending

vs,

by one third of the time period of the pole voltage. Therefore, the , and are 120 apart. Since, fundamental phasors, the zero sequence components of each pole current have no return path to the midpoint of the DC link capacitor, the zero sequence components of each pole voltage, VNO = (VAO + VBO + vc0)/3, appear between the neutral point and the midpoint of the DC llnk capacitor. Therefore, each phase of the load voltages, VAN = VAO vNO, vBN = vBO - vNO, and vCN = VC- - VNO, consists of only a fundamental component and odd harmonic components (n) given by the equation (3) where n = 6k f 1 for k = 1 , 2 , 3 , etc. For a vw = 7d2 per unit, the amplitudes of fundamental and harmonic components, VAN,^, are shown in Fig. 6 as a function of y for possible values of y between 0 and 90. It is shown that for y =

vB,l

vC,,

1455
0, the fundamental as well as all the harmonic components have the highest possible amplitudes. At y = 0, a 3-level pole acts as a 2level pole which switches from +vm/2 to -vm/2 and offers the maximum possible DC to AC utilization. However, at y > 0, a 3level pole which switches from +v&2 to 0 to -vm/2 produces improved output waveform quality at the expense of reduction in the fundamental voltage. This is just what is needed if the SSSC has to operate from the common DC link capacitor which is the case in this paper. For y > 0, the fundamental amplitude decreases monotonically. However, the harmonic amplitudes vary sinusoidally. A measure of the harmonic content defined as
GNh =

7
n

(4)

where n = 6k f 1 for k = 1, 2, 3, etc. is also shown in Fig. 6. A measure of the total harmonic distortion of the voltage defined as
THD, =

v,,

v,,,

(5)

is also shown in Fig. 6. At rowm = 15.35", the fundamental amplitude decreases by 3.57% compared to what is obtained from a 2-level operation of the poles. But, the harmonic content is reduced to 16% from 31%, obtained from a 2-level operation of the poles in a 6-pulse inverter, resulting in the smallest THDv.
'AN5 VANJ

THDV
0.31
0

'ANh

time shifted by an angle of -8, the fundamental and all the harmonic components of the pole voltage get a phase shift by an angle of +e in the positive direction, irrespective of their sequence. n timeshift phase f i n d timeshift phase final shift phase shift phase angle pole D angle pole A 5 -5*(0) 0 0 -5*(-d6) M 6 x 7 +7*(0) 0 0 +7*(-d6) +d6 x 11 -ll*(O) 0 0 -11*(-d6) +d6 0 13 +13*(0) 0 0 +13*(-~/6) M 6 0 17 -17*(0) 0 0 -17*(-d6) +d6 x 19 +19*(0) 0 0 +19*(-d6) M 6 x 23 -23*(0) 0 0 -23*(-d6) +d6 0 25 +25*(0) 0 +25*(-./6) 0 M6 0 Table 1 Phase Angles of a 12-PulseInverter Phasors Table 1 shows the time shifted A and D pole voltages' first twenty five harmonic components' final phase angles after appropriate phase shift. The pole voltages from the ABC inverter exhibits a 6-pulse harmonic neutralized waveform with harmonic components n = 6k f 1 for k = 1, 2, 3, etc. Similarly, the pole voltages from the DEF inverter exhibits a 6-pulse harmonic neutralized waveform whose harmonic components (n = 6k f 1 for k = 1, 2, 3, etc.) have the same magnitudes as the corresponding harmonic components of the ABC inverter's 6-pulse harmonic neutralized waveform. However, the harmonic components (n = 6k f 1 for k = 1, 3, 5, etc.) are in opposite phases while the harmonic components (n = 6k f 1 for k ==2,4, 6, etc.) are in phases with the corresponding harmonic components of the ABC inverter's 6-pulse harmonic neutralized waveform. Therefore, if all the outputs from each 6-pulse inverter are combined by connecting the corresponding phases in series, a 12-pulse harmonic neutralized waveform is obtained. The resulting output voltage exhibits a fundamental component and odd harmonic components (n) given by the equation (3) where n = 12k 1 for k = 1,2,3, etc. Note that the output voltage of a 12-pulse inverter with 3-level poles is referred to as a 12-pulse waveform when the poles are operated with dead angle y = 0.

MAGNETIC CIRCUIT

15.35'

30'

6 0 '

90'

Fig. 6 Variations of Amplitudes of Fundamental and Harmonic Components, Harmonic Content and Total Harmonic Distortion Factor as a Function of y
InverterDEF, -30'

I .

,z
%

VF

I
VA

\?b

VB
VC

. c m

Fig. 7 A 12-PulseHarmonic Neutralized Inverter Configuration with 3Level Poles Fig. 7 shows two 6-pulse inverters (ABC and DEF) which are operated from the same DC link capacitor. On the AC side, they are connected to a 3-phase load (XYZ) through a magnetic circuit. The poles D, E, and F are operated in such a way that the pole voltage fundamental phasors, vD,l, ~ E , I and , are 120' apart and the fundamental voltage phasor set of the DEE; inverter lags the fundamental voltage phasor set of the ABC inverter by 30". The displacement angle between two consecutive 6-pulse inverters in a multipulse inverter arrangement is 2d6m, where m is the total number of 6-pulse inverters used. The configuration of the magnetic circuit in Fig. 7 is such that if an inverter pole voltage is

Inverter ABC, 0 '

vF,~

Fig. 8 A Magnetic Circuit for a 12-PulseHarmonic Neutralized Inverter Fig. 8 shows a possible configuration of the magnetic circuit which can be used to generate a 12-pulse harmonic neutralized voltage. The ABC 6-pulse inverter voltage is fed to a Y-Y transformer and the DEF 6-pulse inverter voltage is fed to a A-Y transformer. The inverter side A winding and DE winding will have per turn fundamental component voltages which are of same magnitude and in phase and the fifth and the seventh harmonic components each of which are: of same magnitude but in opposite phase. Therefore, if the line riide of the transformer windings are connected in series, the phase-X voltage will exhibit only a
fundamental component and 12-pdse harmonic components. The

line side inverter windings can have any turns ratio other than 0.5 to increase or decrease the output voltage. The presence of 12-pulse Iiarmonic components in the inverter output voltage may not be acceptable in many applications. Therefore, an inverter with a higher pulse output voltage should be considered. Fig. 9 shows a 24-pulse Quasi Harmonic Neutralized

12-Pulse Inverter# 2

Fig. 9 A 24-PulseQuasi Harmonic Neutralized Inverter Configuration ( Q W inverter configuration which consists of four 6-pulse inverters (AlBlCl, A2B2C2, DlElF1, and D2E2F2) operated from a common DC link capacitor charged with a total DC voltage of vK. On the AC side, the outputs from four inverters are connected to a 3-phase load (XYZ) through a magnetic circuit. The poles Al, B1, C1, A2, B2, C2, D1, E l , F1, D2, E2, and F2 are operated in such a way that the pole voltage fundamental phasors in a group, for example, , , and of AlBlCl inverter, VAz1, VBz 1, and of A2B2C2 inverter, FDl,l , VEl,l, and Vn,l of DlElFl inverter, and F D A , , V E T 1 ,and TF,, of D2E2F2 inverter, are 120" apart. The displacement angle between two consecutive 6-pulse inverters in a multipulse inverter configuration is 2n16m (= 15") where m (= 4) is the total number of 6-pulse inverters used. The fundamental voltage phasor set of the AlBIC1, A2B2C2, DlElF1, and D2E2F2 inverters are time shifted by angles of +7.5', -7.5', -22.5', and -37.5', respectively. If the pole voltages from the inverters AlBlCl and DlElFl are magnetically combined as described before, the output voltage exhibits a 12-pulse harmonic neutralized waveform with harmonic components n = 12k k 1 for k = 1, 2, 3, etc. Similarly, if the pole voltages from the inverters A2B2C2 and D2E2F2 are magnetically combined, the output voltage exhibits a 12-pulse harmonic neutralized waveform whose harmonic components (n = 12k rt 1 for k = 1, 2, 3, etc.) have the same magnitudes as the corresponding harmonic components of the first 12-pulse harmonic neutralized waveform. However, the fundamental phasors of the output voltages from the two 12-pdse inverters are at +7.5" and -7.5", respectively. Therefore, if all the outputs from each 6-pulse inverter are combined by connecting the corresponding phases in series, as shown in Fig. 10, a 24-pulse QHN waveform is obtained. Note that the output voltage of a 24-pulse QHN inverter with 3level poles is referred to as a 24-pulse QHN waveform when the poles are operated with dead angle y = 0. The resulting output voltage exhibits a fundamental component and odd harmonic components each of which has an amplitude of

vAi,lvH,l vc2

va,l

Fig. 10 A Magnetic Circuit for a 24-Pulse Quasi Harmonic Neutralized Inverter

(C)

1.08%

/
30'
60' 90

0.0391 0.07:
3.82'

where n'z-1 and 12k 1' for k = 1, 2, 3, etc. and y is the period during which each AC valve operates in each quarter cycle. The amplitude of any odd harmonic component (n) normalized to the fundamental component is

vx,where n

'x,--

cos (nn 124) cos ny (7)

n COS (X 124) COS y = 12k f 1 for k = 1,2, 3, etc. Note that if a 24-pulse QHN

inverter with 3-level poles is operated with y = d48, the resulting output voltage is the same as that is obtained from a 48-pulse QHN inverter.

Fig 11 Normalized Harmonic Componentsof Output Voltages from (a) a 24-Pulse QHN Inverter and @) a 48-Pulse QHN Inverter as a Function of Harmonic Order and (c) Variations of Amplitude of Fundamental Component, Harmonic Content and THD as a Function of y Fig. lla, b show the normalized harmonic components of the output voltages from a 24-pulse QHN inverter and a 48-pulse QHN inverter as a function of harmonic order (n) as given by the equation (7). The variations of fundamental component, harmonic content and total harmonic distortion factor of a 24-pulse QHN inverter with 3-level poles as a function of y is shown in Fig. llc. At yOpm,,,,, = 3.82", the fundamental amplitude decreases by 1.08% compared to what is obtained from a 2-level operation of the poles. But, the harmonic content is reduced to 3.91% from 7.7%, obtamed from a 2-level operation of the poles in a 24-pulse inverter, resulting in the smallest THD,. The configuration of each inverter in this paper is of 24-pulse QHN type and each pole is 3-level type. The inverter in the STATCOM has been operated with a fixed dead angle of n/48 to obtain 48-pulse output voltage waveform. The inverter in SSSC has been operated with a variable dead angle, y, to v a q the amplitude of the injected voltage. I I I . CONTROL OF UPFC The control of a UPFC can be divided into two parts - the control of the STATCOM and the control of the SSSC. When the STATCOM and the SSSC operate as stand-alone devices, they exchange almost exclusively reactive power at their terminals.

1457
During the stand alone operations, the SSSC injects a voltage in quadraturewith the line current thereby emulating an inductive or a capacitive reactance in series with the line and the STATCOM injects a reactive current at the point of connection thereby also emulating a reactance at the point of connection with the transmission line. While operating both the inverters together as a UPFC, the injected voltage in series with the transmission line can be at any angle with respect to the line current. The exchanged real power at the terminals of one inverter with the line flows to the terminals of the other inverter through the common DC link capacitor [4, 51. The STATCOM can still be used to control the reactive current flow through it independently. A. STATCOM The controller of a STATCOM is used to operate the inverter in such a way that the phase angle between the inverter voltage and the line voltage is dynamically adjusted so that the STATCOM generates or absorbs desired VAR at the point of connection [2].
* I

The inverter voltage and current show the presence of 48-pulse quasi harmonic components. v, A
(PU)

Controller r____________________________________

Ilq

I
! I I

I I

Rotating

I
I

Fig. 13 Performance of a Static Synchronous Compensator with a 48-Pulse Quasi Harmonic Neutralized Inverter Operating in Capacitive and Inductive Modes
I I

L___________________-------------____J

Fig. 12 Control Block Diagram of a Static Synchronous Compensator Fig. 12 shows the control block diagram of the STATCOM. An instantaneous 3-phase set of line voltages, vl, at BUS 1 is used to calculate the reference angle, 0, which is phase-locked to the phase a of the line voltage, via. An instantaneous 3-phase set of measured inverter currents, il, is decomposed into its real or direct component, I,, and reactive or quadrature component, Zlq, respectively. The quadrature component is compared with the desired reference value, Zlq*, and the error is passed through an error amplifter which produces a relative angle, a,of the inverter voltage of the inverter with respect to the l i e voltage. The phase angle, 01, voltage is calculated by adding the relative angle, a,of the inverter voltage and th: phaselock-loop angle, 0.The reference quadrature component, Zl ,of the inverter current is defined to be either positive if the STATC6M is emulating an inductivereactance or negative if it is emulating a capacitive reactance. The DC link capacitor voltage, vm, is dynamically adjusted in relationship with the inverter voltage. Fig. 13 shows the digital simulation results from the reactive current control operation of a STATCOM while the SSSC is bypassed by the mechanical switch, MS2. Between 0 and 50 ms, the mechanical switch, MSI, stays open, disconnecting the STATCOM fiom the transmission line. The DC link capacitor is precharged. The inverter output 48-pulse voltage of phase a, el=,and the line voltage of phase a, vln, are in phas? At 50 ms, MSl closes and the quadrature current demand, Zlq , of the inverter is set to zero. Since the inverter current is zero, the inverter voltage of phase a, el,, and the line voltage of phase a, v,,, haye equal amplitudes. At 125 ms, the quadrature current demand, Zl , of the inverter is set to one per unit capacitive, which means the S?ATCOM should "see" the system as q inductive reactance and the inverter current of phase a, ita, lags the line voltage of phase a, vlo, by almost 90". The inverter voltage set, el, is greater than the l k e voltage set, vl. At 175 ms, the quadrature current demand, Z , ,of the inverter is set to one per unit inductive, which means the S'fATCOM should "see" the system as a capacitive reactance and the inverter current in phase a, ilo, leads the line voltage at phase a, via, by almost 90". The inverter voltage set, el, is less than the,line voltage set, vl. At 250 ms, the quadrature current demand, Ilq , of the inverter is set t o one per unit capacitive and the transition takes place in a subcycle time. The phase angle, a, between the inverter voltage and the line voltage is dynamically adjusted so that the inverter maintains proper DC link capacitor voltage. Fig. 14 shows the expanded view of two sections of Fig. 13.

"1a

time
-1

Fig. 14 Waveforms fiom a Static Synchronous Compensator with a 48Pulse Quasi Harmonic Neutralized Inverter Operating in Capacitive and Inductive Modes B. SSSC The SSSC can be operated in many different modes, such as voltage injection, phase angle shifter emulation, line impedance emulation, automatic power flow control, etc. In each mode of operation, the final outcome is such that the SSSC injects a voltage in series with the transmissiori line [3, 6, 71. In this paper, the SSSC is operated in a voltage injection mode. The control block diagram for the SSSC is shown in Fig. 15.
Controller ~----------------.----------.------

I I

p-1

Fig. 15 Control Block Diagam of a Static Synchronous Series Compensator

1458
The desired peak fundamental voltage, Vdq*, at the output of the inverter and its relative angle, p, with respect to the reference of the phase-lock-loop angle are specified. The phase angle, 02, inverter voltage is calculated by adding the relative angle, p, of the inverter voltage and the phase-lock-loop angle, 0.The dead angle of each pole is calculated according to the equation (6) with n = 1. V, A, P, Q real power flow, P,, at the receiving end reverses. The series inverter output voltage, e,, of phase a lags the line current, i,, by an angle $. The reactive power exchanged at the terminals of the coupling transformer, T2, becomes capacitive. Fig. 17 shows the expanded view of two sections of Fig. 16. The inverter voltage and current show the presence of harmonic comDonents. 0.5e2a

0.25 0
Fig. 17 Waveforms fiom a Unified Power Flow Controller, wth a 24-&lse Quasi Harmonic Neutralized Inverter wth 3-Level Poles, Operatmg m a

Voltage Injection Mode IV. CONCLUSION

4 -

Fig. 16 Performance of a Unified Power Flow Controller, with a 24-Pulse Quasi Harmonic Neutralized Inverter with 3-Level Poles, Operatmg in a Voltage Injection Mode Fig. 16 shows the digital simulation results from the voltage injection mode of operation of an SSSC while the STATCOM is operated to deliver no reactive current. At the beginning of the operation, the mechanical switch, MS2, and the electronic switch, ES22, are open and the electronic switch, ES2, is closed. The inverter, VSZ2, injects no voltage. The voltage, vi,, at the terminals of the coupling transformer, T2, is the voltage across its leakage reactance. The power exchanged at the terminals of the coupling transformer, T2, is mostly reactive due to the inductance of the transformer. The mechanical switch, MSl, is open, disconnecting the STATCOM from the transmission line. The DC link capacitor is precharged.* At 50 ms, MSl closes and the quadrature current demand, Ziy ,of the inverter is set to zero. At 100 ms, a series voltage injection of 0.2 per unit, at the inverter side, at an angle p = 120" leading the reference phase-lock-loop angle is requested. The series inverter output voltage, e,, of phase a leads the line current, i,, by an angle $. Since $ > 90", the SSSC emulates a negative resistance in addition to an inductive reactance in series with the transmission line. The real power that is delivered to the line by the series inverter flows from BUS 1 through the STATCOM. The shunt lnverter output voltage, ela,of phase a is almost 180" out of phase with the current, , of phase a at BUS 2 leads ila, flowing through it. The voltage, v the voltage, v,,, of phase a. The real power, Pr, delivered at the receiving end decreases. The reactive power, Q,, delivered at the receiving end becomes inductive. At 200 ms, the injected voltage request is kept at 0.2 per unit while the angle p is changed to 60'. The real power that is absorbed f?om the line by the series inverter flows to BUS 1 through the STATCOM. The shunt inverter output voltage, el,, of phase a is in phase with the current, ila, flowing through it. The reactive power, Qr, delivered at the receiving end becomes capacitive. At 300 ms, the injected voltage request is increased to 0.4 per unit while maintaining the same angle. The voltage, v , of phase a at BUS 2 lags the voltage, v,,, of phase a. The

A UPFC has been modeled using an EMTP simulation package. The UPFC consists of two voltage source inverters - one injects an almost sinusoidal voltage in series with the transmission line and the other injects an almost sinusoidal current at the point of connection. The injected voltage can be at any angle with the line current. The injected current has two parts. First, the real part, which is in phase with the line voltage, delivers or absorbs real power to the line that is negotiated by the injected voltage source plus losses in UPFC. Second, the reactive part, which is in quadrature with the line voltage, emulates an inductive reactance or a capacitive reactance at the point of connection. The SSSC model has been operated injecting a voltage in series with the transmission line. The STATCOM model has been operated regulating the reactive current flow through it and the transition between different modes of operation takes place in a subcycle time. The operation of the model is verified with the model connected to a simple transmission line which can easily be replaced by the utility's existing more complex power system network. V. APPENDIX
BEGIN NEW DATA CASE C FILE: 24PQUPFC.DAT (24-Pulse Quasi harmonic neutralized C UPFC). This UPFC Power Flow Controller was implemented C by K. K. Sen at Westmghouse, STC, Pittsburgh, PA 15235. 16.666-6450.00-3 30 10 TACS HYBRID 99CRD = 180 / PI 99CDR = 1 / CRD 99TWOPI = 2 . 0 * PI 99KpshI = .45 99KishI = 40 99Kinv = (2 / PI) * COS(PI/24) 99KPLLp = 100000.0 99KPLLi = 250000.0 99MS1 = TIMEX .GE. 0.05 99MS2 = 0 C Inverter base 99Vbasei = 112676.528 99Ibasei = 946.662704 C Inputs from the measiiring switches 90BUSOlA

YOBUSOlB
SOBUBOlC 90BUS02A 90BUS02B 90BUS02C 9o m 9 OVRB 9 OVRC 90POS 90NEG 91INVOlA 91INVOlB 91INVOlC 91INV02A 91INV02B 91INVO2C 91BUS03A 91BUS03B 9lBUSO 3C C BUS1 voltage computation 99vlapu = BUSOlA / Vbasei 99vlbpu = BUSOlB / Vbasei

1459
99vlcpu = BUSOlC / Vbasei = vlapu 99vlds 99vlqs = -(vlapu t 2.0 * vlcpu) / SORT (3) C Phase-Lock-Loop (locked to phase a voltage of BUS1) ' SIN(PLLi) vlds ' 99PLLerr = vlqs * COS(PLLi) 99PLLint = PLLini t PLLerr * DELTA? PLLerr 99PLLdot = KPLLi * PLLint + KPLLp PLLini tPLLint 99PLL = PLLi t PLLdqt DELTAT PLLi tPLL 'TWOPI) 99theta = PLL - TWOPI * TRUNC(PLL/ 99COSPLL = COS (theta) 99SINPLL = SIN(theta) C BUS2 voltage computation = BUSOZA / Vbasei 99v2apu 99vZbpu = BUSOZB / Vbasei = BUS02C / Vbasei 99v2cpu C Injected voltage computation 99v12apu = vlapu - v2apu vlbpu 99v12bpu = vlbpu 99v12cpu = vlcpu - v2cpu C Receiving-end voltage computation 99vrapu = VRA / Vbasei 99vrbpu = VRB / Vbasei 99vrcpu = VRC / Vbasei C Line current computation 99iapu = BUS03A / Ibasei 99ib~u = BUS03B / Ibasei = BUS03C / Ibasei 99icpu C Shunt inverter current computation 99ila = INVOlA = INVOlB 99ilb = INVOlC 99ilc 99ilapu = ila / Ibasei = ilb / Ibasei 99ilbpu = ilc / Ibasei 99ilcpu = ilapu 99ilds = -(ilapu + 2.0 * ilcpu) / SQRT(3) 99ilqs = ilds COSPLL + ilqs * SINPLL 99ild = -ilds SINPLL + ilqs * COSPLL 99ilq C Series inverter current computation = INV02A 99i2a = INVOZB 99i2b 99i2c = INVOZC 99vlE1 = vDC / 2 poslEl vDC / 2 * neglEl 99anlF1 = thetal + (-270.0 + 7.5) * CDR 99anglF1 = anlFltTWOPI*(anlF1.LT.O.O)-TWOPI*(anlF1.GE.TWOPI) 99poslF1 = ( (anglF1-gamnal).C;E.O) .AND. ( (anglF1-PItgammal).LT.O) 99neglF1 = ((anglF1 - PI-gammal) .GE. 0) .AND. ((anglF1 TWOPItgammal) .LT. O ! 99vlF1 = VDC / 2 pOSlFl vDC / 2 * neglFl 99anlD2 = thetal t (-30.0 . . 7.5) * CDR 99anglD2 = anlD2+TWOPI*(anlI)2.LT.O.O)-TWOPI*(anlD2.GE.TWOPI) 99poslD2 = ( (anglD2-gammal).GE.O) .AND. ( (anglD2-PItgammal).LT.O) PI-gammal) .GE. 0 ) .AND. ((anglD2 99neglD2 = ((anglD2 TWOPItgammal) .LT. 0) 99vlD2 = vDC / 2 * poslD2 vDC / 2 * neglD2 99anlE2 = thetal + (-150.0 - 7.5) * CDR 99anglE2 = anlE2tTWOPI*(anlEZ.LT.O.O)-TWOPI*(anlE2.GE.TWOPI) 99poslE2 =((anglE2-gammal).GE.O).AND.((anglE2-PI+garmnal).LT.O) 99neglE2 = ((anglE2 PI-gammal) .GE. 0) .AND. ((anglE2 TWOPI+gamal) .LT. 0) 99vlE2 = VDC / 2 * pOslE2 - VDC / 2 neglE2 CDR 99anlF2 = thetal t (-270.0 - 7.5) 99anglF2 = anlFZ+TWOPI* (anlF2.LT.O.O)-TWOPI* (anlFZ.GE.TWOP1) 99poslF2 =((anglF2-gammal).GE.O).AND.((anglF2-PI+gammal).LT.O) 99neglF2 = ((anglF2 - PI-gammal) .GE. 0) .AND. ((anglF2 TWOPI+gammal) .LT. O ! 99vlF2 = vDC / 2 poslF2 vDC / 2 * neglF2 C Magnetic Circuit C Note: The signals vX, VY and VZ in Fig. 10 are renamed C as ela, elb and elc, respectively. The signals vX1, vY1 and C vZ1 are renamed as elal, elbl and elc1,respectively. = (VlAl + vlBl t vlC1) / 3 99vlN1 99vlAlN = vlAl - vlNl 99vlBlN = vlBl - vlNl 99vlClN = vlCl - vlNl 99vlDlE1 = vlDl - vlEl 99vlElF1 = vlEl - vlFl 99vlFlD1 = vlFl - vlDl 99elal = (vlA1N + vlDlEl / SQRT(3)) / 2 99elbl = (VlBlN + VlElFl / SQRT(3)) / 2 99elcl = (vlClN + VlFlDl / SQRT(3)) / 2 = (vlA2 t vlB2 + vlC2) / 3 99vlN2 99vlA2N = vlA2 vlN2 99vlB2N = vlB2 - vlN2 = vlC2 - vlN2 99vlC2N 99vlD2E2 = vlD2 vlE2 99vlE2F2 = vlE2 - vlF2 99vlF2D2 = vlF2 vlD2 = (vlA2N + vlD2E2 / SQRT(3)) / 2 99elaZ 99elb2 = (vlB2N + vlE2F2 / SQRT(3)) / 2 99elc2 = (v1CZN + vlF2D2 / SQRT(3)) / 2 C VSIl output voltage 99ela = (elal + ela2) / 2 = (elbl t elb2) / 2 99elb 99elc = (elcl + elc2) / 2 99elapu = ela / vbasei C Setting the SSSC voltage demand 99v2cml = 0.2 * (TIMEX .GE. 0.100) 99v2cm2 = 0.2 * (TIMEX .GE. 0.300) 99v2dqcm = v2cml + v2cm2 lv2dqrf +vZdqcm 1.0 1.0 0.0040 99betal = 120** (TIMEX .GE. 0.100) (TIMEX .GE. 0.200) 99beta2 = 60 99beta = (beta1 beta2) * CDR 99cosga2 = v2dqrf / vDCpu / Kinv = cosga2 + 0.00000001 99ga2d 99ga2q = SQRT(1 cosgal * cosga2) 99gammaZ = ATAN(ga2q / ga2d) 99tha2 = theta + PI / 2 + beta 99theta2 = tha2 + TWOPI*(tha2.LT.O.O) - TWOPI*(tha2.GE.TWOPI) C Inverter Pole Voltages 99an2A1 = theta2 + 7.5 * CDR 99ang2A1 = an2A1+TWOPI*(an2A1.LT.O.O)-TWOPI*(an2A1.GE.TWOPI) 99pos2A1 = ( (angZAl-gamma2) .GE.O) .AND. ( (ang2Al-PI+gamaZ).LT.O) 99neg2A1 = ((ang2Al PI-gamma2) .GE. 0 ) .AND. ((ang2Al TWOPI+gammaZ) .LT. 0) 99v2A1 = vDC / 2 posZAl - vDC / 2 * neg2Al 99an2B1 = theta2 + (-120.0 + 7 . 5 ) * CDR 99ang2B1 = an2Bl+TWOPI* (anZB1.LT.O.O)-TWOPI*(anZB1.GE.TWOPI) .GE.O) .AND. ((angZB1-PItgamma2).LT.O) 99pos2B1 = ( (anglBl-gamma2) 99neg2B1 = ((an9281 PI-gamma2) .GE. 0 ) .AND. ((ang2B1 TWOPItgamaZ) .LT. 0 ; 99v2B1 = vDC / 2 pos2Bl - vDC / 2 neg2Bl 99an2C1 = theta2 t (-240.0 t 7.5) CDR 99ang2C1 = an2C1+TWOPI*(an2C1.LT.O.O)-TWOPI*(an2C1.GE.TWOPI) 99pos2Cl = ( (angZC1-gamma2).GE.O) .AND.( (ang2Cl-PItgamma2).LT.O) 99neg2C1 = ((angZC1 - PI-gamma2) .GE. 0 ) .AND. ((angZC1 TWOPI+gamma2) .LT. 0) 99v2C1 = vDC / 2 * pos2Cl vDC / 2 * neg2Cl 99an2A2 = theta2 7.5 * CDR 99ang2A2 = an2AZtTWOPI*(an2A2.LT.0.0)-TWOPI*(an2A2.GE.TWOPI) .GE.O) .AND. ( (angZAZ-PI+gammaZ).LT.O) 99pos2A2 = ( (angZA2-gammaZ) 99neg2A2 = ((ang2A2 - PI-gamma2) .GE. 0) .AND. ((ang2A2 TWOPItgamma2) .LT. O ! 99v2A2 = vDC / 2 pos2A2 - vDC / 2 * neg2A2 CDR 99an2B2 = theta2 + (-120.0 - 7.5) 99ang2B2 = an2B2+TWOPI*(an2B2.LT.O.O)-TWOPI*(an2B2.GE.TWOPI) 99pos2B2 =((ang2B2-gamma2).GE.O).AND.((ang2B2-PI+g~a2).LT.O) 99neg2B2 = ((ang2B2 - PI-gammal) .GE. 0) .AND. ((an9282 TWOPI+gammaZ) .LT. O ! 99v2B2 = vDC / 2 pos2B2 - vDC / 2 * neg2B2 99an2C2 = theta2 + (-240.0 - 7.5) CDR 99ang2C2 = an2C2+TWOPI*(an2C2.LT.O.O)-TWOPI*(an2C2.GE.TWOPI) 99posZC2 = ( (angZCZ-gamma2) .GE.O) .AND. ( (anaZC2-PItaamma2)iLT.0) 99negzcz 3 ((angzcz PI-gammaz) .GE. 0 ) .AND. ((angzcz TWOPI+gammaZ) .LT. 0) 99v2CZ = vDC / 2 * pOS2C2 - vDC / 2 * negZC2 99an2D1 = theta2 + (-30.0 + 7.5) * CDR 99ang2D1 = an2D1+TWOPI*(an2D1.LT.O.O)-TWOPI*(an2D1.GE.TWOPI) 99pos2D1 = ( (ang2Dl-gamma2).GE.O) .AND.( (ang2Dl-PI+gammaZ).LT.O) 99neg2D1 = ((anglD1 PI-gamma2) .GE. 0 ) .AND. ((ang2D1 TWOPItgamma2) .LT. 0) 99v2D1 = vDC / 2 * pos2Dl - vDC / 2 neg2Dl 99an2E1 = theta2 + (-150.0 + 7 . 5 ) * CDR

demand 99ilqcml- = T I 99ilqcm2 = 2 * (TI1 99ilacm3 = 2 * (TIMEX .GE. 0.25)

-. .

* o

1.0

0.0040

C shunt-inverter-angle calculation 99ilqerr = (ilqref ilq) MS1 99ilqint = ilqini + ilqerr * DELTAT ilqini +ilqint = KpshI * ilqerr + KishI * ilqint 99alpha 99gammal = 3.75 * CDR 99fhal = theta + PI / 2 t alpha C This addition of PI/2 is because the gating signals are sine C reference and the Phase-Lock-Loop signals are cosine C reference. 99thetal = thal + TWOPI*(thal.LT.O.O) TWOPI*(thal.GE.TWOPI) C Inverter Pole Voltages 99anlA1 = thetal + 7.5 * CDR 99anglA1 = anlA1+TWOPI*~anlA1.LT.O.O)-TWOPI*(anlA1.GE.TWOPI) 99poslA1 = ( (anglAl-gammal).GE.O) .AND. ( (anglAl-PI+gammal) .LT.O) 99neglA1 = ((anglA1 - PI-gammal) .GE. 0) .AND. ((anglAl TWOPItgammal) .LT. 0) 99vlA1 = vDC / 2 * poslAl vDC / 2 neglAl 99anlB1 = thetal t (-120.0 + 7 . 5 ) * CDR 99anglB1 = anlBl+TWOPI* (anlB1.LT.O.O)-TWOPI*(anlBl.GE.TWOPI) 99poslB1 = ( (anglB1-gammal).GE.O) .AND.( (anglB1-PI+gammal).LT.O) 99neglB1 = ((anglB1 - PI-gammal) .GE. 0) .AND. ((anglB1 TWOPI+gammal) .LT. 0 ; 99vlB1 = vDC / 2 poslBl vDC / 2 * neglBl 99anlC1 = thetal + (-240.0 t 7 . 5 ) * CDR 99anglC1 = anlC1+TWOPI*~anlC1.LT.O.O)-TWOPI*(anlC1.GE.TWOPI) 99poslC1 = ( (anglC1-gammal).GE.O) .AND. ( (anglCl-PI+gammal).LT.O) 99neglC1 = ((anglC1 - PI-gammal) .GE. 0) .AND. ((anglC1 TWOPI+aammal) .LT. 0) 99vlc1- = VDC / 2 * poslcl VDC / 2 * neglcl CDR 99anlA2 = thetal - 7.5 99anglA2 = anlAZ+TWOPI*(anlA2.LT.O.O)-TWOPI* (anlA2.GE.TWOPI) 99poslA2 = ( (anglA2-gammal).GE.O) .AND. ((anglAZ-PI+gammal) .LT.O) 99neglA2 = ((anglA2 PI-gammal) .GE. 0 ) .AND. ((anglA2 TWOPI+gammal) .LT. O ! 99vlA2 = vDC / 2 poslA2 - vDC / 2 neglA2 = thetal + (-120.0 - 7 . 5 ) * CDR 99anlB2 99anglB2 = anlB2+TWOPI*(anlB2.LT.O.O)-TWOPI*(anlB2.GE.TWOPI) 99poslB2 =((anglB2-gammal).GE.O).AND.((anglB2-PItgammal).LT.O) 99neglB2 = ((anglB2 - PI-gammal) .GE. 0 ) .AND. ((anglB2 TWOPI+gammal) .LT. 0 ) 99vlB2 = VDC / 2 * poslB2 - VDC / 2 neglB2 99anlC2 = thetal + (-240.0 7 . 5 ) * CDR 99anglC2 = anlC2+TWOPI*(anlC2.LT.O.O)-TWOPI*(anlC2.GE.TWOPI) 99poslC2 = ( (anglCZ-gammal).GE.O).AND.((anglC2-PI+gammal) .LT.O) 99neglC2 = ((anglC2 - PI-gammal) .GE. 0 ) .AND. ((anglC2 TWOPI+gammal) .LT. 0) 99vlCZ = vDC / 2 poslC2 - vDC / 2 * neglCZ 99anlD1 = thetal t (-30.0 t 7.5) CDR 99anglD1 = anlD1+TWOPI*(anlDl.LT.O.O)-TWOPI*(a~lD1.GE.TWOPI) 99poslD1 = ( (anglD1-gammal) .GE.O) .AND. ( (anglD1-PI+gammal).LT.O) 99neglD1 = ((anglD1 PI-gammal) .GE. 0) .AND. ((anglD1 TWOPI+gammal) .LT. 0 ) 99vlD1 = vDC / 2 * ~0slD1 vDC / 2 * nealDl 99anlE1 = thetal + 11150.0 + 7.5) * CDR 99ingiE1 = aniEitTwoZI;laniE1.LT~o.o)~TwopI*(anlE1.GE.TWOPI) 99poslE1 = ( (anglEl-gammal).GE.O).AND. ((anglEl-PI+gammal) .LT.O) 99neglEl = ((anglEl - PI-gammal) .GE. 0 ) .AND. ((anglEl TWOPI+gammal) .LT. 0)

1460
99ang2E1 = an2E1+TWOPI*(an2E1.LT.O.O)-TWOPI*(an2El.GE.TWOPI) 99pos2E1 = ( (ang2El-gama2) .GE.O) .AND.((angZEl-PI+gamma2) .LT.O) 99neg2E1 = ((ang2El - PI-gamma2) .GE. 0) .AND. ((ang2El TWOPI+gammaZ) .LT. 0 ) q qv?Pl = vnC / 7 * ~ o s 2 E l - vDC / 2 * nea2El __.-I99an2F1 = t G t X + (t270.0 + 7.5) * CDR 99ang2F1 = an2F1+TWOPI*(an2F1.LT.O.O)-TWOPI*(an2F1.GE.TWOPI) 99pos2F1 = ( (ang2Fl-gamma2) .GE.O).AND. ((ang2Fl-PItgamma2) .LT.O) 99nea2F1 = ((anqZF1 - PI-gamma2) .GE. 0) .AND. ((angZF1 TWOPf+gamma2) .L'i = vDC / ' Z o ! pos2F1 - vDC / 2 * neg2Fl 99v2F1 99an2D2 = theta2 + (-30.0 - 7.5) * CDR 99ang2D2 = an2D2+TWOPI*(an2D2.LT.O.O)-TWOPI*(an2D2.GE.TWOPI) .GE.O).AND. ((ang2DZ-PI+gamma2).LT.O) 99pos2D2 = ( (ang2DZ-gamma2) 99neg2D2 = ((ang2D2 - PI-gamma2) .GE. 0) .AND. ((ang2D2 TWOPI+gama2) .LT. 0) 99v2D2 = vDC / 2 * pos2D2 - vDC / 2 * neg2D2 99an2E2 = theta2 + (-150.0 - 7.5) * CDR 99ang2E2 = an2E2+TWOPI*(an2E2.LT.0.0)-TWOPI*(an2E2.GE.TWOPI) .GE.O).AND. ((ang2E2-PItgamma2).LT.O) 99pos2E2 = ( (angZEZ-gamma2) 99neg2E2 = ((ang2E2 - PI-gamma2) .GE. 0) .AND. ((ang2E2 TWOPI+gamma2) .LT. O! 99v2E2 = vDC / 2 pos2E2 - vDC / 2 * neg2E2 99an2F2 = theta2 + (-270.0 - 7.5) * CDR 99ang2F2 = anZFZ+TWOPI*(an2F2.LT.O.O)-TWOPI* (anZF2.GE.TWOPI) .LT.O) 99pos2F2 = ( (ang2F2-gama2).GE.O).AND. ((angZFZ-PI+gammaZ) 99neg2F2 = ((ang2F2 PI-gamma2) .GE. 0) .AND. ((ang2F2 TWOPI+gammaZ) .LT. 0) 99v2F2 = vDC / 2 * pos2F2 - vDC / 2 * neg2F2 C Magnetic Circuit C Note: The signals vX, vY and VZ in Fig. 10 are renamed C as e2a, e2b and e2c, respectively. The signals vX1, vY1 and C vZ1 are renamed as e2a1, e2bl and e2c1,respectively. 99v2N1 = (v2A1 + v2B1 + v2C1) / 3 99v2AlN = v2A1 - v2N1 99v2BlN = v2B1 - v2N1 99v2ClN = v2C1 - v2N1 99v2DlE1 = v2D1 - v2E1 99v2ElF1 = v2E1 - v2F1 99v2FlD1 = v2F1 - v2D1 = (v2AlN + v2DlEl / SQRT(3)) / 2 99e2al 99e2bl = (vZB1N + v2ElFl / SQRT(3)) / 2 99e2cl = (vZC1N + vZFlDl / SQRT(3)) / 2 99v2N2 = lv2A2 + v2B2 + v2C2) / 3 . . 99v2A2N = v2A2 - v2N2 99v7R7N . . -~~~ = v2B2 - v2N2 v2c2 - v2N2 99v2C2N 99v2D2E2 v2D2 - v2E2 99v2E2F2 v2E2 - v2F2 v2D2 99vZF2D2 v2F2 SQRT 99e2a2 (v2A2N + v2D2E2 / 2 99e2b2 SQRT lv2B2N + v2E2F2 / 2 / 2 SQRT 99e2c2 = (v2C2N + v2F2D2 C VSI2 output voltage 99e2a = (e2al + e2a2) / 99e2b = (e2bl + e2b2) / 99e2c = (e2cl + e2c2) / 99e2apu = e2a / Vbasei c DC link capacitor voltage calculation 9999 lINVOZA 0.892723.679 1.0 2BUSOlABUS02A 0.892723.679 1.0 TRANSFORMER T2B 9999 1.0 1INV02B 0.892723.679 ZBUSOlBBUSOPB 0.892723.679 1.0 TRANSFORMER T2C 9999 pv. 2 1.0 0.892723.679 .0 .. -c . LBUSOlCBUS02C 0.892723.679 1.0 BLANK RECORD ENDING BRANCHES BUSOZABUSO3A BUS02BBUS03B BUSOPCBUSO3C ela INVOlA elb INVOlB elc INVOlC INV02Ae22a INV02Be22b INV02Ce22c 13ella BUSOlA MS 1 13ellb BUSOlB
MS1

MEASURING MEASURING MEASURING MEASURING MEASURING MEASURING MEASURING MEASURING MEASURING

13ellc BUSOlC
MS1

13e2a e22a ES2 13e2b e22b ES2 13e2c e22c ES2 13e22a ES22 13e22b ES22 13e22c ES22 13BUSOlABUSOZA
MS2

CLOSED CLOSED CLOSED

13BUSOlBBUS02B
MS 2

13BUSOlCBUSOZC BLANK RECORD ENDING SWITCHES 60ela 60elb 60elc 60e2a

MS 2

0.00 -120.00 120.00

-20.00

-1. -1. -1. -1.

-1. -1.

99vDCpu = Z C / %;sei = ela * ila + elb * ilb + elc * ilc 99Pinl = (-Pin1 / vDC) * M S 1 99iDC1 99Pin2 = e2a * i2a + e2b * i2b + e2c * i2c 99iDC2 = (Pin2 / vDC) * M S 1 99iDCnet = iDCl + iDC2 99iDCnl = iDCnet 99iDCnZ = -iDCnl .c Exchanged power between the SSSC and the transmission line 99Pinvpu =(vlZapu*iapu + vlZbpu*ibpu + vl2cpu*icpu) / 1.5 9 9 0 i n w u =lvl2aou*ic~u- vlZcDu*iaDu) * SORTI3) / 1.5 C-iiecelveins-end'powe; calculation 99Prpu = (vrapu*iapu + vrbpu*ibpu + vrcpu*icpu) / 1.5 99Qruu = (vrauu*icpu - vrcpu*iapu) * SQRT(~) / 1.5 C Setting up the-electronic switch& =~ 0 _ 99ES22 . . ~ _ 99ES2 = .NOT. ES22 C TACS Output 33ilqrefilq vDCpu elapu vlapu ilapu alpha 33e2apu vl2apuiapu Prpu Qrpu PinvpuQinvpu BLANK RECORD ENDING TACS VSA BUSOlA 1.0053 19.73 VSB BUSOlBVSA BUSOlA VSC BUSOlCVSA BUSOlA BUS03AVRA 3.0159 59.19 BUS03BVRB BUS03AVRA BUS03CVRC BUS03AVRA 42.0+0 POS NEG iDCnl POS 0.001 iDCnl 1* 00+8 iDCn2 NEG 0.001 iDCnZ 1.00+5
' ' '

qqTmr

= POS

NRG

-140.00 100.00 2POS 2NEG 3POS BLANK BLANK BEGIN BLANK 94500.0 -94500.0 189000 .o NEG RECORD ENDING NODE VOLTAGE OUTPUT RECORD ENDING PLOT NEW DATA CASE RECORD ENDING ALL DATA CASES

VI. ACKNOWLEDGMENT The authors acknowledge EPRI, TVA and AEP for their ongoing support and pioneering spirit for developing FACTS technology. W. REFERENCES
[l] Advanced Static VAR Compensator Using Gate Turn-off Thyristorsfor Utility Applications, L. Gpgyi, N. 6. Hingorani, P. R. Nannery and N. Tai, CIGRE paper No. 23-203,1990. f Advanced Static VAR [2] Vector Analysis and Control o Compensators, C. D. Schauder and H. Mehta, IEE PROCEEDINGS-C, Vol 140, NO.4, July 1993. [3] Static Synchronous Series Compensator: A Solid-state Approach to the Series Compensation o f Transmission Lines, L. Gyugyi, C. D. Schauder and K. K. Sen, 96 WM 120-6 PWRD, IEEE PES Winter Meeting, 1996.
[4]

ella

BUSOlA

l.OOc8

ellb BUSOlB ellc BUSOlC e2a e22a e2b e22b e2c e22c e22a e22b e22c TRANSFORMER 9999 lINV0lA 2ella TRANSFORMER lINVOlB 2ellb TRANSFORMER lINV0lC 2ellc TRANSFORMER
9999

1.00+8

A Unified Power Flow Control Conceppt for FZexibZe AC

1.00+8 1.00+8 1.OOt8 1.00+8 1.00+8

1.00+8 1.00+8

T1A 0.892723.679 1.0 1.0 0.892723.679 T1B 0.892723.679 1.0 0.892723.679 1.0 T1C 0.892723.679 0.892723.679
1.0 1.0

9999

T2A

Transmission Systems, L. Gyugyi, B E PROCEEDINGS-C, Vol 139, No. 4,July 1992. [5] The UniJied Power Flow Controller: A New Approach to Power Transmission Control,'' L. Gyugyi, C. D. Schauder, S. L. Williams, T. R. Rietman, D. R. Torgerson, and A. Edris, 94 SM 474-7 PWRD, IEEE PES Summer Meeting, 1994. [6] Operation of the Unified Power Flow Controller (UPFC) Under Practical Constraints, C. D. Schauder, L. Gpgyi, M. R. Lund, D. M. Hamai, T. R. Rietman, D. R. Torgerson and A. Edris, PE-511-PWRD-0-11-1996,IEEE PES Winter Meeting, New York. [7] SSSC - Static Synchronous Series Compensator: Theov, Modeling, and Applications, K. K. Sen, PE-862-PWRD-0-041997, IEEE PES Summer Meeting, Berlin, Gemany.