IBM Assembly Language Coding (ALC) Part 1

IBM Mainframe Assembler Language Coding
Main Storage
Main storage (memory) is measured in terms of 8-bit bytes and an address is assigned to each. The first byte is assigned address zero, the second byte address one, etc. Main storage is directly addressable and provides for high-speed processing of data. Both data and programs must be loaded into main storage from input devices before they can be processed. The amount of main storage available depends on the model of the CPU. Mainframes today (1998) can have up to 2 Gigabytes of real memory. Worldspan has mainframes with 2 Gigabytes of real memory. This means that byte addresses on such a computer run from 0 to 2,097,143,807 (7CFFDFFF in hex).
last updated 12/29/99

General Registers Each processor (CPU) contains 16 General Purpose Registers. The registers are numbered 0 - 15 (0 - F in hexadecimal notation). Each register contains 32 bits or the equivalent of four bytes of main storage. The bits within each register are numbered 0 - 31 from left to right. The General Registers are used to contain binary data in the form of accumulators, counters or in conjunction with binary arithmetic operations. In addition, 15 of the 16 general registers may be used as base-address and index registers in address generation. Register zero specifies that no base or index is to be applied, and, thus, general register zero cannot be designated as a base or index register.

Program-Status Word The current Program-Status Word (PSW) in the CPU contains information required for the execution of the currently active program. The PSW is 64 bits in length and includes the instruction address, condition code, and other control fields. In general, the PSW is used to control instruction sequencing and to hold and indicate much of the status of the CPU in relation of the program currently being executed.
PSW bits
18 19
32 33
Instruction Address
63
Condition Code
Address Mode
Condition Code (CC): Bits 18 and 19 are used to contain the condition code. The condition code is set to 0, 1, 2 or 3, depending on the result obtained in executing most arithmetic and logical operations as well as some other operations. Addressing Mode: Bit 32 controls the size of effective address generation. When the bit is zero, 24-bit addressing is specified. When the bit is one, 31-bit addressing is specified. Instruction Address: Bits 33 - 63 form the instruction address. This address designates the location of the leftmost byte of the next instruction to be executed.
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Assembler Programming Conventions names/tags/labels must begin in column 1. They : should be 8 characters or less can only consist of A - Z, 0 - 9, $, @, # must start with a letter or national character there are company naming standards for labels. operation codes should begin in column 10. operands should begin in column 16 and must not continue beyond column 71. lower case (or a mixture of cases) is not recognized by the assembler for labels or operands. to continue a line: stop coding at column 71 or before put any non-blank character in column 72 (requires command - set trunc 72) start the next line in column 16 to code comments: leave at least one space after the operands, then code comments out to column 71 or place an asterisk in column 1 and code comments in columns 2 - 71 comments are not included in the object module, but they are printed on the assembly listing. They help provide narrative documentation of the program.

Types of Instructions Machine Instructions: cause the system to execute the program instructions one by one at run time. e.g. MVC, LR. Machine Instructions are produced by the Assembler. Assembler instructions: are instructions to the assembler program. They are interpreted by the Assembler at assembly time e.g. DS, DC. The Define Storage instruction will not produce any object code but the Define Constant will. Macro instructions: are expanded by the assembler into several machine instructions to save development time e.g. OPEN, CLOSE, GET, PUT.

Machine Instructions Characteristics The following statements are generally true about the S/370 formats (there are some exceptions). RR format: The mnemonic operation code ends in R. Two register operands. The result of the operation is placed in the first operand. RX format: One register operand and one storage operand. The storage operand is addressed by the left-most byte. The storage operand is usually boundary aligned. The storage operand is usually fixed length, i.e. halfword, fullword, doubleword. RS format: Two register operands and one storage operand. SI format: One storage operand (one byte in length) and one byte of immediate data within the instruction. The immediate data operates on the first operand.

Machine Instructions Characteristics SS format: Two storage operands. The result of the operation is placed in the first operand. Each operand is addressed by the left-most byte. The length codes in the machine language instruction is one less than the total number of bytes specified in the operands. The method of instruction execution depends on the presence of one or two length codes in the instruction. SS1 format, one length code: The maximum operand size is 256 bytes. Operands are operated upon left to right within each operand. The length of the first operand controls the execution. Therefore, both operands should be the same length. SS2 format, two length codes: Each operand has its own length. The maximum operand size is 16 bytes. Operands are operated upon from right to left within each field. (The data address is still the left-most byte; the length code is used to get over to the right-most byte for execution.)

Load Fullword
R6,CE1CR0
CE1CR0 before: 00 F2 CE 83
CE1CR0 after: 00 F2 CE 83
Reg 6 before: 00 00 10 0C
Reg 6 after: 00 F2 CE 83

Relative Address An arithmetic expression appended to a symbol allows modification of the displacement that is generated by the assembler. L L R3,FIELDA+12 R4,FIELDA+((3-1)*4) R3 After FIELDA 00 00 00 00 00 00 00 00 00 00 00 00 FF EE DD CC 00 R4 After 00 00 DD 00 00 00 CC

Move Characters Instruction
The Move Characters instruction actually copy data from one memory location to another. MVC The Move Character copies L bytes (where L <= 256) from the memory location designated by the 2nd operand to the memory location designated by the 1st operand. The result is a byte-for-byte move.
MVC MVC MVC MVC D1(L,B1),D2(B2) 10(17,R3),0(R4) LABEL1,LABEL2 10(17,R3),LABEL2
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Move Character Example
VAL1 VAL2
DC DC
C'ABCDE' C'1*!?2'
MVC VAL2,VAL1 VAL2 before: 1 * ! ? 2
VAL2 after: A B C D E
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RESULT VAL1 VAL2 VAL3 MVC
DC DC DC DC
CL8' ' C'ABCD' C'XY' C'GARBAGE'
RESULT,VAL1
RESULT before: b b b b b b b b
RESULT after: A B C D X Y G A
MVC
RESULT(4),VAL1
RESULT before: b b b b b b b b
RESULT after: A B C D b b
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DC DC DC DC
RESULT+4,VAL2
before: b b b b b b b b A B C D X Y
RESULT
VAL1
VAL2
after: b b b b X Y G A R B A G X Y
RESULT
VAL1
VAL2
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B1 DC OUTPUT DS MVC
C' ' CL133
OUTPUT,OUTPUT-1
before: b ? ? ? ? ? ? ? ? .....
B1 OUTPUT
after: b b b b b b b b b .....
B1 OUTPUT
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DC DC DC DC
RESULT+4(2),VAL2
before: b b b b b b b b A B C D
RESULT
VAL1
after: b b b b X Y b b A B C D
RESULT
VAL1
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Model Program
BEGIN NAME=ZOO1,VERSION=II *=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=* *=-= ZOO1 -- PROGRAM 0 =-=* *=-= THIS PROGRAM ... =-=* *=-= =-=* *=-= INPUT -- B@x =-=* *=-= OUTPUT -- SCREEN =-=* *=-= =-=* *=-= LEVELS -- D0 -- A-06-IMG INPUT MESSAGE BLOCK =-=* *=-= =-=* *=-= REGISTERS -- R0 -=-=* *=-= -- R1 -=-=* *=-= -- R2 -=-=* *=-= -- R3 -=-=* *=-= -- R4 -=-=* *=-= -- R5 -=-=* *=-= -- R6 -=-=* *=-= -- R7 -=-=* *=-= -- R14 -=-=* *=-= -- R15 -=-=* *=-= =-=* *=-= WORKAREAS -- EBW000-063 -- OUTPUT MESSAGE LINES =-=* *=-= -- EBXnnn-nnn -- . =-=* *=-= =-=* *=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=* * MI0MI REG=R1 ADDRESABILITY TO INPUT MESSAGE L R1,CE1CR0 BASE OF INPUT MESSAGE * *=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=* *=-= BODY OF PROGRAM =-=* *=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=* * GET , GET AN INPUT RECORD * PUT , DISPLAY A LINE OF OUTPUT * *=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=* *=-= CLOSING ROUTINES =-=* *=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=* * * PUTEXIT , DISPLAY A LINE OF OUTPUT AND * TERMINATE THE ENTRY *=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=* *=-= DEFINE CONSTANTS =-=* *=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=* * FINIS , TERMINATE TPF PROGRAM END , TERMINATE ASSEMBLY
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Entry Control Block R9
.....
Workarea ..
1/A
EBW000 - EBW103 104 Bytes
nnnnnnnn D0 - CE1CR0 - a core address nnnnnnnn D8 - CE1CR8 - a core address
.....
Workarea ..
2/B
EBX000 - EBX103 104 Bytes
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EXERCISE #1 PROGRAM 1. Instructor will walk the class through this exercise. Save the input message. Move the input message to a designated output area. Display the message on the terminal. Requires two instructions added to shell. Shell is ZOO1ii assemble. Input: b@lastname+ Move data (length 15) from input message block to EBX000-014. Move data (length 15) from EBX000 to EBW000-014. Use the PUTEXIT macro. 'HARDCOPY' the source code and the listing. When above is working - modify program to handle length equal to number of characters in your last name.
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Address Generation Prior to the advent of the System/370 Extended Architecture (370-XA) feature, storage addresses were limited to a 24-bit binary number, up to 16,777,216 (decimal) or 16 mega-bytes of addressable storage. While retaining this capability, 370-XA provides for storage addresses to be a 31-bit binary number, up to 2,147,483,648 (decimal) or 2 giga-bytes of addressable storage Bimodal Addressing: The addressing mode is controlled by bit 32 of the Program Status Word (PSW). Instructions are provided that examine and set the mode. This permits combining old programs, which must operate in 24-bit mode, and new programs, which can take advantage of the 31-bit addressing mode.
PSW bits
32 33
40
24-bit address 31-bit address
63
Address Mode Bit
Address Mode Bit: Off (0) = 24-bit addressing On (1) = 31-bit addressing
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Address Generation The address used to refer to main storage either is contained in a register designated by the "R" field in the instruction or is calculated from the following three binary values: Base Address A binary number contained in a general register specified by the program in a 4-bit field called the "B" field in the instruction. Index A binary number contained in a general register designated by the program in a 4-bit field called the "X" field in the instruction. It is included only in the address specified by the RX instruction format. Displacement A 12-bit number contained in a field called the "D" field in the instruction. The displacement provides for relative addressing designated by the base register. A zero in either the "X" or "B" fields indicates the absence of the corresponding address component. For the absent component, a zero is used in forming the address, regardless of the content of register zero. A displacement of zero has no special significance (it simply means 0 displacement). Because of the significance of zero indicating the absence of a component of an instruction, register zero should never be used as a Base register or Index register in any instruction. Register zero cannot be designated as containing a branch address. A value of zero in the R2 field causes the instruction to be executed without branching.
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Address Generation In computing the address, an intermediate sum is first calculated. The base address and index value are treated as 32 bit binary integers. The displacement is treated as a 12-bit binary integer, and 20 zeroes are appended on the left. The three are added as 32-bit binary numbers, ignoring overflow. The sum is always 32 bits long and is used as an intermediate value to form the effective address. When an instruction specifies that the address is contained in a general register, the register contents are used as the 32-bit intermediate value. The effective address is formed from the intermediate value as follows: In the 24-bit addressing mode, the rightmost 24 bits of the sum are retained. The leftmost 8 bits are set to zero. In the 31-bit addressing mode, the rightmost 31 bits of the sum are retained. The leftmost bit is set to zero. The bits of the address are numbered 8-31 and 1-31, respectively, corresponding to the numbering of base-address and index bits in a general register:
24-bit address 0 8 31 01 31-bit address 31
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Assembler Procedure Phase 1 Functions Maintenance of location counter Address assignment Construction of symbol table Terms The location counter is a binary counter that contains the 24-bit address of the current instruction or data field. This counter is initialized to the value in the 'Start' statement operand. Thereafter, as the assembler assigns addresses, the location counter is incremented by the number of bytes required by each assembled instruction or data field. The Symbol Table is constructed from the symbols appearing in the name field of each instruction or data field. Each entry contains the symbol, the 24-bit binary address assigned by the assembler and the length attribute.
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Assembler Procedure Phase 2 Functions Construction of a base register table. Assignment of base and displacement values to instruction operands. Generation of object module and assembly listing. Terms The base register table is constructed to contain the register number specified in the second operand of the Using statement and the value that the base register will contain at execution time (specified in the first operand of the Using statement). The entry is made when the assembler encounters the Using statement. When a symbolic operand is encountered in an instruction requiring a storage address, the assembler uses the symbol table to obtain the 24-bit address of the symbol. The difference between that address and a promised base register value is used as the displacement in the assembled operand. (This number must not excede 12 bits - FFF16 - 409510.)
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Number Systems Background It is important to be familiar with not only the decimal numbering system but also the binary and hexadecimal numbering systems. The last two numbering systems are used extensively in the data processing environment. The number of digits in a given numbering system determines its base power. The value of each digit in a number is a multiple of the base power of the number. This is referred to as positional notation or positional value. Positional Values Within Numbers Decimal Contains ten digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 with a base power of ten. The value of the decimal number 423 is computed as:
4 4 x 102 400 2 2 x 101 20 3 3 x 100 3 = 423
+ +
+ +
Binary Contains two digits 0 and 1 with a base power of two. The value of the binary number 10101 is computed as:
1 1 x 24 16 + + 0 0 x 23 0 + + 1 1 x 22 4 0 + 0 x 21 + 0 + + 1 1 x 20 1 = 2110
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Number Systems Hexadecimal Contains sixteen digits 0 through 9 and A through F with a base power of sixteen. The positional values of the digits in the hexadecimal number A423 is computed as follows:
A 10 x 163 40960 163 = 4096 + + 4 4 x 162 1024 162 = 256 + + 2 2 x 161 32 161 = 16 + + 3 3 x 160 3 = 42,01910 160 = 1
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Number Systems It is also important to become familiar with the representations of the first sixteen binary and hexadecimal integers since both forms are used extensively in the data processing environment. Representations of Integers Decimal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Binary
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 10000
Hexadecimal
0 1 2 3 4 5 6 7 8 9 A B C D E F 10
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Number Systems Binary Addition and Subtraction Addition is a simple matter since there are only four rules to learn: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1 and 1 + 1 = 10 (two in binary). In the last rule, a carry of 1 is generated and must be added to the next higher-order digit, an operation analogous to the handling of carries in decimal addition. Some examples: 10110 + 1100 ---------100010 10110 + 11 ---------11001 11111 + 1 ----------100000 11001 + 11001 ---------110010
Subtraction is also straight forward, since the only situation in which a borrow operation can arise is that of subtracting 1 from 0. A borrow of 1 is necessary when the first digit is smaller than the second. Examples: 10110 101 ----------10001 10110 - 1010 ----------1100 10000 1 ----------1111 10010 - 1101 ----------101
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Number Systems Hexadecimal Addition and Subtraction In addition, the sum is a single digit if its value is less than sixteen; otherwise a carry of 1 is generated. Examples: 4 + 6 ---A 4 + A ----E A + 6 ----10 DE + C8 -----1A6 FFF + 1 ------1000
In subtraction, a borrow of 1 (decimal sixteen ) is necessary. Examples: B - 6 -----5 10 - 8 ------8 18 - 9 -----F DE - C8 ------16 40C E -------3FE
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Number Systems Conversions of integers from one base to another The simplest method is to utilize the Hexadecimal and Decimal Conversion Table located at the back of the Enterprise Systems Architecture/390 Reference Summary as follows: Decimal to Hexadecimal Follow the instructions on the conversion table and convert the decimal number to its hexadecimal equivalent. Decimal to Binary First convert the decimal number to its hexadecimal equivalent. Then convert each hexadecimal digit to its four-bit binary equivalent. Binary to Hexadecimal Convert every four consecutive binary digits to their hexadecimal equivalent starting from the right-hand digit and adding zeroes on the left, if necessary. Binary to Decimal First convert the binary number to its hexadecimal equivalent. Then convert to decimal using the conversion table. Hexadecimal to Decimal Convert the hexadecimal digits to decimal using the conversion table. Hexadecimal to Binary Convert each hexadecimal digit to its four-bit binary representation.
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Formating The Source Listing TITLE The TITLE instruction provides for headings for each page of the assembly listing of the source module. The SPACE instruction inserts one or more blank lines in the listing of the source module. The EJECT instruction stops the printing of the assembly listing on the current page and continues printing on the next page. The END statement terminates the assembly of a program. It must always be the last statement in the source module.
SPACE
EJECT
END
Example:
LABEL
TITLE 'THIS IS PROGRAM XYZ1' SPACE 2 EJECT END
These and the DS/DC instructions are explained in the HLASM (High Level Assembler) Language Reference SC26-4940 which can be found in the HLASM Bookshelf.
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Conversion from /to EBCDIC and Packed Decimal Format From: To: Some guidelines: 1. The first operand is the result field. The second operand undergoes no changes. 2. L1 and L2 are lengths of the 2 operands. Each is required to be less than or equal to 16. The lengths need not be equal but care must be taken not to lose significant digits. 3. The sign contained in the low order byte in each format will be carried through the conversion. 4. No validity check is made on the two fields - so you can pack or unpack anything. 5. Neither instruction sets the condition code. 6. Processing proceeds right-to-left through the operands.
PACK UNPK
D1(L1,B1),D2(L2,B2) D1(L1,B1),D2(L2,B2)
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Conversion from/to Binary and Decimal Format
CVD CVB R1,D2(X2,B2) R1,D2(X2,B2)
Some guidelines: 1. The Convert to Decimal instruction converts a 32-bit binary integer into an 8-byte packed decimal number. The binary integer must be in a register and the receiving field will be 8 bytes long. 2. The Convert to Binary instruction converts an 8-byte packed decimal number into a 32-bit binary integer in a register specified by the R1 operand. The sending field must be a valid packed decimal number.
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Pack (Packed Decimal Zoned Decimal)
PACK
PACKED,ZONED
Before
00 00 00 00
PACKED
F1 F2 F3 C4
ZONED
After
00 01 23 4C
PACKED
F1 F2 F3 C4
ZONED
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Pack (Packed Decimal
PACK
Zoned Decimal)
PACKED(3),ZONED(4)
Before
00 00 00 00
PACKED
F1 F2 F3 C4
ZONED
After
01 23 4C 00
PACKED
F1 F2 F3 C4
ZONED
36

Pack (Packed Decimal
PACK
Zoned Decimal)
ZONED,ZONED
Before: F1 F2 F3 C4
ZONED
After: 00 01 23 4C
ZONED
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Conversion from Packed Decimal Format to Binary CVB R6,PKDDBL
Before 00 F1 88 08
REG 6
00 00 00 00 00 00 10 1C
PKDDBL
After 00 00 00 65
REG 6
00 00 00 00 00 00 10 1C
PKDDBL
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Multiply Register
MR
R6,R3
Before: FA 21
REG 6
19
1C
00
REG 7
00
01
23
00
REG 3
00
00
04
After: 00
REG 6
00
00
00
00
REG 7
00
04
8C
00
REG 3
00
00
04
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Conversion from Binary Format to Decimal
CVD
R6,PKDDBL
Before: 00 00 00 64
REG 6
00 10 20 30 40 50 6F FF
PKDDBL
After: 00 00 00 64
REG 6
00 00 00 00 00 00 10 0C
PKDDBL
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UNPK (Zoned Decimal Packed Decimal)
UNPK
ZONED,PACKED
Before:
F1 F2 F3 C4
ZONED
45 6D
PACKED
After:
F0 F4 F5 D6
ZONED
45 6D
PACKED
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UNPK (Zoned Decimal
UNPK
Packed Decimal)
NOTBIG,TOOBIG
Before: 00 00 00 00
NOTBIG
01 23 45 6C
TOOBIG
After: F3 F4 F5 C6
NOTBIG
01 23 45 6C
TOOBIG
Truncation of significant digits occurs. The receiving field was not large enough to receive all digits, but processing continues with, perhaps, undesireable results.
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UNPK (Zoned Decimal Packed Decimal)
UNPK
PACKED,PACKED
Before: 01 23 45 6C
ZONED
After: ?? ?? ?? C6
ZONED
Do not Unpack a field into itself!!
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Move Zone
This instruction copies only the left-most 4 bits of each of the designated bytes of the source fields into the destination fields. The right-most 4 bits are not altered. Format: MVZ SAVE DC MVZ SAVE before: F1 F2 F3 C4 D1(L1,B1),D2(B2) Z'1234' SAVE+3(1),SAVE+2
SAVE after: F1 F2 F3 F4
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EXERCISE #2 PROGRAM 2. Input: rate hours name. Message: b@hhrrname+ name is max 15 characters Process: calculate gross pay; rate x hours. Input and output numbers are character format. Arithmetic is in binary format. Output: name gross pay. Name occupies first 15 positions starting in position 1. Gross salary starts in 3rd position after name. Gross salary has no editing characters ($ , .).
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Define Constants - Format {LABEL} DC {D} T {LN} 'CONSTANT'
{LABEL} - Label or name DC - Operation code {D} - Duplication factor T - Type (B, C, Z, P, H, F, D, X, A, V) {LN} - Length 'CONSTANT' - Actual constant value (nominal value) Items within brackets are optional. Constant data, within single apostrophes, must be coded. Maximum length of 256 for define constants.
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Types of Constants for DC Instructions Type Code Meaning C Text or characters
Binary Integer (4 bytes) Binary integer (2 bytes) Binary number (8 bytes)
Comments Each character is converted to its 8-bit EBCDIC representation. The characters are stored in consecutive bytes. Padding occurs with blanks in unoccupied bytes to the right. Truncation may occur, on the right. Fullword The number is converted to its 32-bit binary integer format (including sign). Max value 2,147,483,647 Halfword The number is converted to its 16-bit binary integer format (including sign). Max value 32,767 Doubleword Approximate max value: 7.2 x 10(75). Floating point constants not used in TPF.
Alignment Byte
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Types of Constants for DC Instructions Type Code P
Meaning Decimal numbers (packed)
Alignment Byte
Decimal numbers (zoned)
Byte
Hexadecimal Byte
Comments Each digit is converted to a 4-bit binary integer. Max of 31 digits. Decimal point is ignored, e.g. P'3.5' is the same as P'35'. Zero fill with 4-bit zeroes to the left and truncation is on the left. Each digit is converted to an 8-bit EBCDIC format, max of 16 digits. The decimal point is ignored as in packed format. Zero fill with character zeroes (F0) to the left and truncation is on the left. Each digit must be one of the 16 hex digits and will be represented by a 4-bit binary number. Decimal point not allowed. Zero fill left, truncation on left.
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Types of Constants for DC Instructions Type Code B
Meaning Bit data
Alignment Byte
Address constant Address constant
Fullword
Fullword
Comments The bits are represented as given in the DC statement 8 bits per byte. Zero fill to the left and truncation on the left. The value of the symbol as a binary integer will be be stored. Space is reserved for an external address.
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Define Constant - Object Listing
LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT 3 ** 4 ** CONSTANTS OF 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ** DOUBLE HEX
ZERO 000000 000008 000009 00000C 000010 000012 000013 000014 000015 0000000000000000 00 000000 00000000 0000 0C 00 F0 C0 DC DC D'0' X'0' F'0' H'0' P'0' B'0' C'0' Z'0' OF ONE X'1' F'1' H'1' P'1' B'1' C'1' Z'1'
000016 000017 000018 00001C 00001E 00001F 000020 000021
01 00 00000001 0001 1C 01 F1 C1
FULLWORD DC HALFWORD DC DECIMAL DC BINARY DC CHAR DC ZONED DC ** ** CONSTANTS ** AHEX DC AFULL AHALF ADEC ABIN ACHAR AZONE DC DC DC DC DC DC
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Define Constant - Object Listing
LOC OBJECT CODE ADDR1 ADDR2 STMT 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SOURCE STATEMENT ** ** CONSTANTS OF -1 ** BFULL DC F'-1' BHALF DC H'-1' BDEC DC P'-1' BCHAR DC C'-1' BZONE DC Z'-1' ** ** CONSTANTS OF ONE ** WITH PADDING ** CDEC DC PL8'1' CCHAR DC CL8'1' CZONE DC ZL8'1' END
00002E 000030 000034 000036 000037 000038
0000 FFFFFFFF FFFF 1D 60F1 D1
000039 000000000000001C 000041 F140404040404040 000049 F0F0F0F0F0F0F0C1
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Define Constant - Halfword Data HALF1 DC HALF1 H'+18' 00 12
HALF2
DC HALF2
H'18' 00 12
HALF3
DC HALF3
H'-18' FF EE
HALF4
DC HALF4
2H'4' 00 04 00 04
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Define Constant - Fullword Data FULLWD1 DC F'+32' 00 00 00 20
FULLWD1
FULLWD2
DC
F'32' 00 00 00 20
FULLWD2
FULLWD3
DC
F'-32' FF FF FF E0
FULLWD3
FULLWD4
DC
2F'32' 00 00 00 20 00 00 00 20
FULLWD4
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Multiply Fullword
R6,FULL
Before: DO N'T CA RE
REG 6
00
REG 7
00
00
10
00
FULL
00
00
04
After: 00
REG 6
00
00
00
00
REG 7
00
00
40
00
FULL
00
00
04
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Multiply Halfword
MH
R5,HALF
Before: 00
REG 5
00
00
0A
00
HALF
03
After: 00
REG 5
00
00
1E
00
HALF
03
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Add Register
AR
R3,R4
Before: 01
REG 3
A2 30
11
02
REG 4
13
75
A6
After: 03
REG 3
B5
A5 B7
02
REG 4
13
75
A6
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Subtract Register
SR
R3,R4
Before: 00
REG 3
00
00
39
00
REG 4
00
00
12
After: 00
REG 3
00
00
27
00
REG 4
00
00
12
58

Divide Register
DR
R6,R2
Before: 00
REG 6
00
00
00
00
REG 7
00
00
2E
00
REG 2
00
00
08
After: 00 00 00 06 00 00 00 05
REG 6 (REM.)
REG 7 (QUOTIENT)
00
REG 2
00
00
08
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Add Fullword
R3,FULL
Before: 00
REG 3
00
00
06
00
FULL
00
00
04
After: 00
REG 3
00
00
0A
00
FULL
00
00
04
60

Subtract Fullword
R3,FULL
Before: 00 00 00 0A 00 00 00 C8
REG 3 (+10)
FULL (+200)
After: FF FF FF 42 00 00 00 C8
REG 3 (-190)
FULL (+200)
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Divide Fullword
R6,FULL
Before: 00
REG 6
00
00
00
00
REG 7
00
36
92
00
FULL
00
00
03
After: 00 00 00 02 00 00 12 30
REG 6 (REM.)
REG 7 (QUOTIENT)
00
FULL
00
00
03
62

Divide Fullword Remember that the machine will look at all 8 bytes of the two registers as the dividend. Therefore, you must make certain that the sign bit (bit 0 of the 64 bits) reflects the true sign of the number. You must also propagate the sign of the number through the padding bits in the even register. This is a very good way of doing that (presuming the dividend does not exceed a fullword): M 6,=F'1'
Regardless of the value in the odd register, the dividend now occupies registers 6 and 7 with the correct sign and padding.
63

Add Halfword
AH
R3,HALF
Before: 00
REG 3
00
00
0A
00
HALF
03
After: 00
REG 3
00
00
0D
00
HALF
03
64

Add Halfword
AH
R3,HALFNEG
Before: 00 00 00 0A FF F1
REG 3 (+10)
HALFNEG (-15)
After: FF FF FF FB FF F1
REG 3 (-5)
HALFNEG (-15)
65

Subtract Halfword
SH
R3,HALF
Before: 00
REG 3
00
00
0A
00
HALF
03
After: 00
REG 3
00
00
07
00
HALF
03
66

Load Register
LR
R4,R5
Reg 4 before: 00 81 34 77
Reg 5 before: 00 00 12 11
Reg 4 after: 00 00 12 11
Reg 5 after: 00 00 12 11
67

Load Halfword
LH
R7,TWOBYTS
Reg 7 before: before: 00 12 33 F0
TWOBYTS
00
48
Reg 7 after: 00 00 00 48
TWOBYTS after: 00 48
68

IBM Assembly Language Coding (ALC) Part 1

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MVC VAL2,VAL1 VAL2 before: 1 * ! ? 2

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