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Design Considerations for High-Frequency Crystal Oscillators Digitally Trimmable to Sub-ppm Accuracy
Qiuting Huang, Senior Member, IEEE, and Philipp Basedau, Student Member, IEEE
Abstract The current consumption of crystal oscillators is usually determined by the steady-state amplitude requirement, rather than the minimum transconductance for oscillation to exist. In a bipolar implementation transconductance is proportional to current, so that current consumption scales with frequency and load capacitance in the same way as transconductance. In a complementary metaloxidesemiconductor (CMOS) implementation, current scales as the square of transconductance. It is therefore important to distinguish current from transconductance in power estimation for high frequency oscillators. Analytical expressions relating current to steady-state amplitude are used in this paper to estimate the minimum power required for a crystal oscillator at a given frequency. A 78 MHz crystal oscillator is described, which forms part of a regulated system in a pager where the oscillation frequency is controlled digitally to subppm accuracy. The oscillator can be pulled from 665 ppm to the required frequency with 0.2 ppm accuracy, with a maximum current consumption of 197 A. The circuit has been fabricated in a 1-m CMOS technology. The measured phase noise is 0113 dBc/Hz at 300 Hz offset. Index Terms CMOS oscillators, crystal-oscillator, digital trimming, high-frequency oscillators, low power, oscillation amplitude, sub-ppm accuracy.

I. INTRODUCTION RYSTAL oscillators play an important role in modern electronic circuits and systems. The resonant frequency of a crystal is accurately dened and its quality factor is very high, usually more than 10 000. Whenever an application requires precise denition of oscillation frequency, low phase noise and low power, a crystal oscillator is the best candidate. While frequency accuracy and low power can be achieved indirectly by phase-locking a voltage-controlled LC oscillator to a crystal oscillator at low frequency, extremely low phase noise can only be achieved by the high resonator of the crystal at the desired oscillation frequency directly. As the application frequency becomes higher, however, both the requirement of the crystal and that of power consumption become higher. In this paper, we use the example of a 78MHz crystal oscillator for paging application, to illustrate the relationship between power consumption and oscillation frequency, precision of the center frequency, as well as low phase noise.
Manuscript received September 8, 1996; revised May 15, 1997. The authors are with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich CH-8092 Switzerland. Publisher Item Identier S 1063-8210(97)09106-3.

In paging systems based on the POCSAG standard, digital data are transmitted using binary FSK modulation. Different RF carrier frequencies are used, ranging from 150 MHz to around 900 MHz. The higher the RF frequency, the higher the relative accuracy requirement for the local oscillators, as a very small fractional error of a high local oscillator frequency translates to a large offset for the signal frequency at the low kilohertz range. At 470 MHz the local oscillator accuracy requirement is a fraction of 1 ppm. For single channel paging systems, a popular and simple way to generate the local oscillator signal is to multiply the output of a suitable crystal oscillator and select its nth harmonic [1]. A complete pager receiver chip [1] is widely used by RF system designers, for which the recommended oscillator frequency for 470 MHz pagers is 78 MHz using overtone crystals. A variable capacitor is envisaged for ne tuning the oscillator frequency, in production, to the required accuracy, as are many external passive capacitors and inductors. Requested by pager system designers, we developed a fully integrated complementary metaloxidesemiconductor (CMOS) oscillator to reduce the number of passive components, hence the cost and space, and to make accurate tuning of oscillation frequency digitally, so that both production tuning and digital tuning during pager operation are possible. The phase noise required by the customer was below 92 dBc at 300 Hz offset from the carrier at 78 MHz. Fundamental crystals are used, instead of overtone crystals, because the former have a wider pulling range. In the following, we shall describe the oscillator design as it relates to digital tuning for high accuracy, high frequency and low power. A CMOS technology is used for reasons of cost. The question of how power is related to crystal parameters, frequency and transistor geometry will also be answered. II. BASICS OF CRYSTAL OSCILLATOR DESIGN One of the best known oscillator structures is the so called three-point oscillator [2] shown in Fig. 1. Depending on which of the three points is ac ground, the circuit is also known as Colpitts, Pierce, or Clapp oscillator. Capacitors and transform the transconductance of into a frequency dependent negative resistance, in series with and . The negative resistance can be shown to be (1)

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Fig. 1. The basic structure of a three point oscillator.

In a crystal oscillator, the crystal static capacitance is in parallel with the -( ) combination, so that the negative resistance that the - part of the crystal sees into the A node is somewhat less than that given by (1). In practical designs and are made much higher than in which case (1) can be used to estimate the minimum (critical) transconductance ( ) required to compensate the loss due and sustain oscillation to (2) is the motional resistance of the resonator. For where the best trade-off between frequency stability and required transconductance, and should be equal [2]. This means that for the oscillation to exist at all, the required transconductance is proportional to the square of both the load capacitance and the oscillation frequency. In a CMOS realization, the . current consumption is roughly a quadratic function of This might mislead some people to believe that power consumption in such an oscillator increases as the fourth power of both the load capacitance and the oscillation frequency. If one refers to the state-of-the-art low-power CMOS crystal oscillators published in recent years, low power consumption means 2.3 A for 2.1 MHz [3]. Scaling the frequency to 78 MHz while keeping the rest of the parameters identical would require a current consumption of nearly 6 A! This seems to suggest that unless bipolar transistors are used, a low power crystal oscillator is very difcult at high frequencies, because the improvement that can be expected by increasing s W/L ratio, even by 100 times, and the improvement of motion resistance of higher frequency crystals, will still be insufcient to bring the current down to a milliamp or so. Increasing the width of also increases the parasitic capacitance due to the gate. The last option of reducing the load capacitance is also seriously restricted by the requirement of a trimming capacitor bank in our design. III. POWER CONSUMPTION IN CMOS OSCILLATORS In order to estimate power consumption accurately, it is important not only to look at the minimum transconductance required to start oscillation, but also the steady-state oscillation amplitude. In the local oscillator of an RF receiver, the amplitude is required to exceed certain level, 0 dBm for example, to drive the switch transistors of a mixer sufciently on and off, which minimizes noise gure. In frequency synthesizers, the amplitude must be sufciently high to drive the digital prescaler. In our application, the oscillator output should be more than 100 mV , to drive the frequency multiplier. Amplication after the oscillator is usually not power efcient,

as the amplier must then have much higher unity-gain bandwidth than the oscillation frequency. If steady-state amplitude is taken into consideration, then the power consumption requirement could be formulated differently from that purely determined by start-up conditions. In bipolar oscillators, is directly proportional to current, so that there is no extra degree of freedom for the designer. The relationship between bias current and steady state amplitude is well known, the latter is proportional to the former. Discussing amplitude requirement is therefore the same as discussing the minimum for start-up. In CMOS, there are more degrees of freedom in the oscillator design. The same can be realized by different combinations of bias current and transistors W/L ratio. To the authors knowledge, no analytical expression has been published to relate the steady state amplitude to the other electrical parameters of the circuit. It has therefore been difcult to obtain an estimate of power consumption based on amplitude requirement, except in the limiting case when a MOS transistor works in weak inversion and therefore resembles a bipolar transistor [4]. We have recently performed a time domain analysis of the three point oscillator and obtained exact expressions for the steady state amplitude in three-point oscillators realized by MOS transistors [5]. If s transconductance is barely required, the oscillation is very higher than the critical weak. For the ac current through has 100% duty cycle (see below). It can be shown that the oscillation amplitude across capacitor is given in this case by the following equation: (3) s transconductance coefcient times its where equals W/L ratio. In practical designs, is usually designed to have much In this case, more transconductance than just the voltage swing across s gate is so high that turns off during part of each period of oscillation. If the duty cycle of s current is we can dene (4) to facilitate the derivation of the steady state oscillation amplitude In (4), represents the steady-state dc bias voltage across the gate-source of transistor and its threshold voltage. With the help of we can show that the steady state amplitude can be derived from the equations below

(5)

(6)

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Fig. 2. Oscillator amplitude, normalized to the Io =gmc ratio, versus cosine of the current duty cycle.

for bipolar implementation applies. The MOSFET rarely works in weak inversion, however, for high frequency operations. The ratio is usually higher than 5, in which case the duty cycle in which the transistor conducts current is 30% or less. The average current during this ontime is therefore three-to-ten times the bias current. At high oscillation frequencies the critical is usually high which in turn requires high current for a practical amplitude. The required current level is then usually too high for MOSFETs with a practical W/L ratio to work in weak inversion during its short on-time. At low frequencies, such as a 32-kHz oscillator for watches, the required current is only a few nano amperes and the situation can be quite different. Returning to the question we had earlier, whether the required power consumption scales as the fourth power of an oscillators frequency, we see that the answer is negative. Most oscillators are designed to have a certain amplitude, this means is usually sized to have substantially higher transconductance than the strict minimum to start oscillation. The current duty cycle in is therefore less than 100% and (5) determines the amplitude According to (5), the bias current must scale as the square of the oscillation frequency to maintain the same . To scale a 2.1-MHz crystal oscillator to 78 MHz with the same amplitude and similar crystal motional resistance, the estimate of the power consumption is now 3 mA. The motional resistance of high frequency crystals can be slightly lower than those of lower frequencies. In our application, however, this reduction in will be limited by the switch on-resistances of the trimming network. The accuracy of the trimming capacitor bank also limits our ability to scale capacitors and to bring the current consumption to submilliamp level. IV. DIGITAL TRIMMING OF OSCILLATION FREQUENCY As mentioned earlier in the introduction, one of the requirements of the present design is to achieve an oscillation frequency accuracy in the sub-ppm range. On the other hand, the untrimmed accuracy of the crystal resonators available to us is about 35 ppm, including variations due to change in temperature and aging. The only way to tune this frequency is by varying the equivalent capacitance parallel to the resonator. In the three point oscillator, this is the crystals shunt capacitance in parallel with the series combination of and . For frequency stability, capacitors and should be made a few times higher than . This means and should be made variable to cover a wider tuning range. The oscillation frequency of the circuit is approximately given by (7)

Fig. 3. Cosine of oscillator current duty cycle versus ratio between average transconductance and critical gm.

The dependence of the normalized (to ) on is plotted in Fig. 2. Equation (6), on the other hand, is plotted in Fig. 3. It shows that is a monotonic function of the ratio between and For ratio between 1.225 and 10, rises rapidly from 1 to 0.7. According to (5) this would cause the oscillation amplitude to change by 28%. Above 10, the curve is very at so that a change in ratio causes virtually no change in the oscillation amplitude. The role of s transconductance, once it is a few times above the critical value for oscillation, is therefore minor in determining an oscillators steady state amplitude. The parameters that do have a dominant inuence, are the bias current, to which is proportional, and , to which is inversely proportional. Equation (5) has been veried by extensive measurements. Despite the fact that mobility degradation is not taken into account in s I-V characteristic, (5) agrees with measurements to within 10% accuracy [5]. It might seem that in the case of very high W/L ratio, the MOSFET works in weak inversion so that the result

and are the resonators motional inductance where and capacitance, respectively, and is the equivalent load capacitance dominated by and . The fractional frequency is the second term in the brackets in (7), change due to which provides the only way to tune a crystal oscillator. Equation (7) is plotted in Fig. 4, for the nominal characteristic

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(a)

(b) Fig. 5. (a) Fixed and switched part of C1 . (b) Equivalent resistance in series with C1 .

Fig. 4. Resonant frequency as a function of load capacitance (including case capacitance), for different crystal characteristics.

of the crystal, as well as characteristics corresponding to the two limits of frequency deviation. The latter are denoted by point A and point C. From Fig. 4, we see that for one extreme, tuning must take place along the A-B curve. This denes the maximum added trimming capacitance required to cover the upper limit of tuning range. For the other extreme, oscillation frequency at the lower limit must be trimmed back to the nominal, and the C-D curve must be followed. Since C-D is the steepest of the set of tuning curves, it limits the maximum capacitance step in the trimming bank to achieve the desired tuning resolution of 0.20.3 ppm. A small step dened by the steep C-D curve, on the other hand, means that many more steps are needed on the atter A-B curve to cover the same tuning range. A larger tuning capacitor bank results. If we also take into account the 20% tolerance of the values of MOS capacitors as well as stray capacitances, a 10-bit trimming and to achieve 70 ppm network is required for both tuning range. This places a severe limit on our ability to save power by using small values of and , which now consist of two parts each, a variable capacitor bank for frequency tuning, and a xed capacitance. The latter is required for the generation of negative resistance from even when the tuning part is completely switched off. According to (5), the current consumption is proportional to the equivalent resistance in series with and . To minimize power, one of the main concerns is therefore the on-resistances of the switches that form part of the trimming bank. If we represent the xed part of as and the as in series with an equivalent variable part of resistance Rsw of all the switches that are on, as shown in Fig. 5(a), we can estimate the latters inuence on the required current by transforming Fig. 5(a) to that of Fig. 5(b). It can be shown that the equivalent loss resistance in Fig. 5(b), , is approximately related to the switch resistance by the relationship below (8)

The on-resistance of a minimum-sized switch in a typical 1 m CMOS technology is of the order of several kilo-ohms. It is exacerbated by the low supply voltage of 1.9 V, which is specied for worst case battery operation. For the worst case threshold voltage, the available gate overdrive is only 1 V. To reduce this resistance, the width of the switch transistors must be sufciently wide. The gate-width can not be too wide, however, because otherwise the drain-substrate capacitance will be too large, affecting the tuning accuracy when the switch is off. The sizing of the switch, as well as the assignment of xed and variable parts to and , is therefore a tradeoff between accuracy and power consumption. An additional aspect of the trimming capacitor bank is how it should be organized. The most straight forward way is to organize it as a binary weighted array, connected to ground by switches with binary weighted channel widths. Because monotonicity of the tuning curve is an important consideration for the receiver system design, there is a lower limit to the value of the LSB capacitor to ensure sufcient matching accuracy. On the other hand, the capacitor bank can be organized as a parallel array of unit capacitors, and controlled by thermometer codes, as shown in Fig. 6. Monotonicity is guaranteed in this case, because each increase in total tuning capacitance is achieved by adding a new unit capacitor. A parallel array of unit capacitors, however, requires not only many more switches, but also additional decoding logic to realize the thermometer code. Although this would cause the overall silicon area to increase, it allows us to reduce the size of the total tuning capacitance without losing monotonicity. From the point of view of frequency stability, very large and is not required in our application as it will be determined by trimming, and not the crystals inherent and to be just resonance frequency. We can thus size to ensure that sufcient a few times above the value of is translated into the negative resistance generated by series resonator loop of the crystal. Lower capacitance allows us to achieve submilliamp current consumption. Although we consider the parallel array of unit capacitors (thermometer code) a better way of achieving low power with-

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(a) Fig. 6. Thermometer-coded trimming capacitor bank.

(b)

out compromising monotonicity, we have implemented both the binary-coded array and the thermometer coded array for the trimming network, to evaluate the trade-off between power consumption and silicon area. For both implementations, the switches will be controlled by digital codes from the controller which compares the oscillator frequency with the reference derived from the RF signal in the pager system, if on-the-y tuning is performed. In the binary design, the W/L ratio of the MSB switch is nearly 4000, resulting in 4 pF drain bulk capacitance. For the less signicant bits the gate widths of the switch transistors are progressively lower by a factor of two. This is because the scaling factor in (8) makes the contribution of LSB switches to the total resonator loss much less signicant. The equivalent and due to the control switches resistance in series with is of the order of 4 , which is slightly less than the crystals motional resistance. Although the minimum capacitance of the tuning capacitor array is as small as 31 fF, the total capacitance of each array is still as high as 31 pF. When the entire array reaches a maximum of 37 pF, of which is switched in, and roughly 2 pF 4 pF is the gate-source capacitance of on comes from the pad and associated wiring. Capacitor the other hand, reaches a maximum of 39 pF, which includes of and the stray capacitances the pad capacitance, associated with the biasing transistor. The maximum load is of the order of 20 capacitance for the crystal, including pF. Reducing the area of the array further is difcult, because the resulting increased matching error will compromise the monotonicity to the extent unacceptable to the pager system designer. Even at its present size, capacitance errors in the rst three most signicant bits can be larger than what is required by the 0.20.3 ppm trimming accuracy. Additional 2- and 3-bit trimming capacitor arrays have been implemented to trim the MSB capacitors to the required accuracy during production and when both testing. The minimum capacitance of tuning arrays are turned off, are 13 and 15 pF, respectively, which are sufciently high to ensure oscillation. The strays

associated with the switches in the off-state and the bottom plates of the array capacitors, which have no effect when the switches are on, are taken into consideration here. The main array in the thermometer coded design contains only 224 unit capacitors, which gives us a resolution of slightly less than 8 bits. An additional three-bit ne tuning is realized by seven additional capacitors whose values range from 1/8 to 7/8 of the unit capacitance of the main array. Because these ne tuning capacitors only realize the three least signicant bits of tuning, the tolerance of their values has a limited effect on the overall monotonicity. Each unit capacitance is 69 fF when the switch is on, which includes all parasitics. When the switch is off, the remaining parasitics still contribute 15.8 fF to the xed part of or The variable capacitance contributed by each unit capacitor is therefore 43 fF and the total variable capacitance is about 10 pF, half the case of the binary design. Although the thermometer-coded array has only half the total capacitance, it incurs considerable overhead in terms of switches and decoding logic. The overall area for the trimming array is therefore 60% higher than the binary case. This is the price paid for reduced current consumption. Although there are more switches in the thermometer-coded array, each switch can be made small. The contribution of its on-resistance to the resonator loss is scaled by the square of the ratio of the small unit capacitance to the overall capacitance in each case. With a W/L ratio of ten, each switch transistor contributes 0.01 resistance to the resonator, and the contribution of each array is 2.3 . V. IMPLEMENTATION
OF

PIERCE OSCILLATORS

Among the three possible ways of biasing the three point oscillator, the Pierce oscillator shown in Fig. 7. has the advantage that capacitors and are grounded. The stray capacitances associated with the switches and the bottom plates of the tuning array, which are connected to the substrate and therefore to ac ground, do not come in parallel with . The pad and

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Fig. 7. Schematic diagram of the Pierce oscillator with tuning capacitor banks.

(a)

PCB wiring capacitances associated with the crystal nodes and and not This, as explained are also part of earlier, ensures higher frequency stability and lower power consumption. Connecting the source of the switch transistors to ground also maximizes the gate overdrive in addition to shorting the source-bulk capacitance. We have therefore selected the Pierce oscillator for our low power oscillator implementation. The characteristics of the 78MHz fundamental mode crystal which we use are: and the parallel capacitance pF. Given these characteristics and the loss due to control switches, the sizing of is an iterative process, because the parasitic capacitances of feed in the expressions for and which in turn modies the required transconductance For the binarycoded design s transconductance is of the order of 12 mA/V, which gives a ratio of around 17. The is just above the knee point on Fig. 3. This resulting allows us to reach 96% of the theoretical maximum amplitude without being excessively wide. To minimize systematic mismatch of the tuning capacitor array due to parasitics and oxide thickness gradient, the binary weighted capacitor banks are carefully laid out in common centroid structures. Each capacitor-switch combination in the array consists of identical unit capacitorunit switch cells. Fig. 8(a) shows the photomicrograph of the binary-coded oscillator chip, where the capacitor banks dominate the silicon area. The total chip size is 1.1 0.9 mm without the pad frame, in a 1 m-CMOS technology specied by our customer. For the thermometer-coded design, both the bias current and s width are smaller due to smaller parallel capacitors. Like a RAM, the capacitor array is organized as 7 rows and 32 columns. Unlike a RAM, many elements in the capacitor array must be selected simultaneously. To accomplish this without individual wires going to each element, the logic is split between the decoding logic in the column and row decoders, and four transistors at each switch site, as shown in Fig. 6. Those four transistors implement the following passtransistor logic, SW AR CR COL CR The AR, Active Rows, select the complete rows of capacitors that have

(b) Fig. 8. Photomicrograph of oscillator: (a) with binary weighted capacitor bank and (b) with thermometer coded capacitor bank.

already been switched in. The current row (CR) is a moving cursor which selects the present row of capacitors to be added or one by one. Which ones should be switched in to are then determined by the column decoder. Distributing logic to the cell site reduces the amount of wiring, but increases the size of each cell. The nal tradeoff results in a total silicon area, shown in Fig. 8(b), 60% higher than the binary implementation. The smaller capacitors, however, enable the thermometer coded design to consume only 1/3 of the current. Because the oscillation amplitude is only a weak function of the transistor gm, the choice of technology, whether it is bipolar or CMOS, and in the latter case if the feature size is 1 or 0.25 m, does not make too much difference as far as the oscillator proper is concerned. Finer feature size such as 0.5 or 0.25 m will reduce the parasitic capacitance and loss resistance in the trimming capacitor banks somewhat, but this is not very signicant for two reasons. The rst is that parasitic capacitances per unit area will increase due to thinner gate oxide and increased doping concentration, which offsets some of the reduction due to reduced switch size. The second is that mobility degradation due to normal eld becomes much

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SUMMARY

OF

TABLE I OSCILLATOR DESIGN PARAMETERS

AND

MEASURED PERFORMANCE

more serious in a deep submicron CMOS, which limits switch area and on resistance reduction. Some further details on the general subject of submicron CMOS scaling can be found in [6]. The transistor dimensions of both the binary and thermometer coded designs are summarized in Table I.

VI. EXPERIMENTAL RESULTS To minimize parasitic capacitance, both the crystal and the oscillator chip for each design have been directly bonded onto a PCB where 10 dip switches are used to control the tuning capacitor array switches. For the binary design, the oscillator works both when the tuning arrays are completely switched off and when they are completely switched on, for a voltage supply as low as 1.7 V. The total tuning range is 126 ppm, which is much better than our worst case estimate of 70 ppm. Four frequency points, corresponding to two below and two above each major carry of the digital control code, are measured to examine the worst case resolution and the monotonicity of the frequency tuning scheme. As the three frequency steps between the four points are monotonic for each major carry, we conclude that the entire frequency tuning curve is monotonic. As for the trimming accuracy, the highest frequency step for the rst seven set of frequency steps (from the LSB to the seventh MSB) is that corresponding to the LSB code. This is 22.7 Hz which corresponds to 0.29 ppm of 78 MHz. Fig. 9 shows the approximate tuning curve based on the available 40 measurement points. For a relatively constant amplitude of 450 mV The required current consumption depends on how much of the capacitor bank has been switched in. Table I shows the measured current consumption for the minimum, nominal and maximum tuning capacitance. The best and worst case current consumptions are 104 and 606 A, respectively, whereas the typical current consumption, which corresponds to the average crystal, is 239 A at 78 MHz.

Fig. 9. Measured tuning curve of oscillator with binary weighted capacitor bank.

The oscillation amplitude is around 500 mV which is within 10% of that predicted by (5) based on designed switch resistance and capacitances, and the measured 6 crystal motional resistance. For the thermometer coded design, the minimum supply voltage for which the circuit works is 1.9 V. The total tuning range is 128 ppm. The maximum tuning step is 0.2 ppm. As the tuning method is inherently monotonic, we have not performed exhaustive measurements to test every transition, which would require several hundred points. Transition points are tested randomly, however, and monotonicity is observed everywhere tested. The 8 LSB steps by the sub-array have been tested exhaustively. The result is plotted in Fig. 10. The current consumption is 57, 104, and 197 A for the minimum, nominal and maximum capacitances, respectively. Again, the amplitude-current relationship is within 10% of that predicted by (5). In addition to the 78 MHz oscillator, we have also been asked to test if the same circuit will also work for a 105-

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TABLE II CRYSTAL CHARACTERISTICS

Fig. 10. Measured tuning curve versus 8 LSB steps for oscillator with thermometer coded capacitor bank.

Fig. 11.

Phase noise measurement setup.

MHz, thermometer-coded crystal oscillators are set to different tuning codes so that their oscillation frequencies differ by about 10 kHz. Their outputs are mixed down using the set up shown in Fig. 11. An integrated 50 output buffer, shown in Fig. 7, amplies the oscillator output so that 0 dBm power is available to drive the diode mixer. After the lowpass lter, the oscillator spectrum is translated to 10 kHz. This is shown in Fig. 12. The measured phase noise is the sum of both oscillators. At 300 Hz frequency offset, the phase noise is extrapolated to be 110 dBc/Hz. Each individual oscillators phase noise is 3dB better, 113 dBc/Hz. Such an extremely low noise ensures that even after multiplication to 470 MHz, the phase noise is about 97 dBc/Hz at 300 Hz offset, which meets known specications by a very comfortable margin. Standard alone commercial oscillators typically use overtone crystals at this frequency range. This results in better phase noise ( 130 dBc at 300 Hz) but less tuning range ( 20 ppm, with varicap) and higher power consumption (10 mA @ 12 V) [7]. The important design parameters and measurement results of both oscillator implementations and both crystals are summarized in Table II. VII. CONCLUSIONS Low power design of high-frequency CMOS crystal oscillators has been described using precise formulas relating oscillation amplitude to current consumption. Crystal oscillators at 78 and 105 MHz, which are intended for pager receivers, have been used to illustrate the tradeoff between power and performance. A ne frequency accuracy requirement in the sub ppm range combined with a wide tuning range of at least 70 ppm makes a 10-bit capacitor tuning array necessary. The load capacitance due to tuning capacitors, and the loss due to switch on-resistances have been kept as small as possible to save power. The maximum current consumption of the thermometer coded 78 MHz oscillator is less than 200 A and the minimum power supply is 1.7 V. REFERENCES
[1] Philips Semiconductors, UAA2082 Advanced Paging Receiver, Data sheet, Jan. 1996. [2] E. Vittoz, M. Degrauwe, and S. Bitz, High performance crystal oscillator circuits: Theory and application, IEEE J. Solid-State Circuits, vol. 23, pp. 774783, June 1988. [3] D. Lanfranchi, E. Dijkstra, and D. Aebischer, A P-based analog wristwatch chip with 3 seconds/year accuracy, in Proc. ISSCC Tech. Dig. Papers, San Francisco, CA, Feb. 1994, pp. 9293. [4] E. Vittoz, Micropower Techniques, in Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, J. Franca and Y. Tsividis, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1994, pp. 8790.

Fig. 12.

Measured phase noise versus frequency offset.

MHz fundamental crystal, whose characteristics are fF and pF For the binary design, the total tuning range is about 80 ppm. The current consumption is 715 A in the nominal case for 417 mV amplitude. For the maximum capacitance case, 1.85 mA is required for 323 mV amplitude. The worst case power supply is 1.9 V. For the thermometer-coded design, the total tuning range is 84 ppm. The current consumption for minimum capacitance is 200 A whereas that for maximum capacitance is 714 A. In both cases the amplitude is about 400 mV One of the reasons for the crystal oscillator based LO frequency generation is the low phase noise characteristic of crystal oscillators, which can be below 100 dBc/Hz at a few hundred hertz. To measure such phase noise, two 78

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[5] Q. Huang, Exact calculation of oscillation amplitude and predicting power consumption for CMOS Colpitts oscillators, presented at IEEE ISCAS, Hong Kong, June 1997. [6] F. Piazza, P. Orsatti, Q. Huang, and H. Miyakawa, A 2 mA/3V 71 MHz IF amplier in 0.4 m CMOS programmable over 80 dB range, in Tech. Dig. Papers, pp. 7879; see also in Proc. Slide Supplement, IEEE Int. Solid-State Circuit Conf., San Francisco, CA, Feb. 1997, pp. 5657. [7] Data sheet, TCO-205 (100 MHz), TOYOCOM, Japan.

Philipp Basedau (S95) was born in Zurich, Switzerland, in 1960. He received the M.S. degree in electrical engineering from Swiss Federal Institute of Technology, Zurich, Switzerland, in 1985. He is currently a Research Assistant working toward the Ph.D. degree at the Integrated Systems Laboratory, Swiss Federal Institute of Technology. From 1985 to 1992, he was with the Department of Wire-Bound Transmission, Siemens-Schweiz, Zurich. His research interests include mixed signal integrated circuit design for telecommunications and CMOS-oscillator design in particular.

Qiuting Huang (S86M88SM93) graduated from the Department of Precision Instruments, Harbin Institute of Technology in 1982. He received the Ph.D. degree from Katholieke Universiteit Leuven, Departement Elektrotechniek, ESAT Laboratories, Heverlee, Belgium, in 1987. Between 1987 and 1992, he was a Lecturer at the University of East Anglia, Norwich, UK. Since January 1993, he has been an Assistant Professor at the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland. His general eld of research is in analog and mixed analog-digital integrated circuits and systems. His current research projects include RF front-end for wireless communications, interface circuits to sensors and actuators and low noise/low power ICs for biomedical applications.