i

DECLARATION

We hereby declare that this submission is our own work and that, to the best of our knowledge and belief, it contains no material previously published or written by another person nor material which to a substantial extent has been accepted for the award of any other degree or diploma of the university or other institute of higher learning, except where due acknowledgement has been made in the text.

Signature:

Signature:

Aakansha Yadav
Roll No. : 0906331002 Date:

Manu Shukla
Roll No.: 0906331047 Date:

Signature:

Signature:

Abhijeet Tiwari
Roll No.: 0906331003 Date:

Prateek Shukla
Roll No.:0906331067 Date:

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CERTIFICATE
This is to certify that the project entitled Design and simulation of combinational MTCMOS circuit using previously proposed leakage current and ground bounce noise reduction technique. which is submitted by Aakansha Yadav, Abhijeet Tiwari, Manu Shukla and Prateek Shukla in partial fulfillment of the requirement for the award of degree of Bachelor of Technology to Department of Electronics and Communication of GautamBuddh Technical University, is a record of the candidates own work carried out by them under my supervision.

Date: Mr.Anjan Kumar Assistant Professor

Department of Electronics and Communication Engineering

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ACKNOWLEDGEMENT

It gives us a great sense of pleasure to present the report of the B.Tech Project undertaken during B.Tech Final Year. We owe special debt of gratitude to our project guide Mr.Anjan Kumar, Department of Electronics and Communication, G.L.A.I.T.M., Mathura for his constant support and guidance throughout the course of our work. His sincerity, thoroughness and perseverance have been a constant source of inspiration for us. It is only his cognizant efforts that our endeavors have seen light of the day.

We also take the opportunity to acknowledge the contribution of Prof. T.N. Sharma, Head, Department of Electronics & Communication Engineering, G.L.A.I.T.M, Mathura and Mr. Abhay Chaturvedi, Program Coordinator, Department of Electronics and Communication, G.L.A.I.T.M., Mathura for his full support and assistance during the development of the project. We also do not like to miss the opportunity to acknowledge the contribution of all faculty members of the department for their kind assistance and cooperation during the development of our project. Last but not the least, we acknowledge our friends for their contribution in the completion of the project.

Aakansha Yadav (0906331002)

Manu Shukla (0906331047)

Abhijeet Tiwari (0906331003)

Prateek Shukla (0906331067)

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ABSTRACT

The exponential increase in leakage power due to technology scaling has made power gating an attractive design choice for low power applications. Power gating technique reduces leakage current of digital circuits during sleep mode. However, conventional power gating technique for minimizing leakage current introduces ground bounce noise during sleep to active mode transition and this ground bounce noise greatly affects the reliability of the circuits. In this project we will optimize leakage power & ground bounce noise. Key words: MTCMOS, Noise Margin, Ground Bounce Noise, Leakage current, Subthreshold leakage

TABLE OF CONTENTS
DECLARATION CERTIFICATE ACKNOWLEDGEMENTS ABSTRACT LIST OF FIGURES LIST OF TABLES NOMENCLATURE CHAPTER 1: INTRODUCTION 1.1 General Introduction 1.2 MTCMOS Technology 1.3 Leakage Current 1.4 Subthreshold Leakage 1.5 Noise Margin 1.5.1 Formulaes 1.6 Ground Bounce Noise 1.6.1 Ground Bounce Mechanism 1.7 Motivation CHAPTER 2: Literature Review 2.1 Literature Review 2.2 Leakage & Ground Bounce Reduction Techniques 2.2.1 Tri Mode Power Gating Technique 2.2.2 Dual Switch Power Gating Technique 2.2.3 Tri Transistor Technique i ii iii iv viii x xi 1-9 1 1 3 4 6 6 7 7 9 10-14 10 11 11 12 13

vi 2.3 Research Gap 2.4 Objective 2.5 Methodology 2.6 Software used 14 14 14 14

CHAPTER 3: Combinational Circuit 3.1 1-Bit Full Adder 3.1.1 Introduction 3.1.2 Full Adder Circuit CHAPTER 4: Simulation & Results 4.1 Simulation Setup

15-19 15 15 17 19-35 19

4.2 Leakage Current 4.3 Leakage Current Analysis for Conventional 4.3.1 Leakage Current with voltage 4.4 Leakage Current for Tri Mode 4.4.1 For W = 0.12um 4.4.2 For W = 5um 4.4.3 For W = 15um 4.5 leakage Current for Dual Switch 4.5.1 For W = 0.12um 4.5.2 For W = 5um 4.5.3 For W = 15um 4.6 Leakage for Tri Transistor 4.6.1 For W = 0.12um 4.6.2 For W = 5um 4.6.3 For W = 15um

19 20 20 21 21 22 22 23 23 24 24 25 25 26 26

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4.7 Comparisons 4.7.1 Leakage Current Comparison for W=.12um in Deep Sleep mode 4.7.2 Leakage Current Comparison for W=.12um in Intermediate mode 4.7.1 Leakage Current Comparison for W=5um in Deep Sleep mode 4.7.2 Leakage Current Comparison for W=5um in intermediate mode

27

27

27

28

28

4.8 Ground Bounce Noise Calculations 4.8.1 For conventional Circuit 4.8.2 For Tri Mode circuit 4.8.3 For Dual Switch circuit 4.8.4 For Tri Transistor 4.9 Ground Bounce Comparison 4.9.1 For W=0.12um 4.9.2 For W=5um 4.9.3 For W=15um

29 29 30 31 32 33 33 34 35

CHAPTER 5: Conclusion & Future Scope 5.1conclusion 5.2 Future Scope

36 36 36

REFERENCES

37

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LIST OF FIGURES

Figure No.
Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4

Figure Description
General Structure of a MTCMOS Leakage Current Mechanism3 Subthreshold leakage Subthreshold Leakage in a negative channel MOS transistor 5 6 7 11 12 13 16 18 20 21 23 25 2 3 4

Page No.

Figure 1.5 Figure 1.6 Figure 2.1 Figure 2.2 Figure 2.3 Figure 3.1 Figure 3.2 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4

Noise Margin Ground Bounce Mechanism Tri Mode Power Gating Structure Dual Switch power gating structure Tri Transistor Power gating technique Conventional CMOS full adder Full adder circuit with Sleep transistor Adder with Conventional Technique Adder with Tri Mode Technique Adder with Dual Switch Technique Adder with Tri Transistor Technique

ix Figure 4.5 Variation of leakage power with Voltage in deep sleep(.12um) 27

Figure 4.6

Variation of leakage power with voltage in intermediate (.12um) 27

Figure 4.7

Variation of leakage power with voltage in Deep Sleep mode(5um) 28

Figure 4.8

Variation of leakage power with voltage In inter mediate mode (5um) 28 29 29 30 30 31 31 32 32 33 34 35

Figure 4.9 Figure 4.10 Figure 4.11 Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Figure 4.16 Figure 4.17 Figure 4.18 Figure 4.19

Ground Bounce Noise in Conventional circuit Graph of Noise in Conventional circuit Ground Bounce Noise in Tri Mode Circuit Graph of Noise in Tri Mode Circuit Ground Bounce Noise in Dual Switch circuit Graph of noise in Dual switch Ground Bounce Noise in Tri Transistor circuit Graph of Noise in Tri Transistor Ground Bounce Noise Comparison for w=.12um Ground Bounce Noise Comparison for w=5um Ground Bounce Noise Comparison for w=15um

LIST OF TABLES

Table No.
Table 2.1 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 Table 4.6 Table 4.7 Table 4.8 Table 4.9 Table 4.10 Table 4.11 Table 4.12

Table Description
Research Gap Simulation Setup Conventional Circuit analysis Tri Mode analysis (.12um) Tri Mode analysis (5um) Tri Mode analysis (15um) Dual Switch analysis (.12um) Dual Switch analysis (5um) Dual Switch analysis (15um) Tri transistor analysis (.12um) Tri transistor analysis (5um) Tri transistor analysis (15um) Ground Bounce Comparison

Page No.
14 19 20 21 22 22 23 24 24 25 26 26 33

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List of Abbreviations

Abbreviation
MOS rev exp Vth Gnd I NMH NML VOH VOL L W VDD Dn LB r

Description
Metal Oxide Semiconductor Reverse exponential Threshold Voltage Ground Current Noise Margin for high Signal Level Noise Margin for Low Signal Level Output High Voltage Output Low Voltage Channel Length Channel Width Power Supply Voltage Channel Depth Length of Barrier Region Reference Potential