1 5.

What are the total stall cycles for the following code sequences with both the base protocol(MSI) and the new MESI protocol? Assume that states transitions that do not require interconnect transactions incur no additional stall cycles.

2 a) Instruction P0: read 100 MSI 100 Cache State I -> S MESI 100 Cache State I -> E Comment For both protocols read data from the memory MSI send invalidate signal at any case while MESI doesnt because data access is exclusive.

P0: write 100

15

S -> M

E -> M

Total

115

100

b) Instru ction MSI Cache State MESI Cache State C o m m e n t F o r b o t h p r o t o c o l s r e a d

P0: read 120

100

I -> S

100

I -> S

d a t a f r o m P 3 s c a c h e P0: write 120 15 S -> M 15 S -> M M S I s e n d i n v a l i d a t e s i g n a l a t

a n y c a s e w h i l e M E S I s e n d s i n v a l i d a t e s i g a n l b e c a u s

e P 3 h a s d a t a . Total c) Instru ction MSI Cache State MESI Cache State C o m m e n t F o r b o t h p r o t o c o l s r e a d 115 115

P0: read 100

100

I -> S

100

I -> E

d a t a f r o m t h e m e m o r y P0: read 120 100 I -> S 100 I -> S F o r b o t h p r o t o c o l s r e a d d a t a

f r o m t h e m e m o r y Total 200 200

Below we assume that if processor has a write miss it writes directly to the memory and other processors snoops data from the bus. That is from solution but we dont think that this is correct. d) Instru ction MSI Cache State MESI Cache State C o m m e n t F o r b o t h p r o t o c o

P0: read 100

100

I -> S

100

I -> E

l s r e a d d a t a f r o m t h e m e m o r y P1: write 100 100 p1: I >M p0: S >I 100 p1: I -> M p0: E -> I F o r b o t h p r o t o c o l s w r

i t e d a t a d i r e c t l y t o t h e m e m o r y . Total e) Instr uctio n P0: read 100 MSI Cach e State I -> S MESI Cache State Comment 200 200

100

100

I -> E

For both protocols read data from the memory MSI send invalidate signal at any

P0: write 100

15

S -> M

E -> M

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case while MESI doesnt because data access is exclusive. P1: write 100 10+100 p1: I >M p0: M -> I 10+100 p1: I -> M p0: M -> I P0 write back and P1 writes directly to the memory

Total 225

210

Here we assume the on write miss we load the data first and then modify it in the cache. We thinks that this is correct according to write-back protocol (see picture below) d) Instru ction MSI Cache State MESI Cache State C o m m e n t F o r b o t h p r o t o c o l s r e a d d

P0: read 100

100

I -> S

100

I -> E

11

a t a f r o m t h e m e m o r y P1: write 100 100+15 p1: I >M p0: S >I 100+15 p1: I -> M p0: E -> I F o r b o t h p r o t o c o l s r e a d d a t a f

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r o m t h e m e m o r y . A n d t h e n s e n d i n v a l i d a t e s i g n a l . Total 215 215

13 e) Instr uctio n P0: read 100 MSI Cach e State I -> S MESI Cache State Comment

100

100

I -> E

For both protocols read data from the memory MSI send invalidate signal at any case while MESI doesnt because data access is exclusive. P0 write back and P1 reads data from P0 modifies the data and sends invalidate signal to P0.

P0: write 100

15

S -> M

E -> M

P1: write 100

40+10+15

p1: I >M p0: M -> I

40+10+15

p1: I -> M p0: M -> I

Total 175

165

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