PCB Design: Dr. Daryl Beetner Missouri S&T Electromagnetic Compatibility Laboratory P y y

PCB Design
Dr. Daryl Beetner Missouri S&T Electromagnetic Compatibility p y Laboratory y

(Formerly the UMR EMC Laboratory)
IEEE EMC Symposium - Fundamentals July 26, 2010
MO-AM-1
Outline

Basics concepts PCB design guidelines - explained Power bus decoupling
D. Beetner Missouri S&T EMC Laboratory MO-AM-1
The Basic Concepts
D. Beetner
MO-AM-1
Elements of an EMC Problem
Source Coupling path

E.g.: - High-speed clock - High-speed High speed I/O - Switched inductive load - ESD - Etc. E.g.: - Copper trace (conducted) - Large heat sink (electric field) - Signal/return current loop (magnetic field) - Antenna structure (radiated)
Victim
E.g.: - Analog A/D converter - IC connected to I/O - External wireless device
Minimizing EMC issues in PCB design

Pay special attention to: Potential sources

Large di/dt or dv/dt (high frequency, fast rise-time) Connected to a g good antenna Sensitive to small changes in voltage/current Well coupled to a potential source Potential antennas Management of current return path
D. Beetner Missouri S&T EMC Laboratory MO-AM-1 5
Potential victims

Coupling mechanisms

Potential sources
Digital clock circuits High speed digital signals DC power planes
dd noise ss
Potential sources
Low-speed digital signals

Vdd Plus highfrequency noise!
Noise V Vss High-Speed Clock IC IC Low-Speed I/O
Vdd
Fast rise times => high freq. energy
Vss
Low-Speed I/O
D. Beetner Missouri S&T EMC Laboratory MO-AM-1 7
Potential sources
Low frequency digital signals with fast rise-times may include significant high-frequency energy
Potential sources
Power switching circuits
Potential victims
Analog signals

Audio A di Wireless RF
10
Potential source and victim
Anything run off board
11
Potential antennas
Dipole antenna
Monopole antenna
An efficient antenna requires two electrically large conductors d t that th t may be b driven di against i t one another th
Loop antennas are rarely problem
12
Potential antennas
13
Potential antennas
Good antenna parts <100 MHz
cables
Poor antenna parts <100 MHz >100 MHz

Anything not big Microstrip or stripline traces
>100 MHz
Heatsinks Power planes T ll components Tall t Seams in enclosures
14
Potential coupling mechanisms
Systems are generally electrically small, so coupling must occur through: Conductive coupling Capacitive coupling Inductive coupling
15
Possible coupling mechanisms
Conducted coupling
Vdd
Vss
Vdd
Noise Vss
16
Voltage driven (capacitive / electric field coupling)
Vdd Low-Speed I/O High-Speed Clock IC IC
Vss
17
Current driven (mutual inductance / magnetic field coupling)
Vdd Low-Speed I/O High-Speed Clock IC IC
Vss
Large di/dt
IC
Inductive coupling to board

IEEE EMC Symposium - Fundamentals July 26, 2010 D. Beetner Missouri S&T EMC Laboratory MO-AM-1 18
Current return paths should be well controlled
Current always returns to its source, primarily through the path of least impedance A low-impedance return path

Minimizes signal- and power- integrity issues Mi i i Minimizes the h potential i l for f crosstalk, lk by b maximizing i i i the h current that returns through the intended return path
At high frequencies (>100 kHz) kHz), current typically returns through the path of least inductance
Low impedance p = low inductance = small loop p area
Control current return paths by minimizing signal/return i l/ t loop l areas

Current always returns to its source
20
Return current beneath a PCB trace

High Frequency
High frequency current tends to concentrate beneath the trace trace, so is well controlled
21
What is the high-frequency current return path?
A low-impedance p return path p helps p control the return current

What is the high-frequency current return path?

Vdd Out
Vss In
Vss
A high-impedance return path can cause signal integrity issues or cause the signal to return by an alternate path
Avoid gaps in the return plane
Crossing g the g gap p may y cause ringing, g g increased emissions, and increased susceptibility.
Increased susceptibility and emissions
Increased mutual inductance at g gap p increases susceptibility and emissions.

Increased emissions
Flux wraps small planes more easily than large planes, increasing associated inductance. The inductive voltage drop caused by the gap can drive unintentional antennas
26
Some Design Guidelines Explained
D. Beetner
MO-AM-1
Can I just follow a list of guidelines?
Guidelines are helpful BUT:
Guidelines are often developed for specific scenarios that may not t apply l to t your design d i It is often difficult to follow ALL the guidelines ALL the time.
The basis for any guideline should be understood so it can be applied intelligently
Guidelines are useful advice not rules.
28
PCB EMC Guidelines

Minimize the loop area of all high-speed signals
1 MHz Clock Driver
Vdd O t Out
Vss
IC
In
Vss
NO RETURN PLANE
A high inductance return path may cause signal i integrity i issues i A high impedance return path may cause signals to return where you don dont t want them to. to
PCB EMC Guidelines

Minimize the loop area of all high-speed signals Rules with similar basis: Locate components to minimize the length of highspeed traces On a board with power and return planes planes, connections to the planes should be made directly with vias no traces Critical signal traces should be buried between power/ground planes
PCB EMC Guidelines

Minimize the loop area of all high-speed signals Rules with similar basis: On boards with multiple return planes, planes all return planes should be well connected with vias.
31
PCB EMC Guidelines

Dont locate circuitry between connectors
Circuitry between connectors can drive a noise voltage between connected cables
32
PCB EMC Guidelines

Dont locate circuitry between connectors Rules with similar basis: Locate connectors on one edge or one corner of the board All off off-board board communications from a single device should be routed through the same connector
33
PCB EMC Guidelines

Control signal transition times
Low rise/fall times minimize high-frequency g q y energy gy

PCB EMC Guidelines

Control signal transition times Rules with similar basis: Use logic families that are no faster than necessary Filter digital signals to use the longest reasonable rise time
35
PCB EMC Guidelines

Provide a solid return plane with no gaps
Gaps can: Increase I return t path th impedance i d Increase potential for crosstalk Increase potential to drive noise voltage across return plane
PCB EMC Guidelines

Provide a solid return plane with no gaps Rules with similar basis: All power planes and all traces should be routed on the same layer No MHz signals should be allowed to cross a gap in the return plane
37
PCB EMC Guidelines

A device that communicates off board should be located as closely as possible to the connector it uses
Vdd
Vss
High-Speed Clock IC IC
Low-Speed I/O
Minimizes the potential for unwanted noise to couple to the connector

PCB EMC Guidelines

A device that communicates off board should be located as closely as possible to the connector it uses Rules with similar basis: Keep K MH MHz circuits i it away from f connectors t attached tt h d to t external cables unless these signals must pass through the connectors Provide space for filters at I/O connectors No trace unrelated to I/O should be located between a device using I/O and the connector Signals g with high-frequency g q y content should not be routed beneath components used for board I/O
PCB EMC Guidelines

Avoid electrically floating metal
Floating metal can increase capacitive coupling between circuits or can be driven to radiate
40
PCB EMC Guidelines

Avoid electrically floating metal Rules with similar basis: Connect all metal fill area to return plane Connect return planes with multiple vias When possible, connect heat sinks to return planes
41
PCB EMC Guidelines

Place and route highest-frequency components and signals first, working toward lower-frequency components
Maximizes the potential to provide a good return path and to minimize crosstalk
42
Power Bus Decoupling
MO-AM-1
Power bus decoupling
The intent of power bus decoupling is to connect the power and return planes with zero impedance at high f frequencies i Inductance makes this increasing difficult with frequency
44
Capacitors
At high hi h f frequencies, i parasitic iti i inductance d t will ill dominate capacitance PCB should be designed to minimize this inductance
Boards with no power/return planes

On boards without power/return planes, local decoupling capacitors should be mounted to minimize power/return loop area
46
Widely spaced planes (>0.5 mm)

For widely spaced planes, the IC/decoupling capacitor vias to the farthest planes should be placed as close t th as possible together ibl
IC Capacitor IC Vdd Vss Vdd Vss Capacitor IC Capacitor IC
Vdd Vss Capacitor

Vdd Vss
Closely spaced planes (<0.3 mm)

For closely spaced planes, local decoupling capacitors should be placed reasonably close to the part. L ti is Location i not t critical. iti l
48
Capacitor connection
Capacitors should be connected to planes with minimum loop area
49
Thank you. Q Questions?
50
Acknowledgements
Special thanks to Todd Hubing and Tom Van Doren, whose class notes provided significant inspiration for th these slides. lid
51

PCB Design: Dr. Daryl Beetner Missouri S&T Electromagnetic Compatibility Laboratory P y y

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PCB Design: Dr. Daryl Beetner Missouri S&T Electromagnetic Compatibility Laboratory P y y

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PCB Design

Dr. Daryl Beetner Missouri S&T Electromagnetic Compatibility p y Laboratory y

IEEE EMC Symposium - Fundamentals July 26, 2010

Basics concepts PCB design guidelines - explained Power bus decoupling

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

The Basic Concepts

Elements of an EMC Problem

Source Coupling path

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Minimizing EMC issues in PCB design

IEEE EMC Symposium - Fundamentals July 26, 2010

Digital clock circuits High speed digital signals DC power planes

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Low-speed digital signals

Noise V Vss High-Speed Clock IC IC Low-Speed I/O

Fast rise times => high freq. energy

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Power switching circuits

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Potential source and victim

Anything run off board

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Loop antennas are rarely problem

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Poor antenna parts <100 MHz >100 MHz

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Potential coupling mechanisms

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Possible coupling mechanisms

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Possible coupling mechanisms

Voltage driven (capacitive / electric field coupling)

Vdd Low-Speed I/O High-Speed Clock IC IC

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Possible coupling mechanisms

Current driven (mutual inductance / magnetic field coupling)

Vdd Low-Speed I/O High-Speed Clock IC IC

Inductive coupling to board

Current return paths should be well controlled

Low impedance p = low inductance = small loop p area

Control current return paths by minimizing signal/return i l/ t loop l areas

Current always returns to its source

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1

Return current beneath a PCB trace

IEEE EMC Symposium - Fundamentals July 26, 2010

D. Beetner Missouri S&T EMC Laboratory MO-AM-1