Cadence Virtuoso : Analog Design & Simulation Procedure:

Procedure for Schematic Design, Simulation in the Analog Environment (Cadence Virtuoso). ## In Linux Environment Open Terminal ## On the command prompt window [root@simcomp-30~]$ csh [root@simcomp-30~]$ source cshrc The following execution of the script changes environment for Verilog, provided by cadence. WELCOME TO CADENCE TOOLS SUITE cd Database/cadence_analog_labs icfb & ----------------------------------------------------------------------------------------------------------## This opens icfb Log:/root/CDS.log window Creating a New library ## We will now create a new library, which will contain the cells we design. In the library Manager File New Library The New library form appears, type library name say LOW_POWER Click Apply In the Technology file for library, Select attach to an existing tech file

Click OK

Close ----------------------------------------------------------------------------------------------------------Creating a Schematic CellView ## We will now create a new Schematic file and implement our design. In the library Manager

File New Cellview Select the Library name LOW POWER Cell Name inverter

View Name Schematic Tool Composer-Schematic Click OK ---------------------------------------------------------------------------------------------------------Adding Components to Schematic To add the components click on Menu Add Instance or (press i) Click on browse button, this opens the library browser, Select gpdk180 nmos symbol and place the symbol in the schematic window. Select gpdk180 pmos symbol and place the symbol in the schematic window and press escape. Make the interconnections by selecting wire (narrow) and complete the connection. To inset the input & output pins, select Pin / Press P & give the pin names and specifies i/p & o/p pin.

Pin Name Vin Vout Vdd Vss

Direction Input Output input output input output

Press r to rotate to place the pins Check and Save ---------------------------------------------------------------------------------------------------------Creating the Symbol of Schematic In the schematic design window Click on Design Create Cell View From Cell View This opens cell view form, check the following

Library name: LOW POWER Cell name: inverter From View name: Schematic

To View name: Symbol Tool/Data type: Composer-Symbol Click OK Modify the pin specifications Pin Specifications Left pins Right Pins Top pins Bottom pins Click OK After the symbol design is done Click on save and close the window. Vin Vout Vdd Vss

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Creating the TEST BENCH for the schematic designed In the Library Manger window Click on File New Cell View This opens cell view form, check the following Library name: LOW POWER Cell name: inverter_test View name: Schematic Tool: Composer-Schematic Click OK A new window opens up, where we can design out test bench for schematic. Now insert the symbol we have created, click on Add instance browse and select the library LOW POWER and click on inverter symbol. and place the symbol in the schematic window ans press escape. Now insert the Vdc for VDD, Vpulse and Gnd. Library name LOW POWER analogLib Cell View name inverter Vpulse Properties/Comments Symbol voltage1 = 0V, voltage2 = 1.8V, Delay time = 0

Rise time = 1ns, fall time = 1ns, Pulse width = 10ns, Period = 20ns analogLib analogLib Vdc Gnd DC voltage = 1.8V -

Click on wire (narrow) icon and finis the schematic as shown below Click on Check and save The schematic test bench will appear as seen below.

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Analog Simulation with spectre simulator In the inverter_test window Click on Tools Analog Environment This opens the analog environment simulation window, in the simulator window Setup Simulator/Directory/Host Select the Spectre simulator Click OK Setup Model libraries Click on the path /root/Database/cadence_analog_labs/models/spectre/gpdk.scs Add if nor present, if present already verify whether given path is correct or not Click Apply and OK Click on Analysis Choose Select transient analysis, tran Stop time as 5m Click on Enable Button Click on Moderate Button Click Apply OK

Click on Outputs To be plotted select on schematic Click on output terminal Vout and click on input terminal Vin Press Esc after selecting In the Analog Simulation window Click on Netlist and Run Click OK

This shows the simulated waveforms