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21*
22
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25*
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40
41

1
CK
APPD

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.


2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

REV

08/03/04

CIRCUIT

BLOCK

TABLE OF CONTENTS
SYSTEM BLOCK DIAGRAM
POWER BLOCK DIAGRAM
REVISION HISTORY
TABLE ITEMS
FUNC TEST
POWER CONNECTOR / POWER ALIAS
SIGNAL ALIAS
2.5V VREG
1.2V VREG
3.3V/5V PWRON SWITCHING
SMU
CPU LOGIC ANALYZER CONNECTOR
FAN 1, 2 AND SYSTEM TEMP SENSOR
FAN 3 AND HARD DRIVE TEMP SENSOR
I2C CONNECTIONS
INDICATOR LED
U3LITE CORE
SHASTA CORE
U3LITE MISC
SHASTA SERIAL
PULSAR POWER
PULSAR CLOCKS
U3LITE APPLE PI
NEO APPLE PI
CPU STRAPS
NEO POWER & BYPASS
CPU BYPASS
CPU VREG
CPU VREG
CPU VREG OUTPUT CAPS
CPU DIODE CONDITIONER
U3LITE MEMORY
SERIES TERMINATION
DIMMS
PARALLEL TERMINATION
PARALLEL TERMINATION
VTT VREG
U3LITE AGP
GPU AGP
GRAPHICS VREGS (GPU CORE & 1.5V)

TOP

PROCESSOR

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74

ECN

ENG
APPD

DESCRIPTION OF CHANGE
DATE

PAGE PDF
51
52
53
54
55
56
57
58
59
60
62*
64
73
74*
75*
76
77*
80*
83
84*
87
88*
90
91*
92
94
95*
96*
98*
100*
101*
102*
103*

ZONE

338723

PRODUCTION RELEASED

CIRCUIT

DATE

08/04/04 ?

BLOCK

EXTERNAL TMDS TRANSMITTER


GPU FRAME BUFFER
FRAME BUFFER TERMINATION
GRAPHICS DDR SDRAM A
GRAPHICS DDR SDRAM B
GPU STRAPS
GPU DAC & CLOCKS
GPU DVI & STRAPS
EXT VGA & TMDS
U3LITE HYPERTRANSPORT
SHASTA HYPERTRANSPORT
HYPERTRANSPORT LA CONNECTORS
PCI SERIES TERMINATION
SHASTA PCI
BOOT ROM
AIRPORT EXTREME
USB2 PCI
SHASTA DISK
DISK CONNECTORS
SHASTA ETHERNET
ETHERNET PHY & CONNECTORS
SHASTA FIREWIRE
FIREWIRE A PHY & CONNECTORS
USB HOST INTERFACE
USB DEVICE INTERFACE
MODEM CONNECTOR
PCM3052 AUDIO CODEC
LINE IN AMP
LINE OUT AMP
SPEAKER AMP
AUDIO CONNECTORS
AUDIO POWER SUPPLIES
S/PDIF TRANSMITTER

GRAPHICS

HT
C

PCI
DISK
ETHERNET
FIREWIRE
USB
B

MODEM

AUDIO

MEMORY
DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

METRIC

XX

X.XX
DRAFTER

GRAPHICS

NOTICE OF PROPRIETARY PROPERTY

DESIGN CK

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

X.XXX
ENG APPD

MFG APPD

QA APPD

DESIGNER

RELEASE

SCALE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ANGLES

TITLE

DO NOT SCALE DRAWING

* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC

SCH,MLB,IMG5
NONE
SIZE

THIRD ANGLE PROJECTION

MATERIAL/FINISH
NOTED AS
APPLICABLE

DRAWING NUMBER

REV.

051-6482
SHT

C
OF

103

FREQUENCIES LISTED ARE MAXIMUM DATA TRANSFER RATES SUPPORTED BY U3LITE

U2900

CPU
NEO 10S

U1300

PAGE 29
J5900, J5901
J5902, J5903

U1301

SMU

RTC

17",20" INVERTER

TMDS
EXT VGA

32-BIT
APPLE PI
ELASTIC INTERFACE
1.2V/900MHZ

PAGE 59

PAGE 13

PAGE 13

FRAME
BUFFER A

64-BIT
FRAME BUFFER
2.6V/540MHZ

PAGE 28
U3

GPU

AGP

32-BIT
8X AGP
0.8V/533MHZ

NV18B/NV34

PAGE 54

U3LITE

PAGE
48

CORE

4X = 1.5V
I/O = 1.5V

64-BIT
FRAME BUFFER
2.6V/540MHZ

POWER

CLOCKS

FRAME
BUFFER B

PAGE 26

PAGE 27

PAGE 55

DIMMS

SERIES

PARALLEL

TERM

TERM
PAGES 44&45

PAGE 38

PAGE 40

MISC

HYPERTRANSPORT

PAGE 24

PAGE 60

J9210/J9220/J9230

USB
CONNECTORS
PAGE 92

8-BIT
HYPERTRANSPORT
1.2V/400MHZ

J9400

MICRODASH MODEM

CONTROL = 2.5V

U5500, U5501

PULSAR

64/128-BIT
MAIN MEMORY
2.6V/400MHZ

PAGE 22

PAGE 49

U2600

MAIN MEMORY

APPLE PI
U4900

U5400, U5401

PAGE 37

J4000
J4001

CONNECTOR
PAGE 94

I2C

J9240

J6400
J6401
J6402

PAGE 18

HT
DEBUG

AIRPORT
EXTREME
CONNECTOR

PAGE 75

SHASTA

1.2V/1.5GHZ
PAGE 83

EDUCATION: HARD DRIVE


GOOD,BETTER,BEST: OPTICAL

UATA
CONNECTOR

UATA/133

UATA

PAGE 80

J8301

3.3V/133MHZ

NCs

CORE
PAGE 23

PAGE 84

PAGE 88

BCM5221

PAGE 87

4 Diff pairs
J8700

PCI
PAGE 77

J9401

PAGE 94

SCCB
I2S2

U9500

S/PDIF

AUDIO CODEC
LINE OUT
AMP

PAGE 95

FIREWIRE A
802A

PAGE 97

SPEAKER
AMP

LINE IN
AMP
2 Diff pairs

PAGE 90

PAGE 97

SYSTEM BLOCK DIAGRAM

SPEAKER
CONNECTOR

J9800

J9802

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

LINE IN

MIC

CONNECTOR

CONNECTOR

PAGE 98

PAGE 98

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6482

D
SCALE

NOTICE OF PROPRIETARY PROPERTY

PAGE 98

PAGE 97

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

J9000, J9001

PAGE 87

PAGE 98
LINE OUT

J9801

PAGE 90
0
1

FIREWIRE A
CONNECTORS

OPTICAL OUT
J9803

COMBO OUT
CONNECTOR

PCM3052

ETHERNET
CONNECTOR

CTL-LESS /
SOFT MODEM
CONNECTOR

U9000

10/100 ETHERNET

uPD720101

32-bit PCI (5V-3.3V/33MHz)

I2S
PAGE 25
SCCA
I2S0
I2S1

1394 OHCI (3.3V/98MHz)


8-bit TX/RX

GMII (3.3V/125MHz)
8-bit TX & 8-bit RX

U8700

USB 2.0

PAGE 76

PAGE 91

ETHERNET FIREWIRE

PAGE 83

PAGE 92

PAGE 25

GPIO/PCI64

SATA/150

BLUETOOTH
CONNECTOR

U2300

SATA2

SATA DEV
CONNECTOR

SATA

PAGE 80

J8302

PAGE 74

PAGE 62

PAGE 83

FOR DEVELOPMENT ONLY

PCI

HYPERTRANSPORT

SATA1

1.2V/1.5GHZ

U7700

J7600

JXXXX

SATA/150

PAGE 91
U7500

BOOTROM
SATA
CONNECTOR

USB

PAGE 64

EDUCATION: NOT USED


GOOD,BETTER,BEST: HARD DRIVE

To Shasta
SCCA

OF

C
103

1
SMU

SYS_POWERUP_L

POWER SEQUENCE PIN

PULSAR_POWER_DOWN
MAKE_BASE=TRUE
=PULSAR_POWER_DOWN
27

SYS_POWERUP_L

J700
PAGE 7

POWER CONNECTOR

PP24V_RUN

PP12V_RUN

FW CONN
20" LCD INVERTER

PP5V_RUN

20" PANEL POWER


20" LCD INVERTER

PP5V_ALL

13

10

TURN_ON_SHASTA_CORE_L

SMU_PWRSEQ_P1_0

13

10

TURN_ON_PP1V2_L

SMU_PWRSEQ_P1_1

13

SMU_PWRSEQ_P9_5

13

(PWR_GOOD_SB_CORE)

SMU_PWRSEQ_P9_6

13

(PWR_GOOD_PP2V5)

SMU_PWRSEQ_P1_2

13

(TURN_ON_VTT)

PP3V3_RUN

HDD & OPTICAL

SMU_PWRSEQ_P1_4

PCI BUS
AUDIO CODEC

5V

PP3V3_ALL

PP3V3_ALL
LINEAR

R331

PAGE 11

10K

FW PHY
SMU

3.3V

5%
1/16W
MF
2 402

PWR_GOOD_SB_CORE
=PP5V_RUN_CPU

PP5V_RUN_AUDIO
LINEAR

CPU CORE
SWITCHER

PAGE 99

5V

PAGE 33
HP/LINEOUT AMP

6 7 8 31

PP2V5_RUN_CPU_AVDD
ALIAS

CPU_AVDD_EN

LINEAR

PP5V_PWRON
FET SWITCH

PP3V3_PWRON
FET SWITCH

PAGE 11

PAGE 31

SC2643VX*1
SC1211*4

0.8~1.2V

31

CPU AVDD

2.8V

PAGE 11
USB CONN
UDASH MODEM

5V

GPUL

ENET PHY
USB2 HOST
MODEM & BT

3.3V

PP1V2_SHASTA_CORE

SWITCHER

GPU CORE
SWITCHER
PAGE 50

PAGE 10

IN

IRU3037ACS

1.2V

SHASTA CORE

IRU3037CS

1.6/1.4V

NV18B/NV34

3
11
10 6

PP4V5_RUN_AUDIO
LINEAR

U3LITE CORE
SWITCHER

PAGE 99

4.5V

IRU3037CS

PAGE 22

AUDIO CODEC

PP2V5_PWRON
SWITCHER

1.53V

PAGE 9

U3LITE CORE

2.62V

SHASTA HT
DDR DIMM

PP1V2_PWRON
FET SWITCH IN

PP2V5_PWRON

PP1V2_RUN
FET SWITCH

IN

1.5V

20%
16V
2 CERM
402

IN

PWRON_SD
PWRON_DISK_SB

HT BUS
API BUS

PP5V_ALL
PP3V3_ALL
1

R342

PULSAR CORE

R341
10K

R340

PAGE 50

PAGE 46

AGP BUS

RAM VTT

46

LM339A

SOI

V+
1

U1100

100K 2
5%
1/16W
MF
402

5%
1/16W
MF
2 402

PS_2V_REF

PP1V5_RUN
POWER SW

5%
1/16W
MF
2 402

1.25V

12

C330

150K

PP1V25_RAM_VTT
LINEAR
IN

14

GND

0.01UF

PAGE 50
RAM TERM
GRAPHIC FB

PAGE 10

PP1V5_PWRON
LINEAR

PAGE 9

SOI

U1100

100K 2 COMPARE_SB_CORE
1
5%
1/16W
MF
402

PAGE 10

PP2V5_RUN
FET SWITCH

R330

IN

IRU3037CS

LM339A

RAIL_CTL_NEG

V+

PPVCORE_PWRON_SB

COMPARE_PP2V5

PWR_GOOD_PP2V5

GND
12

C340

0.01UF

20%
16V
2 CERM
402

R343
100K

5%
1/16W
MF
2 402

TURN_ON_VTT

POWER BLOCK DIAGRAM

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

OF

C
103

8
DATE

EVT3 RELEASE (REV 20)

05/06/04

DVT RELEASE (REV 24)

03/05/04

GPU XTAL - C5700 AND C5719 -> 27PF FROM 22PF


I2C A - U1800 MOVED BACK TO PWRON RAIL
HEATSINK ASSEMBLY - NEW PART NUMBERS
FAN 3 - STUFFING ON ALL CONFIGS
FIREWIRE POWER DU JOUR
EVT3 - BOM REV 21 RELEASE

05/07/04

TMDS - NEW PARALLEL TERMINATION RESISTORS R5869-R5872


CHECKIN 24001

05/10/04

FRAME BUFFER CLOCKS - ADDED DIFF PAIR PROPERTIES


PCI_RESET - UPDATES FOR SCHEMATIC REUSE
MASTER PAGE SYNC - ADDED S/PDIF XMITTER AND BITCLK DELAY
CHECKIN 24002
AUDIO UPDATES
CHECKINS 24003-24005

03/24/04

MASTER PAGE SYNC


EVT3 REWORKS
NOSTUFF R807 - SMU_BOOT_SCLK IS ALSO CPU_VID<5>
NOSTUFF R3691 & R828 - DIODE CAL RETURN PATH
MOVED MARTY SERIAL 0 OHM RESISTORS TO COMMON BOM
SMU - ADDED QREQ
GPU - ADDED DECOUPLING TO GPU_VTT FOR NV36
INVERTER CONTROL - ADDED AND GATES U5850 & U5851 TO CONTROL LCD_PWM AND FPD_PWR_ON
CHECKIN 21001

04/12/04

CPU - CHANGED CPU SYMBOL TO NEO-10S-REV2-76C (OLD IS OBSOLETE)


SCHEMATIC REUSE - NETS THAT NEED ALIASES START WITH = (DOES NOT EFFECT NETLIST)
3PHASE CPU POWER SUPPLY - ADDED TABLE FOR R3328
INVERTER - ADDED RESISTORS R5860-1 AND CHANGED R5808-9 TO 47OHM
TMDS POWER - ADDED R5960 AND D5914
DIODE CAL - ADDED OPTION TO POWER FROM PP5V_ALL AND PP3V3_ALL RAILS
CHECKIN 21002

04/12/04

MASTER PAGE SYNC - IN SYNC ON ALL PAGES EXCEPT PAGE 13


EMI - REMOVED EMI700 & EMI9400
QREQ_L HACK - ADDED U2850, C2850, R2850, R2851
VOLTAGE SENSE FROM 12V - ADDED R3360, R3361
CHECKIN 21003

04/21/04

MAIN MEMORY DQS PARALLEL TERM - CHANGED TO 100 OHM (LIKE EVT3)
I/O ALIGNMENT FIXTURE - ADDED 815-8008 TO MLB BOM
DIMM CONNECTORS - UPDATED 30 DEGREE SYMBOL
GREEN LED - ADDED KINGBRIGHT AS ALTERNATE
VTT - NO LONGER POWER SEQUENCED - NO STUFFED R4610 AND R4603
HD TEMP SENSOR - STUFFED ON ALL CONFIGS
SMU PULLUPS CHANGES - R1312 -> 2K; R1311 -> 10K
SDF804 -> ZH804
CHECKIN 21004

MASTER PAGE SYNC - NOW IN SYNC ON ALL SHAREABLE PAGES


MAIN MEMORY - DQ SERIES TERM CHANGED TO 22 OHM
MAIN MEMORY - DQ PARALLEL TERM CHANGED TO 82 OHM
FIREWIRE POWER - NEW CURRENT LIMITING RESISTOR
NOSTUFFING FIREWIRE PORT POWER "CHOICE A" CIRCUIT
INPUT VOLTAGE SENSE - CHANGED DIVIDER VALUES
INPUT CURRENT SENSE - CHANGED R3343 TO 0.025 OHM 1% RESISTOR
CHECKIN 22003

04/21/04

SMU_SUSPENDREQ - STUFFED LEVEL SHIFTER


CPU POWER SUPPLY - NOSTUFFED R3305
CHANGED R3304 TO 116S1000
CHANGED C3304-7 TO 132S4733
EVT3A BOM RELEASE REV 23

04/26/04

USB POWER CAPS - NOSTUFFED C9211, C9221, C9231


PULSAR_POWER_DOWN CONNECTED TO SMU_PWRSEQ_P1_4
SW703 CHANGED TO 516S0221
MASTER PAGE SYNC
CHECKIN 23001

04/27/04

MASTER PAGE SYNC - AUDIO AND SMU CHANGES


SUSPENDACK LEVEL SHIFTER - REPLACED Q2407 AND Q2408 WITH Q2420 SN7002DW
I2C_CPU_A - ADDED Q1801 TO LEVEL SHIFTER
ADDED POWER SUPPLY TEMP SENSOR
Q3000 ADDED TO LEVEL SHIFT / INVERT CPU_BYPASS AND CPU_HRESET
CURRENT SENSE - CHANGED R3345 FROM 121K TO 73.2K
CHECKIN 23002

04/29/04

QREQ CIRCUITS MOVED TO PWRON RAIL


I2C UPDATE
NB_SUSPENDACK_L NOW USED U700 TO LEVEL SHIFT - OLD CIRCUIT REMOVED
DIMMS - UPDATED TO 25/28 DEGREE CONNECTORS
MASTER PAGE SYNC
CHECKIN 23003

04/30/04

SOFT MODEM - ADDED DECOUPLING CAPS TO POWER RAIL


REMOVED OLD OVERTEMP CIRCUIT
ADDED DIAG LED
MASTER PAGE SYNC
CHECKIN 23004

05/03/04

CPU POWER SUPPLY - ON SEMI FETS ONLY


ADDED 1.6GHZ CPU PART NUMBER
UPDATED PLATING FOR ZH702
CHECKIN 23005

A
05/05/04

05/11/04

DVT RELEASE (REV 25)

06/10/04

LAST MINUTE BOM CHANGES FOR DVT:


SUSPENDREQ LEVEL SHIFTER - R2419, R2420 CHANGED TO 330 OHM
I2C A BUS PULLUPS - R1816,R1817 CHANGED TO 200 OHM
USB PULL-DOWNS - R9403,R9404 MOVED TO COMMON BOM
SMU CRYSTAL CAPS - C1304,C1305 CHANGED TO 18PF FROM 12PF
SMU RESET - CHANGED R1322 TO 150K FROM 100K
CPU HEATSINK ASSEMBLIES - NEW PART NUMBERS
TMDS POWER - CHANGED D5914 TO SURFACE MOUNT PART FROM THROUGH HOLE
MOVED R714 TO R1303 FOR SCHEMATIC REUSE
U1600,U1601,U1700 CHANGED TO 353S0890 FOR MORE SOURCES
MOVED CPU LOGIC ANALYZER RESISTORS TO DEVELOPMENT BOM
CHECKIN 25001

06/11/04

MASTER PAGE SYNC - NOSUFFED EXTERNAL S/PDIF TRANSMITTER


ADDED TABLES FOR:
NEW 1.5V FET - LOWER RDS(ON) - Q5006
PATA CONN J8301 CHANGED TO 516S0235 (ADDED VENDOR)
NEW SATA CONNECTER SOURCES J8300, J8302
NEW TMDS CONNECTOR W/ BOSS J5902
REMOVED COIN CELL BATTERY AND I/O ALIGNMENT FIXTURE FROM MLB BOM (FATP ITEMS)
NEW BACKUP SMU_RESET CIRCUIT (SAME AS Q78)
CHECKIN 25003

06/21/04

RAM PARALLEL TERM - DQ RPAKS CHANGED TO 68 OHM


STROBE RESISTORS CHANGED TO 120 OHM
EVT3A RELEASE (REV 22)
CHECKIN 22001 - FIXING DIMM SYMBOL
CHECKIN 22002 - FIXING DIMM SYMBOL AGAIN

04/14/04

DESCRIPTION

02/27/04

04/13/04

06/22/04

REPLACED Q5006 (FET FOR 1.5V) WITH 376S0254


FAN OPAMPS - REPLACED U1600 W/ SECOND OPAMP IN U1700
TIED INPUTS IN UNUSED OPAMP IN U1601
NOSTUFFED CPU VREG ELECTROLYTIC CAPS C3332, C3427, C3421
NOSTUFFED R2775/6 (UNUSED CLOCKS)
CHECKIN 25004

06/22/04
06/23/04

"PROPERLY" TERMINATED UNUSED OPAMP IN U1601


BOM RELEASE REV 26

06/24/04

"PROPERLY" TERMINATED UNUSED OPAMP IN U2100


R5010 REMOVED TO DECREASE DROOP ON 1.5V RAIL
ADDED CONNECTOR J1701 TO SUPPORT REMOTE HD TEMP SENSOR
CHECKIN 26001

06/28/04

MASTER PAGE SYNC - PICKED UP AUDIO CHANGES RELATED TO BITCLK


CHECKIN 26002

06/28/04

SUPPORT FOR 2GB DIMMS - SWAPPED PINS 103 & 167 ON DIMM CONNECTOR
CHECKIN 26003

07/01/04

ADDED SECOND SOURCE VTT REGULATOR (PAGE 46)


NO STUFF POWER SUPPLY TEMP SENSOR
CHANGED HD TEMP SENSOR CONN J1701 TO 4 PIN
MASTER PAGE SYNC - AUDIO CHANGES
CHECKIN 26004

07/02/04

UPDATED LINE AND NECK WIDTH CONSTRAINTS THROUGHOUT SCHEMATIC


NOSTUFFED ON BOARD HD TEMP SENSOR
CHANGED U3LITE CORE TO 1.53V
FEEDBACK RESISTORS CHANGED TO 603
CHECKIN 26005

CPU AVDD - ADDED 2.7V BOM OPTION


POWER_FAIL - RESISTOR DIVIDED TO 3.3V
ADDED BOMS OPTIONS FOR ON_SEMI AND VISHAY FETS FOR 3PHASE AND 4PHASE
CPU PS AVP CHANGES
CPU VREG - ADDED BOM OPTION EXTRA_C FOR CAPS WE WOULD LIKE TO NOSTUFF
CHECKIN 23006
CPU VREG AVP - C3304, C3305, C3306, C3307 CHANGED TO 8.2NF
TMDS TERM - STUFFING CHANGES
CHECKIN 23007

U3LITE PWR SEQ - CHANGED C915 TO 0.22UF


P/S TEMP SENSOR - NOSTUFF
REMOTE HD TEMP SENSOR CONNECTOR - NOSTUFF
PVT / PRODUCTION RELEASE (REV A)

07/28/04

STUFFED TMDS CONNECTOR J5902 (ACCIDENTALLY OMITTED)


FIREWIRE CRYSTAL - CHANGED R9061 TO 470 OHM
2.5V VREG - CHANGED SOFT START CAP TO 0.68UF
NEW P/N FOR HEATSINK ASSEMBLIES
NOSTUFFED OPTICAL TEMP SENSOR
STUFFED REMOTE HD TEMP SENSOR CONNECTOR
BOM RELEASE (REV B)

08/03/04

2.5V VREG - CHANGED SOFT START CAP TO 0.47UF


I/O CONNECTOR SHIELD CHANGE P/N TO 805-5664
NEW CPU P/N AND BINCODES FOR 1.10V VMIN

07/06/04

REMOVED ON BOARD HARD DRIVE TEMP SENSOR


AUDIO DETECT PULLUPS - CHANGED FROM 47K TO 4.7K
CHANGED AUDIO I2S_BITCLK SERIES RESISTER TO 0 OHM
U3LITE FEEDBACK RESISTORS CHANGED TO 0.5% TOLERANCE
CHECKIN 26006

07/08/04

REPLACED MAXIM ANALOG SWITCH U2850 WITH TI ANALOG SWITCH


PERICOM ADDED AS AN ALTERNATE
ALL I/O CONNECTORS CHANGED
POWER CONNECTOR CHANGED
POWER SWITCH CHANGED
SMU DOWNLOAD CONNECTOR - PRODUCTION P/N
CPU PART NUMBERS - UPDATED WITH ACTUAL PART NUMBERS
CHECKIN 26007
BOM RELEASE REV 27

07/12/04

CPU VREG DROOP - R3327 CHANGED TO 1.5K; R3326 CHANGED TO 301


PULSAR_POWER_DOWN - R2750 CHANGED TO 47 OHM FOR ICT
AUDIO DETECT PULLUPS - CHANGED BACK TO 47K FROM 4.7K
AUDIO MUTE PULLDOWNS R9815 & RA012 - CHANGED FROM 47K TO 4.7K
MIC BIAS - NOSTUFFED CA210 TO HELP NOISE FLOOR
1.5V_RUN FET - ADDED (N/S) C5060 FOR POSSIBLE SOFT-START
2.5V VREG SOFT START - CHANGED C915 TO 1UF FOR U3L POWER SEQUENCING
MLB CARCODE - CHANGED TO 825-6447
I/O CONNECTOR SYMBOL UPDATES
CHECKIN 27001

07/13/04

07/15/04

REVISION HISTORY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

07/14/04

FIREWIRE CRYSTAL - ADDED R9060 & R9061


CHECKIN 27003
FIREWIRE CRYSTAL R - FIXED REF DES
ANALOG SWITCH U2850 - ADDED PERICOM & AND MAXIM AS ALTERNATES TO TI
STUFFED P/S TEMP SENSOR
NAMED SOME UNNAMED NETS
CHECKIN 27004

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

REV.

051-6482

SHT
NONE

NOTICE OF PROPRIETARY PROPERTY

POWER_FAIL_L R DIVIDE - ADJUSTED FOR 2K PULLUP THAT WILL BE IN PVT POWER SUPPLIES
ORIGIN HOLE ZH702 - CHANGED TO 4.15MM
CHECKIN 27002

OF

C
103

ASICS

PROCESSORS

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

343S0284

IC,U3LITE,V1.1,300MM,PBGA

U3

QUALIFIED

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

343S0282

343S0284

TABLE_11_HEAD

PART #

QTY

DEVICE

PACKAGE

DESCRIPTION

VALUE

VOLT.

WATT.

TOL.

REFERENCE DESIGNATOR(S)

REF DES

COMMENTS:

U3

U3L,V1.1,200MM,PBGA

TABLE_ALT_ITEM

TABLE_11_HEAD

BOM OPTION

BOM OPTION

337S2968

PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD3,1.6G,85C,ARA

1.6GHZ

1.25V

45W

U2900

CPU_DD30_1_6GHZ

337S2969

PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD3,1.8G,85C,BPA

1.8GHZ

1.20V

45W

U2900

CPU_DD30_1_8GHZ

TABLE_11_HEAD

TABLE_5_HEAD

PART#

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

337S2970

337S2969

BOM OPTION

REF DES

VOLTAGE

COMMENTS:

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

343S0283

IC,ASIC,SHASTA,V1.1,PBGA

U2300

TABLE_ALT_ITEM

CPU_DD30_1_8GHZ U2900

IC,GPUL,DD3,1.8G,BRA

1.25V

NOT QUALIFIED

MISC PARTS
TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_5_HEAD

VOLTAGE

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

337S2957

337S2786

CPU_DD30_1_8GHZ U2900

IC,GPUL,DD3,1.8G,BNA 1.20V

062-2082

SPEC,VENDOR PACKAGING PROCEDURE

VPP1
TABLE_5_ITEM

820-1540

PCB,FAB,MLB

MLB1

825-6447

BARCODE LABEL, MLB, Q45

LBL1

051-6482

PCB,SCHEM,MLB

SCH1

341T1366

IC,FLASH,1MX8,3.3V,90NS

U7500

341T1395

PURCH ASSY, SMU BIG

U1300

CRITICAL 603-6015

HEAT SINK ASSEMBLY 17 IN

MECH17

17_INCH_LCD

CRITICAL 603-6016

HEAT SINK ASSEMBLY 20 IN

MECH20

20_INCH_LCD

TABLE_5_ITEM

TABLE_11_HEAD

PART #

QTY

DEVICE

PACKAGE

DESCRIPTION

VALUE

VOLT.

WATT.

TOL.

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_ITEM

TABLE_11_HEAD

337S2865

PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD2.11,1.8GHZ,85C

1.8GHZ

1.45V

45W

U2900

CPU_DD211_1_8GHZ

TABLE_5_ITEM

TABLE_11_HEAD

337S2866

PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD2.11,2.0GHZ,85C

2.0GHZ

1.45V

45W

U2900

CPU_DD211_2_0GHZ

TABLE_5_ITEM

TABLE_11_HEAD

337S2787

PROCESSOR CBGA-576-1MM IC,GPUL,10S,REV3,2.0G,85C,CJA

2.0GHZ

1.25V

45W

U2900

CPU_DD30_2_0GHZ

TABLE_5_ITEM

TABLE_5_ITEM

ALTERNATES
TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

378S0119

378S0114

BOM OPTION

REF DES

COMMENTS:

LED700,LED702,LED5900
KINGBRIGHT LED

TABLE_ALT_ITEM

TABLE ITEMS
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

OF

C
103

1
PP12V_RUN

I3
I4
I5
I6
I7
I8
I9
I10

I295
I296
I297
I298
I300
I299
I302

I307
I311
I314
I315
I316
I317

I320
I319
I322
I323
I321
I336
I337
I338
I340
I339
I342
I343

I341
I344
I345
I346
I347
I348
I350
I349

I354
I355
I356
I357
I358
I360
I359
I362
I363
I361
I364
I365
I372
I373
I371
I374
I375

I376
I377
I378
I380
I379
I382
I383
I381
I384
I385
I386
I388
I387
I390
I389
I391
I393
I392
I395
I394
I396
I398
I397
I399
I401
I400

I403
I402
I404
I405
I406
I408
I407
I426
I429
I428
I431
I430
I432

NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES

TP_BUF_RST
TP_DFPCLK
TP_DFPCLK_L
TP_DFPD0
TP_DFPD1
TP_DFPD2
TP_DFPD3
TP_DFPD5
TP_DFPD6
TP_EXT_TMDS_CKM
TP_EXT_TMDS_CKP
TP_EXT_TMDS_D0M
TP_EXT_TMDS_D0P
TP_EXT_TMDS_D1M
TP_EXT_TMDS_D1P
TP_EXT_TMDS_D2M
TP_EXT_TMDS_D2P
TP_FBBCS1_L
TP_GPU_INTB_L
TP_GPU_THERMA
TP_GPU_THERMC
TP_IFP1VREF
TP_NVAGP_TDO
TP_TMDS_TXD3M
TP_TMDS_TXD3P
TP_TMDS_TXD7M
TP_TMDS_TXD7P
TP_VIPHCLK
TP_FRWRLPS
TP_AGP_MB_AGP8X_DET_L
TP_ATTENTION
TP_ENET_CLK125M_GTX
TP_ENET_TXD<7>
TP_ENET_TXD<4>
TP_ENET_TXD<5>
TP_FW_CLK98M_LCLK
TP_AFN
TP_PSRO1
TP_PSRO2
TP_PSYNCOUT
TP_USB2_PWREN<2>
TP_USB2_PWREN<3>
TP_USB2_PWREN<4>
TP_NEC_AMC
TP_NEC_NANDTEST
TP_NEC_NTEST1
TP_NEC_SMC
TP_NEC_SMI_L
TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD
TP_NEC_TEB
TP_NEC_TEST
TP_PLS_CLK_66M_0
TP_PLS_CLK_66M_1
TP_PLS_REF_CML
TP_PLS_TEST1
TP_PLS_TEST2
TP_PLS_TEST3
TP_SB_FSTEST
TP_SB_PLLTEST
TP_VREF_CG
TP_SB_NC_P7
TP_SB_NC_P8
TP_SB_NC_R3
TP_SB_NC_R4
TP_SB_NC_R5
TP_SB_NC_R6
TP_SB_NC_R7
TP_SB_NC_R8
TP_SB_NC_T1
TP_SB_NC_T2
TP_SB_NC_T3
TP_SB_NC_T4
TP_SB_NC_T5
TP_SB_NC_T6
TP_SB_NC_T7
TP_SB_NC_T8
TP_SB_NC_U1
TP_SB_NC_U2
TP_SB_NC_U3
TP_SB_NC_U4
TP_SB_NC_U5
TP_SB_NC_U6
TP_SB_NC_V1
TP_SB_NC_V2
TP_SB_NC_V3
TP_SB_NC_V4
TP_SB_NC_W1
TP_SB_NC_W3
TP_SB_NC_Y1
TP_SB_NC_Y3
TP_SATA_CLK25M
TP_ENET_TCK
TP_USB2_PWREN<0>
TP_USB2_PWREN<1>
TP_DUMMY_A
TP_DUMMY_B
TP_RAM_CKE_R<2>

NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES

TP_RAM_CKE_R<3>
TP_RAM_CKE_R<6>
TP_RAM_CKE_R<7>
TP_RAM_CS_L_R<10>
TP_RAM_CS_L_R<11>
TP_RAM_CS_L_R<2>
TP_RAM_CS_L_R<3>
TP_RAM_MUXEN0
TP_RAM_MUXEN4
TP_NB_PM_SLEEP0
TP_J4000_SJRESET_L
TP_J4001_SJRESET_L
TP_CMP_SPARE
TP_ENET_TXD<6>
U2100_UNUSED
PLS_CLK_66M_0_R
PLS_CLK_66M_1_R

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

90

IN

24

90

IN

40

90

IN

77 76 75 74 73

IN

77 76 74 73

IN

21

IN

27

76 74

IN

27

76 74

IN

76 25

IN

52

74 58 51 8

IN

49

77 76 74 73

IN

58

77 76 74 73

IN

58

77 76 74 73

IN

58

77 76 74 73

IN

49

77 76 74 73

IN

77 76 74 73

IN

76

IN

76 75 74

IN

76 75 74

IN

57

I434

58

I433

58

I436

58

I435

58

I437

58

I439

58

I438

58

I440

58

I441

58

I442

58

I444

58

I443

58

I445

58

I446

58

I781

58

I809

58

I810

GENZ SHOULD USE J1400 FOR THE FOLLOWING NETS:


EI_CPU_TO_NB_AD<0..43>
NO_TEST=TRUE
I782
EI_CPU_TO_NB_CLK_N
NO_TEST=YES
I784
EI_CPU_TO_NB_CLK_P
NO_TEST=YES
I785
EI_CPU_TO_NB_SR_N<0..1>
NO_TEST=TRUE
I786
EI_CPU_TO_NB_SR_P<0..1>
NO_TEST=TRUE
I787
EI_NB_TO_CPU_AD<0..43>
NO_TEST=TRUE
I789
EI_NB_TO_CPU_CLK_N
NO_TEST=YES
I788
EI_NB_TO_CPU_CLK_P
NO_TEST=YES
I790
EI_NB_TO_CPU_SR_N<0..1>
NO_TEST=TRUE
I792
EI_NB_TO_CPU_SR_P<0..1>
NO_TEST=TRUE
I791
CHKSTOP_L
NO_TEST=YES
I793
CPU_HRESET_L
NO_TEST=YES
I794
CPU_INT_L
NO_TEST=YES
I795
CPU1_HTBEN
NO_TEST=YES
I796
EI_CPU1_CLK_N
NO_TEST=YES
I797
EI_CPU1_CLK_P
NO_TEST=YES
I798
EI_QACK_L
NO_TEST=YES
I799
EI_QREQ_L
NO_TEST=YES
I800
EI_SE
NO_TEST=YES
I801
I2C_SMU_A_SCL_OUT_L
NO_TEST=YES
I802
I2C_SMU_A_SDA_OUT_L
NO_TEST=YES
I803
MCP_L
NO_TEST=YES
I804
RI_L
NO_TEST=YES
I805
SYNCENABLE
NO_TEST=YES
I806
TP_PROC_TRIGGER_OUT
NO_TEST=YES
I807
EI_CPU1_SYNC
NO_TEST=YES
I808

58
58
58
58
57
58
48
29
87
87
87
87
90
29
29
29
29
92
92
92

77
77
77

87

14 28 29
14 28 29
14 28 29
76 75 74

IN

76 75

IN

76

IN

14 28 29
14 28 29
14 28 29
14 28 29
92

IN

92

IN

14 28 29
14 28 29
14 28 29
92

IN

92

IN

92

IN

8 14 29
14 29 30
14 25 29 30
92

IN

92

IN

92

IN

92

IN

14
14 27
14 27
14 28 29
92

IN

92

IN

14 28 29 30
14 28 29 30
13 14 18
94 76 25

IN

94 25

IN

94 25

IN

94 76 25

IN

13 14 18
14 29
14 29 30
14 29 30

IN

94 25

IN

77

94 25

IN

77

94 18

IN

77

94 18

IN

77

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

PCI_AD<31..0>
PCI_CBE_L<3..0>
PCI_CLK33M_AIRPORT
PCI_SLOTA_REQ_L
PCI_SLOTA_GNT_L
PCI_SLOTA_INT_L
PCI_RESET_L
PCI_FRAME_L
PCI_TRDY_L
PCI_IRDY_L
PCI_STOP_L
PCI_DEVSEL_L
PCI_PAR
PCI_SLOTA_IDSEL
ROM_CS_L
ROM_OE_L
ROM_WE_L
ROM_ONBOARD_CS_L
AIRPORT_CLKRUN_L_PD

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

IN
11 7

IN

18 11

IN

18 11

IN
IN

PP12V_RUN
PP5V_ALL
PP5V_RUN
PP3V3_RUN
PP24V_RUN

10 TEST POINTS

5 TEST POINTS

12 TEST POINTS

83 7

IN

83 7

IN

=PP5V_DISK
=PP12V_DISK

IN

GND

40

94 76 25

77

FW_VP_PORT1
FW_TPO1P
FW_TPO1N
FW_TPI1P
FW_TPI1N
FW_VP_PORT2
FW_TPO2P
FW_TPO2N
FW_TPI2P
FW_TPI2N
FW_VGND

14 29
14 27

77

94

IN

77

94

IN

27

94 25

IN

27

94 25

IN

27

94

IN

27

59

IN

27

59

IN

25

59

IN

25

59

IN

48

59

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

91

USB_BT_N
USB_BT_P

FUNC_TEST=YES
FUNC_TEST=YES

USB2_PORT1_N_F
USB2_PORT1_P_F
USB2_PORT2_N_F
USB2_PORT2_P_F
USB2_PORT3_N_F
USB2_PORT3_P_F
PP5V_USB2_PORT1_F
PP5V_USB2_PORT2_F
PP5V_USB2_PORT3_F

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

I2S1_DEV_TO_SB_DTI
I2S1_SYNC
I2S1_BITCLK
I2S1_MCLK
I2S1_SB_TO_DEV_DTO
I2S1_RESET_L
MODEM_RING2SYS_L
I2C_UDASH_SDA
I2C_UDASH_SCL
USB_UDASH_N
USB_UDASH_P
UDASH_SDOWN
UDASH_RESET_L
UDASH_I2C_A1_PU

2
2
2
2
2
2
2

TEST
TEST
TEST
TEST
TEST
TEST
TEST

POINTS
POINTS
POINTS
POINTS
POINTS
POINTS
POINTS

59

IN

91

59

IN

91

59 7

IN

91

59

IN

91

59

IN

91

59

IN

91

59 57 56

IN

91

59 57 56

IN

91

59

IN

91

59

IN

91

59 58

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

91

59

IN

FILT_ANALOG_RED
FILT_ANALOG_GRN
FILT_ANALOG_BLU
ANALOG_HSYNC_L
ANALOG_VSYNC_L
VGA_IIC_CLK
VGA_IIC_DAT
MON_DETECT
DDC_VCC_5

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

PP24V_INV
GND_20_INV
INV_20_LCD_PWM_
INV_20_CUR_HI_F
PP12V_INV
GND_17_INV
PP5V_AGP_RL
INV_17_LCD_PWM_F
LAMP_STS_F
INV_17_CUR_HI_F

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

CPU_VID_R<5..0>
KPVDD2_FMAX
KPGND2_FMAX
TDIODE_POS_FMAX
TDIODE_NEG_FMAX
CORE_ISNS_M
CORE_ISNS_P

FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

5 TEST POINTS
5 TEST POINTS

PP24V_RUN

PP3V3_RUN

FUNC_TEST=YES
FUNC_TEST=YES

5 TEST POINTS

FUNC_TEST=YES

PP1V5_RUN
IN
IN
18 11

IN

27 18 11

IN
IN

10 3

IN

13 8 7

IN

31 8 7 3

IN

22 7

IN

35 34 33 7

IN

34 33

IN

33

IN

33

IN

8 7

IN

13 7

IN

IN

IN

13 8

IN

33 13 11 10 7

IN

50 46 11 10 9 8

IN

13 8

IN
IN

IN

22

IN

59 57

IN

59 57

IN

59 57

IN
IN

27

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

5 TEST POINTS

PP5V_ALL

PP2V5_RUN PP5V_PWRON

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

PPVCC_TMDS
PP3V3_DDC
TD0M
TD0P
TD1M
TD1P
TD2M
TD2P
TCKM
TCKP
TMDS_DDC_DAT
TMDS_DDC_CLK
GND_CHASSIS_TMDS

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

5 TEST POINTS

PP5V_RUN

101 25

IN

75

IN

83 80

IN

83 80

IN

83 80

IN

83 80

IN

83 80

IN

83

IN

83 80

IN

83 806 6
83 80
83

IN

83 80

IN

83

IN

83

IN

83

IN

36 31

IN

76

IN

76

IN

IN

PP2V5_RUN
PP1V5_RUN
PP5V_PWRON
PP3V3_PWRON
PP1V2_PWRON
PPVCORE_PWRON_SB
=PP3V3_ALL_SMU
=PP5V_RUN_CPU
PPVCORE_NB
PPVCORE_CPU
PP12V_CPU
VCORE_SENSE_GND
VCORE_SENSE_VOUT
SMU_MANUAL_RESET_L
SYS_POWER_BUTTON_L
POWER_BUTTON_L
RESET_BUTTON_L
SMU_RESET_L
SYS_POWERUP_L
SYS_SLEEP
SYS_POWERFAIL_L
EXT_POWER_BUTTON_L
U900_FEEDBACK
U2200_FEEDBACK
ANALOG_RED
ANALOG_GRN
ANALOG_BLU
AUDIO_LI_DETECT_L
AUDIO_LO_DET_L
ROM_WP_L

2 TEST POINTS
2 TEST POINTS

PP1V2_PWRON

PP3V3_PWRON

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES

UATA_DD<15..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_RESET_L
UATA_DSTROBE_R
UATA_HSTROBE
UATA_STOP
UATA_DMARQ_R
UATA_DMACK_L
UATA_INTRQ_R
UATA_IOCS16_PU
UATA_CSEL_PD

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

TDIODE_NEG
TP_AIRPORT_PME_L
TP_AIRPORT_RF_DISABLE

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

91

91

59

IN

27

33 8

IN

87

36

IN

92

36

IN

92

36

IN

24

36

IN

24

36 33

IN

36 33

IN

91

FUNC TEST
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

91

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT

NONE

REV.

051-6482
C
6
103
OF

7
PP12V_RUN

PP5V_RUN

PP5V_ALL

PP3V3_RUN

PP12V_RUN

PP5V_RUN

ONLY ON IN RUN

J700
F-RT-TH

D
POWER_GOOD

12

13

14

15

16

17

18

19

20

10

21

11

22

=PP24V_GRAPHICS

VOLTAGE=24V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

HM96110-P2

59

PWRON RAILS

ALL RAILS

ON IN RUN AND SLEEP

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

PP5V_PWRON

PP12V_RUN

VOLTAGE=12V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

=PP12V_AGP
=PP12V_RUN_CPU
=PP12V_DISK

33

PP12V_AUDIO_CODEC

102

ALIAS

PP12V_AUDIO_SPKRAMP

100

XW705
SM
1

U700

14
2

SYS_POWERUP_L

33 13 11 10 6

74LCX125

C700

=PP5V_PATA
=PP5V_DISK

125
1 TSSOP

23
11 6
23
94

49 50 59

R710
330

R700
330

2 ITS_PLUGGED_IN

5%
1/16W
MF
603

DEVELOPMENT

R701
330

ITS_ALIVE

5%
1/16W
MF
603

LED702

VOLTAGE=3.3V
MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
MAKE_BASE=TRUE

PP3V3_RUN

GREEN
2.0X1.25A

GREEN
2.0X1.25A
2

5%
1/16W
MF
603

LED700

GND RAILS
XW702
SM

28

GND_AUDIO

=PP2V5_PWRON_HT

LED701

26 37 40

62

102 100

GND_AUDIO_SPKRAMP

SYS_POWER_BUTTON_L

2 SYS_PWR_BTN_FILT

VOLTAGE=2.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

83

74

C
1

PPVCORE_NB

5%
1W
FF
2512

25 74 75 76 77
77

ZH700
315R138
102 101

83

PP2V5_GPU

ALIAS

MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.2V

50 52 54 55

=PP2V5_RUN_CPU
=PP2V5_RUN_RAM

=PP1V2_PWRON_HT
=PP1V2_PWRON_DISK_SB
=PP1V2_PWRON_SB

62
59
80
92
25

31

90

SILKSCREEN:POWER
3

L701

GND_CHASSIS_VGA
GND_CHASSIS_USB
GND_CHASSIS_FIREWIRE

ALIAS

ZH701

7R4.15

48 49
26

GND_CHASSIS_RJ45
MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

87

101

GND_SYS_PWR_BTN_FILT

21

SM
35 34 33 6

PPVCORE_CPU

=PPVCORE_CPU

GND_CHASSIS_TMDS
MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

ZH702

=PP1V5_AGP
=PPVCORE_PULSAR

VOLTAGE=1.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

FERR-EMI-100-OHM

SH700

GND_CHASSIS_AUDIO_INTERNAL
MAKE_BASE=TRUE
GND_CHASSIS_LED

ALIAS

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

POWER SWITCH - 17INCH

SW703

POWER SWITCH - 20INCH

SW703

SHLD-IO-CONN
Q45-TH1
3

805-5664

6.00MM-PTH

17_INCH_LCD

59
TABLE_5_ITEM

516S0249

ZH703

BOM OPTION
TABLE_5_ITEM

516S0248

7 29 31 32 36

MAKE_BASE=TRUE

TABLE_5_HEAD

PART#

GND_CHASSIS_AUDIO_EXTERNAL
MIN_NECK_WIDTH=15MIL
MAKE_BASE=TRUE
VOLTAGE=0
MIN_LINE_WIDTH=25MIL

44 45 46

PP1V5_RUN

20%
10V
2 CERM
402

CHASSIS GND

6 22

315R138

ST-SM3

0.1UF

R707

33

59 6

PWR-BUTT

C703

26

SW703

SM

28 37 48 60

PP2V5_RUN

OMIT
CRITICAL

FERR-EMI-100-OHM
13 7 6

95 100 101 102 103

SILKSCREEN:RUN

L700

=PP1V5_PWRON_NB_AVDD
=PPVCORE_PWRON_PULSAR

MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

48 49 50 51 52 56 57 58 59

XW707
SM

PP1V2_PWRON
2

SILKSCREEN:2

60 64

XW703
SM

GREEN
2.0X1.25A

SILKSCREEN:1

XW706
SM

23 25 74 88

46

PP3V3_AUDIO
=PP3V3_RUN_CPU
=PP3V3_PATA
=PP3V3_SB_PCI
=PP3V3_PCI
=PPVIO_PCI_USB2
=PP3V3_DISK

ITS_RUNNING
DEVELOPMENT

36

36

101

=PP3V3_AGP
ALIAS

=PP5V_ALL_CPU

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

94

PP1V5_PWRON

PP3V3_PWRON

36

92

=PP2V5_PWRON_RAM
=PP2V5_HT

3 6 8 31

PP5V_ALL

PP3V3_RUN

PP5V_ALL

=PP3V3_ALL_CPU

87

102

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

6 83

=PP5V_RUN_CPU
PP5V_AUDIO
=PP5V_RUN_RAM

ALIAS

6 8 13

=PP3V3_ALL_EI

91

=PP2V5_PWRON_SB

83

=PP5V_AGP

SYS_POWERUP_L_BUF

=PP3V3_ALL_SMU

23 25 74

PP2V5_PWRON

VOLTAGE=5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

20%
2 10V
CERM
402

PP5V_RUN

0.1UF

CRITICAL

PP3V3_ALL
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

76

=PP3V3_PWRON_SB
=PPPCI64_PWRON_SB
=PPPCI32_PWRON_SB
_PP3V3_PWRON_MODEM
=PP3V3_PWRON_USB
PP3V3_PWRON_ENET
_PP3V3_PWRON_BT
_PP3V3_PWRON_UDASH
=PP3V3_PWRON_CPU
=PP3V3_PWRON_EI

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

PIN 13,19,11,22 ARE DIFFERENCE FROM ATX .

PP3V3_ALL

36

PP5V_ALL

90 59 11 7

94

PP3V3_PWRON

XW701
SM

P/N 518-0159

92

6 83

XW704
SM

VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

_PP5V_PWRON_USB
_PP5V_PWRON_UDASH
=PP5V_PWRON_CPU
=PP5V_PWRON_AIRPORT

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

50 59

XW700
SM

90 59 11 7

RUN RAILS

PP24V_RUN

CRITICAL

PP24V_RUN

20_INCH_LCD

GND_CHASSIS_17_INCH_INVERTER
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

SDF700

HSK-NUT-6.5MM
TH

13 7 6

R713
1K

SYS_POWER_BUTTON_L
DEVELOPMENT

R712
13

SYS_RESET_BUTTON_L 1

1K

5%
1/16W
MF
402

59

POWER_BUTTON_L

RESET_BUTTON_L

5%
1/16W
MF
402

PP1V2_RUN

2
DEVELOPMENT

SW701

SM
2

2
1

C705
0.1UF

20%
10V
2 CERM
402
4

PP1V5_RUN

C704
0.1UF

R7191

POWER
36 32 31 29 7

=PPVCORE_CPU
NOSTUFF

8 6

R7051

SMU_MANUAL_RESET_L

0
5%
1/10W
FF
805 2

SW700
SPST
SM
1

5%
1/10W
FF
805 2

R718 R7151
0

5%
1/10W
FF
2 805

5%
1/10W
FF
805 2

NOSTUFF

R703

35 31 30 29 18 14

=PP1V2_EI_CPU

PP1V2_EI_CPU
VOLTAGE=1.2V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

SMU RESET

=PP3V3_ALL_RTC

5%
1/10W
FF
2 805

5%
1/10W
FF
805 2

NOSTUFF

R709

402

PP1V25_RAM_VTT

44 45 46

0
5%
1/10W
FF
2 805

POWER CONN / ALIAS

NOSTUFF

R717
0

NOTICE OF PROPRIETARY PROPERTY

5%
1/10W
FF
805

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

PP1V2_EI_NB

=PP1V2_EI_NB

VOLTAGE=1.2V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


14 18 28

SIZE

APPLE COMPUTER INC.

5%
1/10W
FF
805

BB10209-A5

1K 2 PP3V3_ALL_BATT
2
1PP3V3_ALL_BATT_SAFETY 1
1
2
PP3V3_ALL_RTC
VOLTAGE=3.3V
VOLTAGE=3.3V
VOLTAGE=3.3V
5%
MIN_LINE_WIDTH=25MIL
MIN_LINE_WIDTH=25MIL
MIN_LINE_WIDTH=25MIL
1/16W
MIN_NECK_WIDTH=10MIL MBR0530 MIN_NECK_WIDTH=10MIL
MIN_NECK_WIDTH=10MIL TH
MF
MAKE_BASE=TRUE

5%
1/10W
FF
805
1

J702

R702

II NOT TO REPRODUCE OR COPY IT

R704
0

13

5%
1/10W
FF
805

26

R716

5%
1/10W
FF
2 805

R711

R7081

R706

CRITICAL

DS700
SM

NOSTUFF

NOSTUFF

ALWAYS ON (TRICKLE)

24 60

=PP1V2_PULSAR

20%
10V
2 CERM
402

RESET

=PP1V2_HT

RTC BATTERY

VOLTAGE=1.2V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SPST

SM

EI OVDD POWER OPTIONS

SW702

SPST
1

GND_CHASSIS_20_INCH_INVERTER
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

OF

C
103

PCI CLOCKS

37

ALIAS

RAM_CKE_R<3>

37

ALIAS

RAM_CKE_R<6>

37

ALIAS

RAM_CKE_R<7>

37

ALIAS

RAM_MUXEN0

37

ALIAS

RAM_MUXEN4

37

ALIAS

RAM_CS_L_R<2>

37

ALIAS

RAM_CS_L_R<3>

37

ALIAS

RAM_CS_L_R<10>

37

ALIAS

RAM_CS_L_R<11>

37

TP_PCI_CLK_GP1
MAKE_BASE=TRUE
PCI_CLK33M_AIRPORT
MAKE_BASE=TRUE

I247

PCI_CLK_P4

ALIAS

TP_ALS0_OUT
MAKE_BASE=TRUE
TP_ALS1_OUT
MAKE_BASE=TRUE
TP_ALS_GAIN_BOOST
MAKE_BASE=TRUE
TP_SMU_ONEWIRE
MAKE_BASE=TRUE

R850
180

5%
1/16W
MF
2 402

LED850P1

LED850

13 8

RED

2
74 58 51 6

LED850P2

27

ALS0_OUT

13

ALIAS

ALS1_OUT

13

ALIAS

PP2V5_PWRON

ALS_GAIN_BOOST

R870
4.7K

ALIAS

13

SMU_ONEWIRE

DEVELOPMENT

5%
1/16W
MF
2 402
13 8

13

PCI_RESET_L
MAKE_BASE=TRUE

14

Q850

74LCX125

SMU_WARM_RESET_L

J800

U700
8
7

13

SMU_PWRSEQ_P1_3

13

SYS_DOOR_AJAR_L

13

FAN_PWM8

13

SYS_DRIVE_BAY_INT_L

13

NB_WARM_RESET_L

24

14
13

74LCX125

SMU_SLEEP

SYS_SLEEP

518S0104

U700
24

14

74LCX125

125
13 TSSOP

12

NB_SUSPEND_ACK_L

11

NB_SUSPENDACK_L

76

SMU ANALOG VREF

75

5%
1/16W
MF
2 402

R821

13

13

CPU_VID<4>

13

CPU_VID<5>

R808

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R809

10K

5%
1/16W
MF
2 402

10K

5%
1/16W
MF
2 402

R804
13
13

SMU_BOOT_SCLK
SMU_BOOT_CE

6 33

SMU_BOOT_CNVSS

R8061

CPU_VID_R<3>

6 33

CPU_VID_R<4>

6 33

R818

10

CPU_VID_R<5>

6 33

10K
5%

5%
1/16W
MF
402 2

J802_6

NOSTUFF
1

R805
0

5%
1/16W
MF
402 2

1/16W
MF
2 402

100

5%
1/16W
MF
402

SMU_BOOT_BUSY
SMU_BOOT_RXD

C801

13

(SMU_BOOT_EPM)
SMU_MANUAL_RESET_L
SMU_BOOT_TXD

PPVREF_SMU
MAKE_BASE=TRUE

NOSTUFF

13

6 7 8
13

NOSTUFF

R803
10K
5%

NOSTUFF

NOSTUFF
1

R832

R831
1K

5%
1/16W
MF
2 402

13

12

11

10

1K

5%
1/16W
MF
2 402

NOSTUFF
1

R830
1K

5%
1/16W
MF
2 402

NOSTUFF
1

R829

R827

1K

5%
1/16W
MF
2 402

20K

31 8 7 6 3

5%
1/16W
MF
2 402

31 8 7 6 3

R837DEVELOPMENT
180
5%
Q802
1/16W
2N3906

MF
2 402

R833

5%
1/16W
MF
2 402

SM
1

DEVELOPMENT

R838

LED801_1

NOSTUFF

DEVELOPMENT

R890

R8011

1K

4.7K

5%
1/16W
MF
2 402

VCC

U890

5%
1/16W
MF
402 2

SM

DELAY

NOSTUFF RESET

SMU_RESET_L 6

NOSTUFF
VOLTAGE DETECTOR
MC33465N_30ATR

0.01UF
10%

16V
CERM 2
402

R800

C891

10%
6.3V
2 CERM
402

TH

29

PLLLOCK 1

180

2 Q803_B

SM

C881

Q800

20%
16V
2 CERM
402

NOSTUFF

SDF803

DEVELOPMENT

Q800_G

OMIT

HSK-NUT-6.5MM

ZH804

6P15R5P4

HS_SDF803 1

HS_SDF804

SM

C883

0.01UF

DEVELOPMENT
3

R836
29 14 6

CHKSTOP_L 1

180

5%
1/16W
MF
402

C884

0.01UF

20%
16V
2 CERM
402

20%
16V
2 CERM
402

DEVELOPMENT

Q801

2N3904

Q801_B

SM
2

SIGNAL ALIAS

DEVELOPMENT

D810

2
27

NOTICE OF PROPRIETARY PROPERTY

CLOCK_ERROR_L

SHASTA JTAG PULL DOWN

25

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

JTAG_SB_TRST_L

THESE PINS HAVE INTERNAL PULLUPS


JTAG_SB_TCK
TP_JTAG_SB_TCK
MAKE_BASE=TRUE ALIAS
TP_JTAG_SB_TDI
JTAG_SB_TDI
MAKE_BASE=TRUE ALIAS
TP_JTAG_SB_TDO
JTAG_SB_TDO
ALIAS
MAKE_BASE=TRUE
TP_JTAG_SB_TMS
JTAG_SB_TMS
MAKE_BASE=TRUE ALIAS

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

25
25
25
25

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

R825

10K

SIZE

5%
1/16W
MF
2 402

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6482

D
SCALE

SM

5%
1/16W
MF
402

C882

0.01UF

20%
16V
2 CERM
402

TH

DEVELOPMENT
GREEN
2.0X1.25A

2N3904

5%
1/16W
MF
402

2N7002

LED802

Q803

TH

HS_SDF802

0.01UF

20%
16V
2 CERM
402

3
D

LED802_1
3

0.01UF

Q800_D

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

DEVELOPMENT

TH

HS_SDF801

C880

180

R835

LED801

R810
1

SDF802

HS_SDF800 1

RED

1uF

GND

DEVELOPMENT

13

NOSTUFF

SDF801

SM

R834

180

Q803_C

R839

330

ERROR_LED

NOSTUFF

C890 1

DEVELOPMENT

DEVELOPMENT
1

5%
1/16W
MF
2 402

NOSTUFF

SDF800

RED

DEVELOPMENT
1

1K
5%
1/16W
MF
2 402

NOSTUFF

CPU HEATSINK SMT NUTS


NOSTUFF

180
2

Q802_E

PULSAR ERROR_L LED

36

DEVELOPMENT

PP3V3_RUN

2 GND_SMU_AVSS_DAGND

HSK-NUT-6.5MM HSK-NUT-6.5MM HSK-NUT-6.5MM

=PP3V3_ALL_SMU

0.1uF
20%

=PP5V_RUN_CPU

SDF890

13 33 36

STDOFF-6MMOD1MMH-TH SDF891
STDOFF-6MMOD1MMH-TH
1

=PP5V_RUN_CPU

AIRPORT CARDGUIDE
SMT NUTS

C802

20%
10V
2 CERM
603

5%
1/16W
MF
402

CHKSTOP LED

SMU_MANUAL_RESET_L

2K PULLUP INSIDE P/S

R811

DEVELOPMENT

BACKUP SMU RESET CIRCUIT

POWER_GOOD IS A 5V DRIVEN
SIGNAL FROM POWER SUPPLY

1K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

36

0.47UF

DEVELOPMENT

8 7 6

4.7K

2 PPVREF_SMU_ADC_REF

R828

PLL LOCK LED

NOSTUFF
1

NOTE:PULL UP CPU_VID<5>TO
2.2V FOR CPU VRM10.

10V
CERM 2
402

R860

5%
1/16W
MF
402
1

1/16W
MF
2 402

C800

6 13

NOSTUFF

SYS_POWERFAIL_L
13

NOSTUFF

Q802_B

13 7 6

=PPVREF_SMU

R802

2.2UF

20%
10V
CERM 2
805

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

1%
1/16W
MF
2 402

J802 & R826 CAN MOVE TO DEVELOPMENT BOM POST RAMP

F-ST-SM
14

BM12B-SRSS-TB

NOSTUFF

J802_2 2

10K

430

GND_SMU_AVSS

5%
1/16W
MF
402

J803

518-0158

R807

10K

6 33

R824
1

6 33

1NOSTUFF

NOSTUFF

R813 1R812

NOSTUFF

R826

M-ST-TH

5%
1/16W
MF
2 402

POWER_GOOD

J802

HC17051

10K

CPU_VID_R<2>

200

CPU_VID_R<1>

5%
1/16W
MF
402

5%
1/16W
MF
402

R817

R822
1

R823
0

10K

13

5%
1/16W
MF
402

5%
1/16W
MF
402

CPU_VID<3>

R816

R820

5%
1/16W
MF
402

CPU_VID_R<0>

PP3V3_ALL

DOWNLOAD
CONNECTOR
PP3V3_ALL

R819
1

PP3V3_ALL_SMU_AVCC

13

10K

POWER_FAIL_L
CONNECTION

77

PP3V3_RUN

R814

CPU_VID<2>

13

49

SM

13

6 9 10 11 46 50

125
4 TSSOP

VID CONTROLLED BY SMU

CPU_VID<1>

CPU VID<0:5>

13

NB_PMR_OBSV

U700

2N3904

5%
1/16W
MF
402

CPU_VID<0>

F-ST-SM
3

8 25 74 77 87

24

SYS_SLOT_PWR

13

U.FL-R_SMT

SYS_WARM_RESET_L

125
10 TSSOP

13

PCI_AIRPORT_RESET_L
GPU_RESET_L
=PCI_ROM_RESET_L
=PCI_USB2_RESET_L

2 DIAG_LED_R

8 25 74 77 87

76

SM

1K

13 24

27

ALIAS

TP_SYS_SLOT_PWR
ALIAS
MAKE_BASE=TRUE
TP_SMU_PWRSEQ_P1_3
ALIAS
MAKE_BASE=TRUE
TP_SYS_DOOR_AJAR_L
ALIAS
MAKE_BASE=TRUE
TP_FAN_PWM8
ALIAS
MAKE_BASE=TRUE
TP_SYS_DRIVE_BAY_INT_L ALIAS
MAKE_BASE=TRUE
SMU_WARM_RESET_L
ALIAS
MAKE_BASE=TRUE

1
DIAG_LED
MAKE_BASE=TRUE

SYS_COLD_RESET_L
SYS_WARM_RESET_L

DIAG LED

R851

DIFFERENTIAL_PAIR

10 MIL SPACING
10 MIL SPACING

27

PCI_CLK_P1

ALIAS

NET_SPACING_TYPE

SMU_RESET
SMU_RESET

SMU

PP5V_ALL

27

PCI_CLK_P3
_PCI_CLK33M_AIRPORT

TP_PCI_CLK_P4
MAKE_BASE=TRUE
PCI_CLK33M_SB_EXT
MAKE_BASE=TRUE

74 27

ELECTRICAL_CONSTRAINT_SET

77

I246

PCI_CLK_GP1

ALIAS

27

PCI_CLK_GP0
=PCI_CLK33M_USB2

24

2.5V

RAM_CKE_R<2>

ALIAS

PCI_CLK33M_USB2
MAKE_BASE=TRUE

24

SSOT-23

ALIAS

2
3

NB_THMI
NB_THMO

ALIAS

VR801

TP_NB_THMI
MAKE_BASE=TRUE
TP_THMO
MAKE_BASE=TRUE
TP_RAM_CKE_R<2>
MAKE_BASE=TRUE
TP_RAM_CKE_R<3>
MAKE_BASE=TRUE
TP_RAM_CKE_R<6>
MAKE_BASE=TRUE
TP_RAM_CKE_R<7>
MAKE_BASE=TRUE
TP_RAM_MUXEN0
MAKE_BASE=TRUE
TP_RAM_MUXEN4
MAKE_BASE=TRUE
TP_RAM_CS_L_R<2>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<3>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<10>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<11>
MAKE_BASE=TRUE

OF

C
103

2.5V VOLTAGE REGULATOR


NOTE:
SET OUTPUT=2.62V FOR FRAMEBUFFER.
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R903+R905)/R905=2.62VDC

PP5V_PWRON
PP5V_PWRON

D900
2

1
1

MBR0520L
SM

R900

U900_VC_R

C904

1UF

20%
2 25V
CERM
805

VCC

VC

IRU3037CS
SOI
8

U900_COMP

HD

LD

U900_GATE_H

SS
U900_GATE_L

Q901
1

Q901_GATE

NTD70N03R

G
S

5%
1/10W
FF
805

CASE369

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

U900_FEEDBACK

C915

0.47UF

20%
2 10V
CERM
603

R901_P2
1

C914
3900PF

C
PP2V5_PWRON

20%
2 10V
CERM
603

Q903

IRF7410

L901
1

SO-8

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

Q902

C913
56PF

C906

5%
2 25V
CERM
402

5%
50V
2 CERM
603

NOSTUFF

220PF

5%
2 50V
CERM
402

NTD70N03R

C905

10%
50V
2 CERM
603

5%
1/8W
FF
2 1206

C907
3300PF

10%
50V
2 CERM
603

7
6
5

R903

11K

1%
1/16W
MF
2 402

CASE369

C908

1800UF

NOSTUFF

C912
1

R905

20%
25V
2 CERM
1206

1UF

R904_P2
1

0.022UF

NOSTUFF

1.1K

8
3
2

TH

R904

PP2V5_RUN

CRITICAL

1.6UH

390UF

1UF

NOSTUFF
1

PEAK CURRENT OF TOTAL RAILS


12.68A WITH DIMM TERMINATION
9.24A WITHOUT DIMM TERMINATION

C903

20%
2 6.3V
ELEC
8X11.5-TH

C917

Q902_DRAIN

4
1

GND

27.4K
1%
1/16W
MF
2 402

20%
2 6.3V
ELEC
8X11.5-TH

FB

390UF

R902

C902

COMP

R901

20%
2 6.3V
CERM
1206

U900_VC_D

C916
1UF

U900

U900_SS

MBR0520L
SM

C901
10UF

D901

U900_VC

20%
25V
2 CERM
805

SM

5%
1/10W
FF
2 805

CRITICAL

D902
MBR0520L

4.7

20%
2 6.3V
ELEC
TH-KZJ

LOW TO ENABLE

C909

1800UF

20%
2 6.3V
ELEC
TH-KZJ

10K
1%
1/16W
MF
2 402

SYS_SLEEP

6 8 10 11 46 50

U900_FEEDBACK

2.5V VREG
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

OF

C
103

SHASTA CORE VOLTAGE REGULATOR


D

D
PP5V_ALL

PP5V_ALL

NOTE:
SET OUTPUT=1.2V
IRU3037ACS VREF=0.8VDC
VOUT=VREF*(R1003+R1005)/R1005=1.206VDC

D1000
2

1
1

MBR0520L
SM

R1002

VCC
SOI

100K

TURN_ON_SHASTA_CORE_L

NOSTUFF

Q1000

R1010

2N7002

Q1000_G

5%
1/16W
MF
402

C1015
0.1UF

COMP

HD

U1000_GATE_H

LD

U1000_GATE_L

FB

Q1001
Q1001_GATE

NTD60N02R

1
G

5%
1/10W
FF
805

CASE369

S 3

C1017
1UF

20%
10V
2 CERM
603

L1001

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL Q1002_DRAIN

MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=15MIL

R1004

Q1002

C1013

C1006
220PF

5%
25V
2 CERM
402

C1005

5%
1/8W
FF
2 1206

10%
50V
2 CERM
603

=PPVCORE_PWRON_SB

23

1
C1007 R1003
5.11K

3300PF

10%
50V
2 CERM
603

1%
1/16W
MF
2 402
1

R1004_P2

CASE369

C1008
1800UF

NOSTUFF
1

0.022UF

5%
2 50V
CERM
603

NTD70N03R

G
S

NOSTUFF

3 6 10

NOSTUFF
1

1.1K

PPVCORE_PWRON_SB

TH

U1000_FEEDBACK

5%
50V
2 CERM
603

C1014

NOSTUFF

68PF

3900PF

PEAK CURRENT OF TOTAL RAILS


5.96A

20%
2 6.3V
ELEC
8X11.5-TH

1.6UH

4
1

C1003
390UF

20%
2 6.3V
ELEC
8X11.5-TH

D 4

GND

1%
1/16W
MF
2 402
R1001_P2

20%
16V
2 CERM
603

SM

R1011
0

27.4K

SS

U1000_COMP

R1001

SYS_POWERUP_L

U1000_SS

5%
1/16W
MF
402 2

33 13 11 10 7 6

IRU3037ACS

R10071

C1000
1UF
20%
R1000
25V

2 CERM
805

VC

U1000

PP3V3_ALL

U1000_VC_D

390UF

20%
2 6.3V
CERM
1206

MBR0520L
SM
1

1UF

20%
25V
2 CERM
805

C1001 1 C1002
10UF

D1001
U1000_VC_R

U1000_VC

C1004

SM

5%
1/10W
FF
2 805

D1002
MBR0520L

4.7

C1012
1UF

R1005

20%
25V
2 CERM
1206

20%
2 6.3V
ELEC
TH-KZJ

C1009

1800UF

20%
2 6.3V
ELEC
TH-KZJ

10K

1%
1/16W
MF
2 402

5%
1/16W
MF
402-1

U1000_FEEDBACK

PP1V2_PWRON FET SWITCH

PP1V2_RUN FET SWITCH

PEAK CURRENT 0.6A

PEAK CURRENT 4.43A

10 6 3

PP1V2_PWRON

PPVCORE_PWRON_SB

10 6 3

PP1V2_RUN

Q1003

PPVCORE_PWRON_SB

SI9426DY

SI3446DV

PP5V_ALL

PP5V_ALL

RDSON=0.06 OHM
@ VGS=2.5 V

RDSON=0.016 OHM
@ VGS=2.5 V
4

TSOP

1 2

I70

5 6

Q1006
PP3V3_ALL

7 8

SOI

R1008
2

R1009
100K 1
2

R10141
5%
1/16W
MF
402 2
3

5%
1/16W
MF
402

Q1006_G

5%
1/16W
MF
402

100K

TURN_ON_PP1V2_L

NOSTUFF

2N7002DW

Q1005

Q1005_G

Q1004
D

2N7002DW

SOT-363
5

SM

SOT-363

2N7002

5%
1/16W
MF
402

Q1004

3
D

R1012

100K 1 Q1003_G

SYS_SLEEP

6 8 9 11 46 50

R1013
33 13 11 10 7 6

SYS_POWERUP_L

5%
1/16W
MF
402-1

1.2V VREG
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

10

OF

C
103

11 7 6

PP5V_ALL

D
CRITICAL

Q1100

SI4467DY
18 6

PP5V_PWRON

SM-1

PP5V_RUN

6 18

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP5V_PWRON

3
7

2
1

90 59 11 7

R1100
R1104

33 13 10 7 6

50 46 10 9 8 6

SYS_POWERUP_L

SYS_SLEEP

5%
1/16W
MF
402

100K 2

LM339A
V+

5%
1/16W
MF
402
RAIL_CTL_POS

PP3V3_RUN

Q1102

1%
1/16W
MF
2 402

SI4467DY
3
7

13

GND

RAIL_RUN_FET
MIN_LINE_WIDTH=20MIL

FET ON IN RUN
4

U1100

RAIL_CTL_NEG
5

GND
12

R11021

LM339A
V+

FET ON IN SLEEP

SOI
2

RAIL_SLEEP_FET
MIN_LINE_WIDTH=20MIL

1%
1/16W
MF
603 2

SM-1

6
7
8

FET ON IN SLEEP

PP5V_ALL

SI4467DY

CRITICAL
4

1
11 7 6

Q1103

47.0K

MIN_NECK_WIDTH=10MIL
RUN -> FLOAT
SLEEP -> LOW
SHUTDOWN -> FLOAT

RUN -> LOW


SLEEP -> FLOAT
SHUTDOWN -> FLOAT

3
4

6 18 27

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

MIN_NECK_WIDTH=10MIL

12

PP3V3_PWRON

SM-1
8

SOI

U1100
11

18 6

1K

1%
1/16W
MF
2 402

CRITICAL

10

100K 2

1K

R1103

5%
1/16W
MF
402

R1107 1R1101

FET ON IN RUN

100K 2
1

PP3V3_ALL

Q1101

P-CHANNEL
Ron=11mOhm

SI4467DY
SM-1

G
S

5
6

3
8

PP3V3_ALL

7 11 59 90

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

P-CHANNEL
Ron=11mOhm

CRITICAL

PROCESS SWING
3.30V - 3.45V

SENSE

VR1100

Vpwr >= Vout+0.35V

Vctrl >= Vout+1.25V

CS5253
SM
VPWR VOUT
VCTRL VOUT
TAB
ADJ

Vout=Vref(1+R2/R1)+Iadj(R2)

R1105
124

R1

2
3_3V_ALL_ADJ
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

C1102
100UF

20%
2 6.3V
ELEC
SM

Vref=1.250V typ
Iadj=50uA typ

1
6

C1101
0.1UF

N20P80%
16V
2 CERM
603

1%
1/16W
MF
2 603

C1100
150UF

20%
2 10V
ELEC
SM

R1106
210

R2

1%
1/16W
MF
2 603

5V & 3.3V VREGS


A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

11

OF

C
103

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

SMU_CLK10M_XTAL

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

SMU_CLK10M_XIN
SMU_CLK10M_XOUT
SMU_CLK10M_XOUT_R

15 MIL SPACING
15 MIL SPACING

RTC_CLK32K_X1
RTC_CLK32K_X2

Real Time Clock

13
13
7

13

13 8 7 6

System Management Unit

13

C1308 1

0.1uF

R1315

=PP3V3_ALL_SMU

13 8 7 6

Power aliases required by this page:


- _PP3V3_ALL_SMU
- _PP3V3_ALL_RTC
- _PP3V3_PWRON_SMU
- _PPVREF_SMU (SMU AVCC or 2.5V reference)

C1300 1
10uF

20%
6.3V
CERM 2
805

C1301 1

C1302 1

0.1uF

0.1uF

20%
10V
CERM 2
402

4.7

5%
1/16W
MF
402

Y = Primary function
N = Alternate function
(see aliases below)
S = Spare

NOTE: CPU current/voltage monitoring


(CPU_SENSE_I/CPU_SENSE_V) requires
100K/10uF RC filter at SMU pins.
Caps should connect to GND_SMU_AVSS.
SMU_VREF should be same signal or
reference used by monitoring
circuit, but be aware that this will
affect other analog inputs such as
AC adapter ID.

33
33
36
30
13
13
13
8

NOTE: All analog inputs to SMU should have


a 100pF capacitor to the SMU AVSS
signal (GND_SMU_AVSS). None of
those capacitors are provided on
this page.

3
3
3
8

NOTE: Some primary and alternate functions


reuire pull-ups that are not.
provided on this page. Please.
review the latest SMU specification
to ensure missing pull-ups are
provided on another page.

3
13 8 6
13 8
13 8

18
18

NOTE: Pinout matches SMU pinout v1.51.

16
16
17
13
13
13

18
18 14 6

NO_SMU_I2C_D

18

R1399
25

13 8 7 6

SMU_TO_SB_INT_L

18 14 6

18

5%
1/16W
MF
402

=PP3V3_ALL_SMU

18
13
27 25 16

13

78

VCC

M30280F8

SOT23

SDA
SCL
TA1out
TA1in
TA2out
TA2in
TA3out
TA3in

P7[0] 27
P7[1] 26
P7[2] 25
P7[3] 24
P7[4] 23
P7[5] 22
P7[6] 21
P7[7] 20

Y
Y
Y
Y
Y
Y
N
Y

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
N
Y
N
Y
Y
Y

Y
Y
N
Y
N
Y
Y
Y

I2C_SMU_B_SDA
I2C_SMU_B_SCL
I2C_SMU_CPU_SDA_IN
FAN_RPM0
I2C_SMU_CPU_SCL_IN
FAN_RPM1
FAN_PWM8
FAN_RPM2

SDAmm
SCLmm
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7

TA4out
TA4in
INT0*
INT1*
INT2*
NMI*
CE*

P8[0] 19
P8[1] 18
P8[2] 17
P8[3] 16
P8[4] 15
P8[5] 14
P8[6] 8
P8[7] 7

Y
Y
Y
S
Y
Y
Y
Y

Y
Y
Y
S
Y
Y
Y
Y

Y
Y
Y
S
Y
Y
Y
Y

Y
Y
Y
S
Y
S
Y
Y

Y
Y
Y
S
Y
S
Y
Y

SYS_LED
SYS_COLD_RESET_L
SYS_PME_L
SMU_QREQ
SYS_SLEWING_L
I2C_SMU_CPU_SDA_OUT_L
SYS_POWERUP_L
MAKE_BASE=TRUE
SMU_SLEEP

P3[0] CLK3
P3[1] Sin3
P3[2] Sout3
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]

TB0in
TB1in
TB2in
AN24
AN25
AN26
AN27

P9[0] 5
P9[1] 4
P9[2] 3
P9[3] 2
P9[5] 1
P9[6] 80
P9[7] 79

Y
Y
Y
Y
Y
Y
S

Y
Y
Y
Y
Y
Y
S

Y
Y
Y
Y
Y
Y
Y

Y
S
Y
Y
Y
Y
Y

Y
S
Y
Y
Y
Y
S

CLOCK_RESET_L
CPU_HRESET
SB_TO_SMU_INT_L
SB_STOPXTALS_L
SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P9_6
SYS_SLOT_PWR

AN0 P10[0] 76
AN1 P10[1] 74
AN2 P10[2] 73
AN3 P10[3] 72
KI0* P10[4] 71
KI1* P10[5] 70
KI2* P10[6] 69
KI3* P10[7] 68

S
Y
Y
Y
Y
Y
Y
Y

S
Y
Y
Y
Y
Y
Y
Y

S
Y
Y
Y
Y
Y
Y
Y

S
Y
Y
Y
Y
Y
Y
S

S
Y
Y
Y
Y
Y
Y
S

TP_SMU_SPARE_P10_0
SMU_WARM_RESET_L
NB_SUSPENDACK_L
SB_SUSPENDACK_L
SMU_SUSPENDREQ_L
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
I2C_SMU_CPU_SCL_OUT_L

P0[0]
P0[1]
P0[2]
P0[3]
P0[4]
P0[5]
P0[6]
P0[7]

AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07

SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_4
SYS_POWERFAIL_L
SYS_DRIVE_BAY_INT_L
SYS_DOOR_AJAR_L

Y
Y
Y
Y
Y
N
N
N

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
Y
Y
Y
Y
Y
Y

59
58
57
56
55
54
53
52

P1[0]
P1[1]
P1[2]
P1[3]
P1[4]
P1[5]
P1[6]
P1[7]

AN20
AN21
AN22
AN23

I2C_SMU_E_SDA
I2C_SMU_E_SCL
FAN_TACH0
FAN_TACH1
FAN_TACH2
FAN_TACH3
FAN_TACH4
FAN_TACH5

Y
Y
Y
Y
Y
S
S
S

Y
Y
Y
Y
Y
N
N
N

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
Y
Y

51
50
49
48
47
46
45
44

P2[0]
P2[1]
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
P2[7]

I2C_SMU_A_SDA_IN
I2C_SMU_A_SDA_OUT_L
I2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT_L
I2C_SMU_D_SDA
I2C_SMU_D_SCL
SMU_CHARGE_BATT
SYS_OVERTEMP_L

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
S

39
38
37
36
35
34
33
32

QFP-80
OMIT

INT3*
INT4*
INT5*

5%
1/16W
MF
2 402

13

C1310

13

=PPVREF_SMU

6
9
10
12
77

SMU_BOOT_CNVSS
SMU_RESET_L
SMU_CLK10M_XOUT_R
SMU_CLK10M_XIN

0.22uF

20%
6.3V 2
CERM
402

13

20%
2 10V
CERM
402

8 13
8 13
8 13
8
8
8
8
8

18
18
13 18
16
13 18
16

SMU Pull-ups / pull-down


=PP3V3_ALL_SMU

6 7 8 13

8 13

R1300

17

1
21

13 25 77

28

10K

5%
1/16W
MF
402

13 25 27 33
18

10K

5%
1/16W
MF
402

R1302

8 13 24

SYS_POWERUP_L

6 7 10 11 13 33

SYS_POWER_BUTTON_L

6 7 13

SYS_RESET_BUTTON_L

7 13

R1303
1

6 7 10 11 13 33

10K

5%
1/16W
MF
402

8 13

27
30
25

PP3V3_PWRON

R1304

25
3

10K

SYS_PME_L

13 25 77

SYS_SLEWING_L

13 25 27 33

SMU_SUSPENDREQ_L

13 24 25 28

SYS_COLD_RESET_L

8 13 24

SMU_SLEEP

8 13

5%
1/16W
MF
402

PCNVSS
RESET*
XOUT
XIN
VREF

R1312
1

R13251

R1316

R13171
0

5%
1/16W
MF
402 2

SMU_CLK10M_XOUT

C1304

18pF

10M

10K

5%
1/16W
MF
402 2

5%
1/16W
MF
402

C1325
1uF

VSS

25
13 24 25 28

11

100K 2
1

R1310

10.0000M
1
2
Keep crystal subcircuit close to SMU.
8X4.5MM-SM

C1305

5%
1/16W
MF
402

CRITICAL

Y1300

2K

5%
1/16W
MF
402

R1313

5%
1/16W
MF
2 402

XW1300
SM
1

18

10K

R1311

7 13

R1327

75

10%
6.3V
2 CERM
402

NO STUFF

PP2V5_PWRON

6 7 13

AVSS

2K

5%
1/16W
MF
402

NO STUFF

13

RTC_CLK32K_X2

C1309

PP3V3_RUN

8 6

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
SMU_BOOT_RXD
SMU_BOOT_TXD

67
66
65
64
63
62
61
60

SM-1

N
N
N
S
S
S
Y
Y

S
S
S
S
Y
Y
Y
Y

Y1301

32.768K
4

N
N
N
S
S
S
Y
Y

S
S
S
S
Y
Y
Y
Y

1
2

0.1uF

SMU_BOOT_BUSY
SMU_BOOT_SCLK
SMU_BOOT_CE

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
Y
Y

X1
X2
SCL
SQW/ VBAT
OUT GND

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
S
S
S
Y

SDA

13

CRITICAL

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
N
N
N
Y

150K

MSOP

8 13 33 36

RTS0*/
CTS0* P6[0] 43
CLK0 P6[1] 42
RXD0 P6[2] 41
TXD0 P6[3] 40
RTS1*
(BUSY) P6[4] 31
CLK1 P6[5] 30
RXD1 P6[6] 29
TXD1 P6[7] 28

CPU_SENSE_I
CPU_SENSE_V
CPU_TEMP
CPU_BYPASS
FAN_RPM3
FAN_RPM4
FAN_RPM5
SMU_ONEWIRE

R1322

D1310
1N914

AVCC

U1300

1
3

I2C_RTC_SCL
NC

Portable
Consumer
Entry Desktop
Desktop
Server

BOM options provided by this page:


(NONE)

I2C_RTC_SDA

18

10%
6.3V
2 CERM
402

RTC_CLK32K_X1

U1301
DS1338

18

C1303
1uF

20%
10V
CERM 2
402

VCC

20%
10V
CERM 2
402

PP3V3_ALL_SMU_AVCC 8
VOLTAGE=3.3V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil

GND_SMU_AVSS

Signal aliases required by this page:


(NONE)

=PP3V3_ALL_RTC
=PP3V3_ALL_SMU

13

Page Notes
D

DIFFERENTIAL_PAIR

Portable
Consumer
Entry Desktop
Desktop
Server

RTC_CLK32K_XTAL

GND_SMU_AVSS 8 13 33 36
VOLTAGE=0V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil

100K 2
5%
1/16W
MF
402

Y1300s load capacitance is 12pF


1

18pF

5%
50V
CERM 2
402

5%
50V
CERM 2
402

Master: Link

System Management Unit

Alternate Functions

NOTICE OF PROPRIETARY PROPERTY

Portable
13
13
13
13 8 6
13 8
13 8
13 8

FAN_RPM3
FAN_RPM4
FAN_RPM5
SYS_POWERFAIL_L
SYS_DRIVE_BAY_INT_L
SYS_DOOR_AJAR_L
FAN_PWM8

Port
0.4
0.5
0.6
1.5
1.6
1.7
7.6

ALS0_OUT
ALS1_OUT
ALS_GAIN_BOOST
SMU_ACIN
SMU_BATT_DET_L
SYS_LID_OPEN
SYS_KBDLED

Consumer
8

13

13

13
13

FAN_TACH3
FAN_TACH4
FAN_TACH5
SMU_CHARGE_BATT

Port
2.5
2.6
2.7
3.6

SYS_LED_RED
SYS_LED_GREEN
SYS_LED_BLUE
DIAG_LED

Tower & Server


21

13 8

21

13 8

21

13 8

18 13
18 13

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
I2C_SMU_CPU_SDA_IN
I2C_SMU_CPU_SCL_IN

Port
6.0
6.1
6.2
7.2
7.4

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

FAN_TACH6
FAN_TACH7
FAN_TACH8
FAN_PWM6
FAN_PWM7

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482
OF

13
1

103

DEVELOPMENT

R1400
27

EI_CPU1_CLK_P_R

5%
MF

EI_CPU1_CLK_P

6 14 27

EI_CPU1_CLK_N

6 14 27

1/16W
402

DEVELOPMENT

R1401

27

EI_CPU1_CLK_N_R

1
5%
MF

D
27

CPU1_HTBEN_R

2
1/16W
402

DEVELOPMENT
0 R1402
1

CPU1_HTBEN

6 14

EI_CPU1_SYNC

6 14 27

5% 402

27

EI_CPU1_SYNC_R

DEVELOPMENT
0 R1403
1

5% 402

=PP1V2_EI_CPU 7

18 29 30 31 35

28 18 14 7

NOSTUFF

=PP1V2_EI_NB 7

J1400

=PP1V2_EI_NB

14 18 28

YFS-30-03-H-08-SB
F-ST-BGA
27 14 6
29 8 6

H1

EI_CPU1_SYNC
CHKSTOP_L

H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12

H13
H14
H15
H16
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
30 29 6
30 29 28 6

H17

EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<15>
EI_NB_TO_CPU_AD<17>
EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<40>
EI_NB_TO_CPU_AD<10>
EI_NB_TO_CPU_AD<39>
EI_NB_TO_CPU_AD<36>
RI_L
EI_QREQ_L

H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30

H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30

G1 G1
G2 G2
G3 G3 NC
G4 G4
G5 G5
G6 G6
G7 G7
G8 G8
G9 G9
G10 G10
G11 G11
G12 G12 NC
G13 G13
G14 G14
G15 G15
G16 G16
G17 G17
G18 G18
G19 G19
G20 G20
G21 G21
G22 G22
G23 G23
G24 G24
G25 G25
G26 G26
G27 G27
G28 G28
G29 G29
G30 G30

EI_CPU1_CLK_P

6 14 27

14 6
27

EI_CPU1_CLK_N

F1
F2
F3
F4

EI_CPU_TO_NB_AD<3> 6 28 29
EI_CPU_TO_NB_AD<4> 6 28 29
EI_CPU_TO_NB_AD<7> 6 28 29
EI_CPU_TO_NB_AD<11> 6 28 29
EI_CPU_TO_NB_CLK_N 6 28 29
EI_CPU_TO_NB_CLK_P 6 28 29
EI_CPU_TO_NB_SR_N<1> 6 28 29
EI_CPU_TO_NB_SR_P<1> 6 28 29

F5
F6
F7
F8
F9
F10
F11
F12

EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<28>
EI_NB_TO_CPU_AD<14>
EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<18>
EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<26>
EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_AD<41>

6 28 29

F13

6 28 29

F14
F15

6 28 29

F16

6 28 29
6 28 29 28 6
29
6 28 29

EI_NB_TO_CPU_AD<5>

F17
F18

6 28 29

F19

6 28 29

F20

6 28 29

F21

6 28 29

F22

6 28 29

F23

6 28 29

F24

6 28 29

F25
F26
F27

EI_NB_TO_CPU_SR_N<0> 6 28 29
29
EI_NB_TO_CPU_SR_P<0> 6 28 29
29
I2C_SMU_A_SCL_OUT_L 6 13 18

28 6
28 6
28 6
29

EI_NB_TO_CPU_AD<37>
EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_SR_P<1>

F28
F29
F30

F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30

E1 E1
E2 E2
E3 E3
E4 E4
E5 E5
E6 E6
E7 E7
E8 E8 NC
E9 E9
E10 E10
E11 E11
E12 E12
E13 E13
E14 E14
E15 E15
E16 E16
E17 E17
E18 E18
E19 E19
E20 E20
E21 E21
E22 E22
E23 E23
E24 E24
E25 E25
E26 E26
E27 E27
E28 E28
E29 E29
E30 E30

30 29 25 6

D1

CPU_INT_L

D2
D3
D4
D5
D6

EI_CPU_TO_NB_AD<8> 6 28 29
EI_CPU_TO_NB_AD<13> 6 28 29

D7
D8

EI_CPU_TO_NB_AD<12> 6 28 29
EI_CPU_TO_NB_AD<5> 6 28 29
EI_CPU_TO_NB_AD<36> 6 28 29
EI_CPU_TO_NB_AD<35> 6 28 29
EI_CPU_TO_NB_AD<18> 6 28 29
EI_CPU_TO_NB_AD<43> 6 28 29
EI_CPU_TO_NB_AD<42> 6 28 29
EI_CPU_TO_NB_AD<38> 6 28 29
EI_CPU_TO_NB_AD<40> 6 28 29
EI_NB_TO_CPU_AD<9> 6 28 29
EI_NB_TO_CPU_AD<11> 6 28 29
EI_NB_TO_CPU_AD<0> 6 28 29
EI_NB_TO_CPU_AD<1> 6 28 29

D9
D10
D11
D12
D13
D14
D15
D16
28 6
29

EI_CPU_TO_NB_AD<15>

D17
D18
D19
D20
D21
D22

EI_NB_TO_CPU_AD<22> 6 28 29
EI_NB_TO_CPU_AD<33> 6 28 29
EI_NB_TO_CPU_AD<43> 6 28 29
EI_NB_TO_CPU_AD<2> 6 28 29
29
EI_NB_TO_CPU_AD<38> 6 28 29
29
SYNCENABLE 6 29 30
TP_PROC_TRIGGER_OUT 6 29 29

D23
D24
D25
28 6

D26

28 6

D27

28

D28

28

29 28

EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<24>
6 EI_NB_TO_CPU_AD<7>
29
6 EI_NB_TO_CPU_AD<6>
6 EI_QACK_L

D29
D30

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30

C1 C1
C2 C2
C3 C3
C4 C4
C5 C5
C6 C6
C7 C7
C8 C8
C9 C9
C10 C10
C11 C11
C12 C12
C13 C13
C14 C14
C15 C15
C16 C16
C17 C17
C18 C18
C19 C19
C20 C20
C21 C21
C22 C22
C23 C23
C24 C24
C25 C25
C26 C26
C27 C27
C28 C28
C29 C29
C30 C30

B1
B2
B3
B4
B5

EI_CPU_TO_NB_AD<6> 6 28 29
EI_CPU_TO_NB_AD<21> 6 28 29
EI_CPU_TO_NB_AD<20> 6 28 29
EI_CPU_TO_NB_AD<25> 6 28 29
EI_CPU_TO_NB_AD<26> 6 28 29
EI_CPU_TO_NB_SR_P<0> 6 28 29
EI_CPU_TO_NB_SR_N<0> 6 28 29
EI_CPU_TO_NB_AD<27> 6 28 29
EI_CPU_TO_NB_AD<23> 6 28 29
EI_CPU_TO_NB_AD<39> 6 28 29
EI_CPU_TO_NB_AD<16> 6 28 29
EI_CPU_TO_NB_AD<19> 6 28 29 28

B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16

29 28 6

EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<16>

29 28 6

EI_NB_TO_CPU_AD<35>

6
29

29 28 6

B17
B18
B19
B20
B21
B22

29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6

EI_SE

6 28 29
30

29 6

18 13 6

EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<32>
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_CLK_P
MCP_L
I2C_SMU_A_SDA_OUT_L

B23
B24
B25
B26
B27
B28
B29
B30

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30

A1 A1
A2 A2
A3 A3
A4 A4
A5 A5
A6 A6
A7 A7
A8 A8
A9 A9
A10 A10
A11 A11
A12 A12
A13 A13
A14 A14
A15 A15
A16 A16
A17 A17
A18 A18
A19 A19
A20 A20
A21 A21
A22 A22
A23 A23
A24 A24
A25 A25
A26 A26
A27 A27
A28 A28
A29 A29
A30 A30

CPU_HRESET_L
CPU1_HTBEN
EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<29>

6 29 30
6 14
6 28 29
6 28 29

6 28 29
6 28 29
6 28 29
6 28 29
6 28 29
6 28 29

6 28 29
6 28 29
6 28 29
6 28 29
6 28 29
6 28 29

CPU LOGIC ANALYZER

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

14

OF

C
103

OPTICAL TEMP SENSOR

FAN 1 - Q37 STYLE CPU FAN CONTROL CIRCUIT

PP3V3_PWRON

CPU FAN 2

PP12V_RUN

R1645
1

R1640

1
C1614
10UF

10K

1%
1/16W
MF
2 402

R1641
100K

R1642
100K

1%
1/16W
MF
402

1%
1/16W
MF
402

R1605
13

FAN_RPM0

Q1600
2N7002

FAN_0_CNTL

5%
1/16W
MF
402

R1639
10K
1%

SM

1/16W
MF
2 402

NOSTUFF

4.7K

C1619
47UF

5%
1/16W
MF
402 2

100PF
1

U1700

20%
16V 2
ELEC
SM

1N914
3

FAN_0_GT

R1601

R1603
0

10K

PP3V3_RUN

C1616

FAN_TACH0

C1617 1

4700PF
1

10UF

10%
50V
CERM
603

C1618

D1605
SM

10UF

10%
16V
CERM 2
1210

2 SYS_OVERTEMP_L

13 16 25 27

MBR0530

10%

2 16V
CERM

1210

POWER SUPPLY TEMP SENSOR


17" SYSTEM FAN 603-5518

PP3V3_PWRON

20" SYSTEM FAN 603-5521

1%
1/16W
MF
2 402

SCL
GND

MOTOR CONTROL
TACH
GND
12V DC

2 CRITICAL

10K

13

5%
1/16W
MF
402

M-ST-TH
1

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

R1604

R1606
0

TEMP_SENSOR_OS 1

CRITICAL

18

I2C_OPTICAL_SCL

OS

HF28040-B

FAN_0_PWR

1%
1/16W
MF
402 2

5%
1/16W
MF
2 402

J1600

MAX FAN CURRENT=0.5A

10K 2

1%
1/16W
MF
402

NOSTUFF
1

I2C_OPTICAL_SDA

SM

R1643

5%
1/16W
MF
402

R1621

CRITICAL

SDA

18

IRF5505

SOT23

FAN_0_OPP

D
NOSTUFF

Q1601

10%
2 16V
CERM
1210

LM75

A0
A1
A2

R1600
0

C1600
10UF

NOSTUFF

D1604

LM358-SOI1
7

FAN_0_GATE

5%
50V
CERM
402

CRITICAL
8

0.1UF

20%
2 16V
CERM
603

R16441

C1615
FAN_0_OPM

U1602
SOP

I2C ADDR:90(1001000)

C1601

20%
2 16V
CERM
805

C1613

VS+

5%
1/16W
MF
402

0.47UF

20%
16V 2
ELEC
SM

FAN_0_DRV_F

FAN_0_DRV

8 NOSTUFF

4.7 2

PP12V_FAN_0_ANALOG
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

FAN_0_TACH

NOSTUFF

VS+

U1650
SOP

I2C ADDR:94(1001010)

5%
1/16W
MF
402

7
6
5

A0
A1
A2

LM75

NOSTUFF

R1650

CRITICAL

18

I2C_PS_TEMP_SDA

SDA

18

I2C_PS_TEMP_SCL

SCL
GND

OS

PS_SENSOR_OS

2 SYS_OVERTEMP_L

13 16 25 27

5%
1/16W
MF
402

FAN 2 - Q37 STYLE CPU FAN CONTROL CIRCUIT


PP12V_RUN

SYSTEM FAN 1
R1611
U1601_UNUSED

PP3V3_RUN

U1601

R1616

LM358-SOI1

1%
1/16W
MF
2 402

R1615
1

FAN_1_DRV

FAN_RPM1

Q1602

R1620

2N7002

FAN_1_CNTL

5%
1/16W
MF
402

10K
1%

SM

1/16W
MF
2 402

0.47UF

C1611

1
C1604
47UF

5%
1/16W
MF
402 2

CRITICAL
8

U1601
1

20%
16V 2
ELEC
SM

C1603

FAN_1_GT

SM

CRITICAL

J1601

D
MAX FAN CURRENT=0.5A

5%
1/16W
MF
402

NOSTUFF

R16171

R1618
0

10K

5%
1/16W
MF
2 402

PP3V3_RUN

20%
16V
CERM 2
402

10%
2 16V
CERM
1210

IRF5505

SOT23

FAN_1_OPP

0.01UF

10UF

Q1603

R1613
10K
1

FAN_1_PWR

C1608
4700PF
1

1%
1/16W
MF
402 2

10%
50V
CERM
603

L1600

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

C1607 1
10UF

10%
16V
CERM 2
1210

C1606

M-ST-TH

D1601
SM
MBR0530
1

MOTOR CONTROL

TACH

L1601

PP12V_RUN_FAN_1_LCL
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
GND

FERR-EMI-100-OHM
1

FAN_1_PWR_FILT

SM

2 CRITICAL

10UF

10%
2 16V
CERM
1210

10-89-7062

FERR-EMI-100-OHM

1%
1/16W
MF
402

2
SM

1N914

NOSTUFF

D1602

R1619
0

L1603

FERR-EMI-100-OHM
PP12V_RUN_FAN_1_LC
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

FAN_1_GATE

5%
50V
CERM
402

LM358-SOI1

20%
603

NOSTUFF

4.7K

100PF
FAN_1_OPM

0.1UF

2 16V
CERM

R1610

C1605

100K 2

C1602 1

20%
2 16V
CERM
805

1%
1/16W
MF
402

1
SM

5%
1/16W
MF
402

C1609

R1614

100K 2
1%
1/16W
MF
402

R1635
0

20%
16V 2
ELEC
SM

FAN_1_DRV_F

13

C1610
10UF

10K

L1602

FERR-EMI-100-OHM

4.7 2

PP12V_FAN_1_ANALOG
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

FAN_1_TACH_FILT

SM

L1604

FAN 1, 2 & SYSTEM TEMP

FERR-EMI-100-OHM

R1623
10K

R1636
13

FAN_TACH1

2
SM

1%
1/16W
MF
2 402

FAN_1_GND_FILT
VOLTAGE=0V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20" HD FAN 603-5487

FAN_1_TACH

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

5%
1/16W
MF
402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

REV.

051-6482 C
16 103
SHT

NONE

NOTICE OF PROPRIETARY PROPERTY

17" CPU FAN 603-5519

OF

FAN 3 - Q37 STYLE SYSTEM FAN CONTROL CIRCUIT


PP12V_RUN

R1745
1

R1740

1
C1714
10UF

10K

1%
1/16W
MF
2 402

R1705
13

FAN_RPM2

Q1700
2N7002

FAN_2_CNTL

5%
1/16W
MF
402

R1742
100K

1%
1/16W
MF
402

1%
1/16W
MF
402

R1739

C1701

603

1
C1719
47UF
20%
16V 2
ELEC
SM

C1715
100PF
1

CRITICAL
8

U1700

5%
50V
CERM
402

FAN_2_GT

IRF5505

SM

SOT23

CRITICAL

J1700

D
MAX FAN CURRENT=0.5A

R1743
1%
1/16W
MF
402

NOSTUFF

R17011

R1703
0

10K

PP3V3_RUN

M-ST-TH

MIN_LINE_WIDTH=20MIL

C1716
4700PF
2

10%
50V
CERM
603

MIN_NECK_WIDTH=10MIL

C1717 1
10UF

10%
16V
CERM 2
1210

C1718
10UF
10%

2 16V
CERM
1210

+12V DC

FAN_2_PWR

1%
1/16W
MF
402 2

5%
1/16W
MF
2 402

10-89-7062

MOTOR CONTROL

10K 2
1

FAN_2_OPP

5%
1/16W
MF
402

10%
2 16V
CERM
1210

Q1701

10UF

1N914

R1700
1

C1700

D1704

NOSTUFF

FAN_2_GATE

LM358-SOI1
1

NOSTUFF

4.7K

5%
1/16W
MF
402 2

FAN_2_OPM

20%

2 16V
CERM

R17441

20%
2 16V
CERM
805

C1713

5%
1/16W
MF
402

0.47UF

0.1UF

1/16W
MF
2 402

10K
1%

SM

R1741
100K
1

20%
16V 2
ELEC
SM

FAN_2_DRV_F

FAN_2_DRV

4.7 2

PP12V_FAN_2_ANALOG
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

TACH

D1705
SM

GND

MBR0530
1 CRITICAL

R1704

10K

13

FAN_TACH2

R1706
0
1

17" HD FAN 603-5520

1%
1/16W
MF
2 402

20" CPU FAN 603-5459

FAN_2_TACH

5%
1/16W
MF
402

REMOTE HARD DRIVE TEMP SENSOR


REMOTE HD TEMP SENSOR

CRITICAL

J1701
53261
PP3V3_PWRON

M-RT-SM
5

1
18
18

I2C_HD_TEMP_SDA
I2C_HD_TEMP_SCL

3
4

I2C ADDR:92(1001001)
6

518S0084

FAN 3 & HD TEMP


A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

17

OF

C
103

7
11 6

PP3V3_PWRON

PP5V_U1800

603

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL

NOSTUFF

11 6

R1833

PP5V_RUN

1
11 6

=PP1V2_EI_NB

C1800

PP3V3_PWRON

27 18 11 6

NOSTUFF

R1830

D
13

14 13 6

13

14 13 6

R1831

2K

SMU
MASTER
U1300
I2C_SMU_A_SDA_IN
MAKE_BASE=TRUE
I2C_SMU_A_SDA_OUT_L
MAKE_BASE=TRUE
I2C_SMU_A_SCL_IN
MAKE_BASE=TRUE
I2C_SMU_A_SCL_OUT_L
MAKE_BASE=TRUE
PINS 36-39

R1800

2K

5%
1/16W
MF
402 2

2K

5%
1/16W
MF
2 402

5%
1/16W
MF
402 2

R1801

20%
10V
CERM 2
402

R1828

4.7K

C1802 R1808
200
0.1UF

4.7K

5%
1/16W
MF
402 2

2K

5%
1/16W
MF
2 402

R18091

0.1UF
NOSTUFF

I2C B BUS

7 14 28

603

PP3V3_RUN
NOSTUFF

5%
1/16W
MF
402 2

20%
10V
2 CERM
402

5%
1/16W
MF
2 402

R18031

R1810
200

2K

5%
1/16W
MF
2 402

SMU
MASTER
U1300

SOI
14

NET_SPACING_TYPE=I2C

13

V+

U3LITE

U1800
GND

NET_SPACING_TYPE=I2C

Q1800

NET_SPACING_TYPE=I2C

2N7002DW

I2C_NB_A_SDA
I2C_NB_A_SCL

SOT-363

27 18 11 6

U1800

2K

5%
1/16W
MF
402 2

SMU

2N7002DW

U2600

NOSTUFF

SOT-363

R1821

27

5%
1/16W
MF
2 402

=PP1V2_EI_CPU

7 14 29 30 31 35

LM339A

R18161

10

SOI

V+

U1800
11

U1602

R1817

200

200

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

16
16

CPU

I2C

SMU_CPU_JTAG_OR_I2C

I2C_CPU_A_SCL
I2C_CPU_A_SDA_TO_SMU
I2C_CPU_A_SDA_TO_CPU

I2C

NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C

SOI
2

16

16

12

SOT-363

U1650

PINS AA20, Y21

NET_SPACING_TYPE=I2C

2N7002DW

PS TEMP SENSOR
4

V+
GND

Q1801

SOT-363

NET_SPACING_TYPE=I2C
I2C_0V6_REF

HD TEMP SENSOR

NOSTUFF

U1702

RP1801
0K

C1801 1 R18111
0.1UF

CPU JTAG

6
5

JTAG_CPU_TDO
JTAG_CPU_TDI
JTAG_CPU_TMS
JTAG_CPU_TCK

29 30

2K

NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C

I2C_NB_C_SCL
MAKE_BASE=TRUE
PINS C21, E21

R18121
2K

U3LITE B

R18151

SHASTA

R1813

R18071

2K

5%
1/16W
MF
2 402

2K

5%
1/16W
MF
402 2

1K

MASTER
U2300

R1806
2K

5%
1/16W
MF
2 402

RTC

5%
1/16W
MF
402 2

R1814
1K

5%
1/16W
MF
2 402

NET_SPACING_TYPE=I2C

I2C_SB_SDA
MAKE_BASE=TRUE
I2C_SB_SCL
MAKE_BASE=TRUE
PINS Y9, AB7

25

U1301

NET_SPACING_TYPE=I2C

25

I2C_NB_B_SDA
I2C_NB_B_SCL

DIMMS

I2C
I2C

I2C
I2C

I2C_RTC_SDA
I2C_RTC_SCL

13
13

PINS 5, 6

PINS C20, B21

J4000 = A0
J4001 = A2

ALIAS

PP3V3_RUN

24

24

ALIAS

5%
1/16W
MF
402 2

I2C SB BUS

PP3V3_ALL

U3

24

I2C_DIMM_SDA
I2C_DIMM_SCL

ALIAS

PINS 1, 2

I2C D & E BUS

24

ALIAS

I2C ADDR:92

PP2V5_PWRON

MASTER
U3
I2C_NB_C_SDA
MAKE_BASE=TRUE

I2C_HD_TEMP_SDA
I2C_HD_TEMP_SCL

29 30

U3LITE

5%
1/16W
MF
2 402

17

USE 576 OHM FOR R1811 IF 5V RAIL IS USED FOR REFERENCE

29 30

1/16W
SM1

2K

17

5%
1/16W
MF
402 2

29 30

I2C C BUS
5%
1/16W
MF
402 2

4.7K

20%
10V
CERM 2
402

5%

R1804

ALIAS

2N7002DW

I2C_CPU_SCL_LS

R1805

ALIAS

I2C ADDR:94

Q1801

I2C_PS_TEMP_SDA
I2C_PS_TEMP_SCL
PINS 1, 2

PP2V5_PWRON

29

U1800

ALIAS

29

LM339A

1/16W
SM1

I2C_CPU_A_SCL
I2C_CPU_A_SDA

ALIAS

I2C ADDR:90

5%
8

I2C_OPTICAL_SDA
I2C_OPTICAL_SCL
PINS 1, 2

U2900

12

ALIAS

OPTICAL TEMP SENSOR

5%
1/16W
MF
2 402

GND

ALIAS

PINS C1, B1

2K

0K

I2C

I2C_CLOCK_SDA
I2C_CLOCK_SCL

5%
1/16W
MF
402 2

27

R1818

RP1800
I2C

NOSTUFF

Q1800 R18201

13

NET_SPACING_TYPE=I2C

PULSAR

3
7

PP3V3_PWRON

R18191

NET_SPACING_TYPE=I2C

I2C_SMU_B_SDA
MAKE_BASE=TRUE
I2C_SMU_B_SCL
MAKE_BASE=TRUE
PINS 26, 27

V+

5%
1/16W
MF
2 402

24

PINS A20, B20

12

13

2K

GND

13

R1802

24

13

NET_SPACING_TYPE=I2C

SOI

13

U3

12

13

5%
1/16W
MF
402 2

LM339A

LM339A

MASTER
U1300
I2C_SMU_CPU_SCL_IN
MAKE_BASE=TRUE
I2C_SMU_CPU_SCL_OUT_L
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_IN
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_OUT_L
MAKE_BASE=TRUE
PINS 14,25,23,68

R1832

PP5V_PWRON

I2C A BUS

MICRODASH
J9400

NOSTUFF
40

R18221

40

PINS 91, 92
OF EACH DIMM

5%
1/16W
MF
402 2

NOSTUFF
1

R1823

94 6

94 6

5%
1/16W
MF
2 402

ALIAS

R1826

5%
1/16W
MF
402

5%
1/16W
MF
402

R1825

R1827

MASTER
U1300

ALIAS

PINS 21, 24

NOSTUFF

R1824
SMU E

I2C_UDASH_SDA
I2C_UDASH_SCL

SMU D

I2C CONNECTIONS

AUDIO

MASTER
U1300

U9500 / AU300

NOSTUFF
13

13

I2C_SMU_E_SDA
I2C_SMU_E_SCL

PINS 50, 51

I2C
I2C

5%
1/16W
MF
402

I2C

I2C_SMU_D_SDA

103 95

I2C

5%
1/16W
MF
402

I2C_SMU_D_SCL

NOTICE OF PROPRIETARY PROPERTY


13

13

PINS 34, 35

103 95

I2C_AUDIO_SDA
I2C_AUDIO_SCL

ALIAS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

ALIAS

PINS 18, 19

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

STANDARD CONFIGURATION: SMU IS MASTER OF BUS E WITH RTC AS SLAVE; U3LITE B AND SMU D ARE NOT USED
TO IMPROVE LATENCY WITH RGB LED - U3LITE B AND SMU E CAN MAKE AN I2C E BUS
SMU D AND RTC CAN MAKE AN I2C D BUS

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

18

OF

C
103

TOTAL CURRENT EXCLUDING LEDS CURRENT < 170 MICRO AMPS

PP3V3_PWRON

RGB_LED

C2105

RGB_LED

220PF
1

PLACE THESE PARTS CLOSE TO SMU IC

G_PWM_IN_H

5%
1/16W
MF
402

RGB_LED

RGB_LED 1

R2104
953K

1%
1/16W
MF
402 2

12

+
-

13

G_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SM

R2105

0.47UF

200K

20%
10V
CERM 2
603

1%
1/16W
MF
402 2

G_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
RGB_LED

R2112
1K

G_IN_OFFSET

R2100

8
11TSSOP

C2107

U2100_UNUSED

GND_CHASSIS_LED

7 21

RGB_LED

220PF

<-- 17 INCH

25.5

LP324

C2109

1%
1/16W
MF
402

5MV INPUT OFFSET

5%
25V
CERM
402

RGB_LED

220PF

220PF

2N3904

20%
16V
CERM
402

RGB_LED 1

SM-1

RGB_LED
1

C2108

RGB_LED

Q2102

10

RGB_LED

C2104

20%
10V
CERM 2
402

5%
25V
2 CERM
402

RGB_LED

RGB_LED

5
BLUE

11TSSOP

U2100

0.1UF

SM-1

G_BASE_DRV

RGB_LED_A
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

RGB_LED

C2103 1

GRN

400-OHM-EMI

0.022UF

C2106 1

LP324
14

RGB_LED

L2104

AMB

L2100

U2100
4

G_PWM_DC

SYS_LED_GREEN
MAKE_BASE=TRUE
PWM INPUT FROM SMU

13

RGB_LED

400-OHM-EMI

RGB_LED

1%
1/16W
MF
402 2

PP5V_PWRON

LATBG66B
AMB-GRN-BLUE
PLCC

953K

R2101

PP5V_PWRON

LED2100
7 21

G_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R21091
RGB_LED

GND_CHASSIS_LED

5%
25V
CERM
402

PP5V_PWRON

RGB_LED

1%
1/16W
MF
2 402

5%
25V
CERM
402

CHANGE R2100 VALUE


TO SET LED CURRENT
MAX LED CURRENT = 0.5 / R

100% DUTY CYCLE OF 3V-PP PWM = 0.5V

SYS_DRV_A
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PLACE THESE PARTS CLOSE TO SMU IC


PP5V_PWRON

R_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

LED2101

1
1

RGB_LED

1%
1/16W
MF
402 2

R_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

LP324

+
-

R_BASE_DRV

RGB_LED

11TSSOP

Q2108

RGB_LED

RGB_LED
1

0.47UF

20%
10V
CERM 2
603

R2111

1%
1/16W
MF
402 2

1K

Q2100

R2113

FDV302P

1%
1/16W
MF
402

25.5

PP3V3_PWRON

<-- 17 INCH

PLACE THESE PARTS CLOSE TO SMU IC


PP5V_PWRON

PWM INPUT FROM SMU

RGB_LED

RGB_LED

R21181

L2102

953K

R2130
2

5%
1/16W
MF
402

953K
1%
1/16W
MF
402 2

1K

117_INCH_LCD

4.7K

1
1

R2103
56.2

1%
1/16W
MF
2 402

SYS_LED_DRV_C
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SYS_LED_IN
3

WHITE_LED

R2107
2

U2100
2

+
-

1
11TSSOP

FDV301N

SM
2

(STUFF WHEN SYS_LED_L = ACTIVE HIGH)


(AND NO STUFF R2132, R2119 & Q2100)

B_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

B_BASE_DRV

WHITE_LED

Q2101

5%
1/16W
MF
402

LP324

SYS_LED_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

5%
1/16W
MF
402 2

RGB_LED

SYS_GATE

SM-1

RGB_LED

1K

5%
1/16W
MF
402

WHITE_LED

R2129

5%
1/16W
MF
402

7 21

R2106

400-OHM-EMI

B_PWM_IN_H

R21161

B_PWM_DC

SYS_LED_BLUE
13
MAKE_BASE=TRUE
PWM INPUT FROM SMU

SYS_LED

GND_CHASSIS_LED

SM-1

WHITE_LED
SYS_LED_H

R2132
13

5%
25V
CERM
402

WHITE_LED

NOSTUFF

B_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

953K 1
1%
1/16W
MF
402

1%
1/16W
MF
402 2

220PF

C2110

400-OHM-EMI

NOSTUFF

R2119

C2111

5%
25V
2 CERM
402

WHITE_LED

L2103

SOT-23

1%
1/16W
MF
2 402

RGB_LED

WHITE_LED
1

NOSTUFF

RGB_LED

2
SM-1

R2114
2

R_IN_OFFSET

PLACE THESE PARTS CLOSE TO SMU IC


R_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

RGB_LED

L2105

400-OHM-EMI

220PF

20%
16V
CERM
402

200K

WHITE_LED

SM6

SM
2

RGB_LED 1

C2112

WHITE

2N3904

C2101

0.022UF

953K

RGB_LED

R21101

5%
1/16W
MF
402

RGB_LED

U2100

R_PWM_IN_H

R_PWM_DC

SM-1

1%
1/16W
MF
402 2

R2115
SYS_LED_RED
MAKE_BASE=TRUE
PWM INPUT FROM SMU
13

SYS_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

400-OHM-EMI

953K
RGB_LED

PP5V_PWRON

RGB_LED

L2101

R21021

RGB_LED

RGB_LED

Q2114

C2102

2N3904

0.022UF
1

TABLE_5_HEAD

SM

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

2
TABLE_5_ITEM

RGB_LED

C2118
0.47UF

RGB_LED

20%
10V
CERM 2
603

R21171

20%
16V
CERM
402

200K
1%
1/16W
MF
402 2

B_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
RGB_LED

RGB_LED
2

1K

RES, 39.2 OHM, 1%, 402

R2103

114S1821

RES, 18.2 OHM, 1%, 402

R2100,R2113,R2126

20_INCH_LCD

INDICATOR LED

TABLE_5_ITEM

20 INCH -->

NOSTUFF

R2126

R2127
B_IN_OFFSET

114S3921

25.5

1%
1/16W
MF
402

NOTICE OF PROPRIETARY PROPERTY

<-- 17 INCH

1%
1/16W
MF
2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

C
OF

21

103

NOTE:
SET OUTPUT=1.5VDC FOR U3LITE CORE
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R2203+R2205)/R2205=1.53VDC

7.73A OF PEAK CURRENT DRAW ON PCORE_NB


PPVCORE_NB

PP5V_PWRON

SM

U2200_VC_R
U2200_VC
1

C2204

1UF

20%
2 25V
CERM
805

C2216

VC

U2200

IRU3037CS
HD
8

U2200_COMP

U2200_GATE_H

SS
LD

FB

Q2201

NTD60N02R

Q2201_GATE
S

C2214
0.1UF

20%
16V
2 CERM
603

R2201_P2

C2215
3900PF

20%
2 25V
CERM
805

R2204

68PF

C2206

NTD60N02R

5%
50V
2 CERM
603

CASE369

S3

5%
25V
2 CERM
402

R2203
2.21K

0.5%
1/16W
MF-LF
2 603

20%
10V
2 CERM
603

NOSTUFF

C2205

C2212

R2205

1UF

10%
50V
2 CERM
603

C2208

1800UF

R2204_P2

0.022UF

5%
50V
2 CERM
603

C2207
1UF

1%
1/16W
MF
2 402

NOSTUFF

220PF

1.1K

Q2202
1
G

C2213

NOSTUFF

20%
2 25V
CERM
1206

C2209
1800UF

20%
2 6.3V
ELEC
TH-KZJ

K15

K12

L14
L17

M16

N18
M11

R18
P11

AG16

P16

U3

P19
N4

U3LITE
V1.0-300MM

AE10

PBGA

AE19
AE25

(SYM 6 OF 7)

N8
N9
N14

AC7

N17

AC13
AC16

N23
N27

AC22
AB2

M12
M15

AB6

M20

AB23
AB27

L10
L13

AA10

L18

AA19
Y12

K2
K6

Y15

20%
2 6.3V
ELEC
TH-KZJ

10K
0.5%
1/16W
MF-LF
2 603

K11

W8
W13

K25
J9

W18

J14

W21
W25

H10
H19

V11

G4

V16
V19

G23
G27

U9

F13

U14
U17

F16
F22

T2
T6

CHECK FETS

GND K16
K21

Y20
W4 GND

U2200_FEEDBACK

22

N13

VDD

OMIT

TH

U2200_FEEDBACK

GND

AG7
AG13
AG22
AE4

L2201
1

D 4

27.4K

20%
2 6.3V
ELEC
8X11.5-TH

1UF

NOSTUFF
6

390UF

C2217

COMP

R2201

MIN_LINE_WIDTH=25MIL Q2202_DRAIN
MIN_NECK_WIDTH=10MIL

U2200_GATE_L

20%
2 6.3V
ELEC
8X11.5-TH

C2203

1.6UH

1%
1/16W
MF
2 402

CASE369

5%
1/10W
FF
805

SOI

U2200_SS

R2202
1

C2202
390UF

20%
6.3V
2 CERM
1206

U2200_VC_D

MBR0520L
SM

20%
2 25V
CERM
805

10UF

1UF

VCC

C2201

D2201

P12
P15

MBR0520L

5%
1/10W
FF
2 805

R14
R17

4.7

=PPVCORE_NB

D2202

T16

W14
W17

22

R2200

U18
T11

U13

MBR0520L
SM

V15
U10

D2200
1

6 7

VOLTAGE=1.2V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
MAKE_BASE=TRUE

V12

PP5V_PWRON

PP5V_PWRON

D2
D7

T12

D10

T15
T20

D19
D25

T23

B4

T27
R10

B13
B16

R13

B22

=PPVCORE_NB
1

C2222
0.1UF

20%
10V
2 CERM
402

C2223

0.1UF

C2225
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2227
0.1UF

20%
10V
2 CERM
402

C2228
0.1UF

20%
10V
2 CERM
402

C2229
0.1UF

20%
10V
2 CERM
402

C2230
0.1UF

20%
10V
2 CERM
402

C2231
0.1UF

20%
10V
2 CERM
402

C2232
0.1UF

20%
10V
2 CERM
402

C2233
0.1UF

20%
10V
2 CERM
402

C2234
0.1UF

20%
10V
2 CERM
402

C2235
0.1UF

20%
10V
2 CERM
402

C2236
0.1UF

20%
10V
2 CERM
402

C2237
0.1UF

20%
10V
2 CERM
402

C2238
0.1UF

20%
10V
2 CERM
402

C2239
0.1UF

20%
10V
2 CERM
402

C2240
0.1UF

20%
10V
2 CERM
402

C2242
0.1UF

20%
10V
2 CERM
402

C2243
0.1UF

20%
10V
2 CERM
402

C2244
0.1UF

20%
10V
2 CERM
402

C2245
0.1UF

C2246
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2247
0.1UF

20%
10V
2 CERM
402

U3LITE CORE POWER


A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

22

OF

C
103

Page Notes

Power aliases required by this page:


- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PPPCI32_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PPVCORE_PWRON_SB (1.2V)
NOTE: PCI pads use the VIO supply to meet
different drive timing
characteristics required by the PCI
spec for 5V vs. 3.3V operation.
Connect _PPPCI32_PWRON_SB to
appropriate PCI bus voltage and
_PPPCI64_PWRON_SB to same if 64-bit
PCI, otherwise 3.3V.

Signal aliases required by this page:


(NONE)
BOM options provided by this page:
(NONE)

Power Sequencing:
Must power Shasta VCore rail before any
other Shasta supplies.

=PP2V5_PWRON_SB
10

7 23 25 74 88

=PPVCORE_PWRON_SB
1

C2350

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

0.1uF

20%
2 10V
CERM
402

C2304
0.1uF

20%
2 10V
CERM
402

0.1uF

20%
2 10V
CERM
402

C2306

0.1uF

20%
2 10V
CERM
402

C2307

0.1uF

20%
2 10V
CERM
402

C2308

0.1uF

20%
2 10V
CERM
402

C2309
0.1uF

20%
2 10V
CERM
402

C2310
0.1uF

20%
2 10V
CERM
402

C2311
0.1uF

20%
2 10V
CERM
402

C2312
0.1uF

20%
2 10V
CERM
402

C2313
0.1uF

20%
2 10V
CERM
402

=PPPCI64_PWRON_SB

V1.0

B2
B5

C2314
0.1uF

20%
2 10V
CERM
402

F4
F8

VIO1

H17
K21

POWER

L21

OMIT

W22

VIO2

Y19

H1

C2320

0.1uF

20%
10V
2 CERM
402

C2321

0.1uF

20%
10V
2 CERM
402

C2322

0.1uF

20%
10V
2 CERM
402

C2323

0.1uF

20%
10V
2 CERM
402

C2324
0.1uF

20%
10V
2 CERM
402

C2355

20%
2 10V
CERM
402

C2356

0.1uF

20%
2 10V
CERM
402

Shasta max (est 06/30/03) current:

V7
W4

DIGITAL
ANALOG12
VDDPs
I/O 2.5
I/O 3.3

A1
A2

1.2V
1.2V
2.5V
2.5V
3.3V

950
600
100
20
220

mA
mA
mA
mA
mA

(1175
( 760
( 250
( 60
( 770

mW)
mW)
mW)
mW)
mW)

A22

=PPPCI32_PWRON_SB

C2360
0.1uF

20%
10V
2 CERM
402

C2361
0.1uF

20%
10V
2 CERM
402

3015 mW

C2325

0.1uF

20%
10V
2 CERM
402

B
1

C2330
0.1uF

20%
2 10V
CERM
402

C2326

0.1uF

20%
10V
2 CERM
402

C2331
0.1uF

20%
2 10V
CERM
402

C2327

0.1uF

20%
10V
2 CERM
402

C2332
0.1uF

20%
2 10V
CERM
402

C2328

For PCI_AD<31..0>
W5
W19

=PP2V5_PWRON_SB

U13
U10

0.1uF

20%
10V
2 CERM
402

C2333
0.1uF

20%
2 10V
CERM
402

C2329
0.1uF

20%
10V
2 CERM
402

C2334
0.1uF

20%
2 10V
CERM
402

AA6
AB1

T12
R19

AB22

F3
F7

P12
P10

H2

N9

H9
J10

N22
N13

J11
J13

N12
N11

M2
M13
M14

M11
M12

GND
M10

0.1uF

20%
2 10V
CERM
402

0.1uF

N10

J16
L16
L9

C2339

L14

0.1uF

20%
2 10V
CERM
402

L12
L13

C2338

L11

0.1uF

20%
2 10V
CERM
402

K9
L10

C2337

K13
K7

0.1uF

20%
2 10V
CERM
402

K12

C2336

K10
K11

0.1uF

20%
2 10V
CERM
402

C2365

P4
GND P14
P13

C19
D2 GND
E22

J22

C2335

7 23 25 74 88

20%
10V
2 CERM
402

P9

J14
1

C2362
0.1uF

20%
10V
2 CERM
402

U22

Total:

A5
AA10

0.1uF

For PCI_AD<63..32>

U9

C2357

20%
2 10V
CERM
402

VDDP_KL V8

L7
M1

=PP3V3_PWRON_SB

0.1uF

R2
U12

74 25 7

H18

BGA
(1 OF 8)

B1

D1
1

0.1uF

SHASTA

AB2
AB6

VDDO33

C2351

20%
10V
2 CERM
402

D19
VDDO25 G15

U2300

AA3
AB10

C2305

VDDC
AA1
AA2

20%
10V
2 CERM
402

T10
T15

R9

0.1uF

C2303

R10
R12

P15

0.1uF

C2302

M15
N8

L8

0.1uF

C2301

K8
L15

J12
J15

C2300

H8

H15

0.1uF

Master: Link

Shasta Core Power

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING

APPLE COMPUTER INC.

TITLE=FIZZY
ABBREV=DRAWING

DRAWING NUMBER

SCALE

LAST_MODIFIED=Wed Aug

SHT
NONE

4 17:57:46 2004

REV.

051-6482
OF

23
1

103

D
=PP1V2_HT

60 7

PP3V3_PWRON

PP2V5_PWRON

PP2V5_PWRON

R2400
100

U3LITE REQUIRES ALL JTAG SIGNALS


HIGH FOR NORMAL OPERATION

1%
1/16W
MF
2 402

NOSTUFF
1

C2401
1000PF

5%
25V
2 CERM
603

R2424 R2426 R2429 R2431 R2433 R2436


10K

10K

10K

10K

10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R2420

NB_VSP_CLK_VREF
VOLTAGE=0.6V
1

R2403
100

1%
1/16W
MF
2 402

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2400 R2402 R2401


0.1UF
1

20%
2 10V
CERM
402

R2419

330

121

121

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

5%
1/16W
MF
2 402

28 25 13

U3LITE
V1.0-300MM

SMU_SUSPENDREQ_L

NB_SUSPEND_REQ_L

Q2404
2N7002DW

U3

330

5%
1/16W
MF
2 402
PMU_SUSPEND_REQ

PBGA

Q2404
2N7002DW

SOT-363

24

SOT-363

(SYM 7 OF 7)
27
27

JTAG_NB_TCK
JTAG_NB_TDI
JTAG_NB_TDO
JTAG_NB_TMS
JTAG_NB_TRST_L

P4 VSP_CLKP
R4 VSP_CLKN

VSP_NB_CLK_P
VSP_NB_CLK_N
JTAG_NB_TCK
JTAG_NB_TDI
JTAG_NB_TDO
JTAG_NB_TMS
JTAG_NB_TRST_L
NB_RI_PU

AC2 CE1_RI
AH3 CEO_TEST
AD5 CE0_MC
AD3 CE0_RE

NB_TEST_PD
NB_MC_PD
NB_RE_PD
1

R2444 R2443 R2442


10K

10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

OMIT

R25 CE1_LT_TCK
V25 CE1_A_TDI
AA25 CE1_B_TDO
M26 CE1_DI1_TMS
F20 CE1_DI2_TRST

TP_NB_PM_SLEEP0

D15 PM_SLEEP0

HRESET*

A21

PURESET*

E20

SUSPENDACK*
SUSPENDREQ*

D20
D21

API0_ISCL A20
API_ISCA B20
SYS_ISCL0 C20
SYS_ISCA0 B21
SYS_ISCL1 C21
SYS_ISCA1 E21
DUMMY_A AC28
DUMMY_B AB28
IRQ0 E9
PMR_OBSV Y9
THMI J17
THMO J18

NB_WARM_RESET_L
NB_COLD_RESET_L
NB_SUSPEND_ACK_L
NB_SUSPEND_REQ_L
I2C_NB_A_SCL
I2C_NB_A_SDA
I2C_NB_B_SCL
I2C_NB_B_SDA
I2C_NB_C_SCL
I2C_NB_C_SDA
TP_DUMMY_A
TP_DUMMY_B

NOSTUFF

24

5%
1/16W
MF
402

18
18

18
18
18
18

6
6

NB_INT_L

25

NB_PMR_OBSV

NB_THMI
NB_THMO

R2408

24

8
8

PP3V3_PWRON
PP2V5_PWRON

NOSTUFF

NOSTUFF
1

5%
1/16W
MF
2 402

13 8

SYS_COLD_RESET_L

4.7K

5%
1/16W
MF
2 402
NB_PU_RESET

5%
1/16W
MF
2 402

6 NOSTUFF

3 NOSTUFF

NB_COLD_RESET_L

Q2412
2N7002DW

R2435

10K

4.7K

24

Q2412
2N7002DW

SOT-363

R2405 R2438

SOT-363

R2406
1

5%
1/16W
MF
402

MASTER: GILA
LAST MODIFIED: JUNE 10, 04

U3LITE MISC
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

24

OF

C
103

10 MIL SPACING

I2S2_DEV_TO_SB_DTI
I2S2_SB_TO_DEV_DTO
I2S2_MCLK
I2S2_BITCLK
I2S2_SYNC

10 MIL SPACING

SB_CLK18M_XTALI
SB_CLK18M_XTALO
SB_CLK18M_XTALO_R
SB_CLK25M_ATA

SPACING
SPACING
SPACING
SPACING

6 25 76 94
30 29 25

6 25 94

25 102

C2521

25 102

25 102

25

25
88 74 23 7

25 27

3.3

2
1

94 76 25 6
94 25 6
94 25 6
94 25 6

5%
1/16W
MF
402

10K

10K

5%
1/16W
MF
402

1
4
3

RP2520

33
5%
1/16W
SM1

5
6

I2S2_DEV_TO_SB_DTI
25 I2S2_SB_TO_DEV_DTO
25 I2S2_MCLK
25 I2S2_BITCLK
25 I2S2_SYNC
102 I2S2_RESET_L
AUDIO GPIO - see note

102
102
102
102

(I2S2_DEV_TO_SB_DTI)
I2S2_SB_TO_DEV_DTO_R
I2S2_MCLK_R
I2S2_BITCLK_R
I2S2_SYNC_R

3
2
1

RP2530

33
5%
1/16W
SM1

7
8

(I2S2_RESET_L)

on right

25
94 25 6

=PP3V3_PWRON_SB
18

R25001

From SouthBridge <SB_INT_L


25

18

10K
5%
1/16W
MF
402 2

87 77 74 8
13
28 24 13

25

13

PCI_64BIT

77 13

R25011
1K

5%
1/16W
MF
402 2

8
8

25

5%
1/16W
MF
402

10K

PCI_SLOTF_REQ_L

6
25

R2580

PCI_SLOTF_GNT_L

5%
1/16W
MF
402 2

25

R2559
2

10K

5%
1/16W
MF
402

25
25

27 25

PCI_SLOTA_INT_L

CRITICAL

25

Y2590

18.432M
1

PCI_SLOTE_INT_L

25

PCI_SLOTG_INT_L

25 77

C2590 1
22pF

5%
50V
CERM 2
402

5%
1/16W
MF
402

3.3

AA5 I2S2DTI_H
Y8 I2S2DTO_H
Y7 I2S2MCLK_H
AB4 I2S2BITCLK_H
W9 I2S2SYNC_H
Y2 GPIO_H_1

I2C_SB_SCL
I2C_SB_SDA

Y9 I2CCLK_H
AB7 I2CDATA_H

SYS_WARM_RESET_L
SB_STOPXTALS_L
SMU_SUSPENDREQ_L
SB_SUSPENDACK_L
SYS_PME_L
TP_SB_WATCHDOG
JTAG_SB_TDI
JTAG_SB_TDO
JTAG_SB_TCK
JTAG_SB_TMS
JTAG_SB_TRST_L
SB_TEST_MODE_PD
TP_SB_PLLTEST
TP_SB_FSTEST
SB_CLK18M_XTALI
SB_CLK18M_XTALO_R
SB_CLK25M_ATA

E9
W10

RESET_L

U11

STOPXTALS_L
SUSPENDREQ_L

V11
W18

SUSPENDACK_L

V12

PCI1PME_L
INTRWD_H

AA11 TDI
W11 TDO
AB11 TCK
Y11 TMS
W12 TRST_L
A3 TEST_MODE_H
U14 PLLTEST
V14 FSTEST
W13 XTAL_18_I
V13 XTAL_18_O
U15 XTALI
NC V15 XTALO

1%
1/16W
MF
2 402
SB_CLK18M_XTALO

25

8X4.5MM-SM
1

C2591
22pF

5%
2 50V
CERM
402

PCI1REQ_3_L

8
9

PCI1REQ_4_L

PCI1GNT_3_L

PCI1GNT_4_L

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

PCI1AD_32_H D18
PCI1AD_33_H A20
PCI1AD_34_H F18

XTAL_18
GND

PLL_45
GND

PCI1AD_35_H F17
PCI1AD_36_H G16
PCI1AD_37_H F16
PCI1AD_38_H A21
PCI1AD_39_H B21
PCI1AD_40_H C20
PCI1AD_41_H G17
PCI1AD_42_H G18
PCI1AD_43_H E19
PCI1AD_44_H F19
PCI1AD_45_H D20
PCI1AD_46_H E20
PCI1AD_47_H C21
PCI1AD_48_H F20
PCI1AD_49_H G19
PCI1AD_50_H C22
PCI1AD_51_H D21
PCI1AD_52_H G20
PCI1AD_53_H D22
PCI1AD_54_H K18
PCI1AD_55_H H19
PCI1AD_56_H J17
PCI1AD_57_H F21
PCI1AD_58_H G21
PCI1AD_59_H H20
PCI1AD_60_H J19
PCI1AD_61_H F22
PCI1AD_62_H G22
PCI1AD_63_H H21
J20
H22

44
45
46
47

PCI1C_BE_4_L

PCI1C_BE_7_L

K20

48
49
50

PCI1REQ64_L
PCI1ACK64_L

K17
L17

PCI1PAR64_H

E18

51
52
53
54

PCI1C_BE_5_L
PCI1C_BE_6_L

K22

XGI_CLK_H Y4
XGI_DTO0_H U7
XGI_DTO1_H T9
XGI_DTI_H W2

FW_LOWPWR

87 25

ENET_ENERGYDET

10K

10K

5%
1/16W
MF
402

R2568

5%
1/16W
MF
402

10K

10K

5%
1/16W
MF
402

SB_TO_SMU_INT_L
CPU_SRESET_L
SB_GPIO12
SYS_OVERTEMP_L
UDASH_SDOWN
UDASH_RESET_L
AGP_INT_L
PCI_SLOTA_INT_L
PCI_SLOTB_INT_L
PCI_SLOTC_INT_L
PCI_SLOTD_INT_L
PCI_SLOTE_INT_L
PCI_SLOTF_INT_L
SB_GPIO23
SB_GPIO24
SB_GPIO25
SB_SATABR_RESET_L
PCI_SLOTG_INT_L
FW_LOWPWR
ENETFW_RESET
SB_GPIO30
ENET_ENERGYDET
AUDIO_LO_DET_L
AUDIO_LO_OPTICAL_PLUG_L
AUDIO_LI_DET_L
AUDIO_LI_OPTICAL_PLUG_L
AUDIO_HP_DET_L
AUDIO_SPKR_DET_L
AUDIO_LO_MUTE_L
AUDIO_HP_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_EXT_MCLK_SEL
AUDIO_GPIO_11
AUDIO_GPIO_12

25
25

I2S0_RESET_L
SB_GPIO45
SB_GPIO46
SB_GPIO47

SB_GPIO12

25

PCI_SLOTB_INT_L

25 29 30

PCI_SLOTC_INT_L

13 16 25 27
25

6 25 94
49

25

25
25

25
25

25

25

SB_GPIO30

25

25

SB_GPIO45

25 90
25

SB_GPIO46

25

SB_GPIO47

25

SB_GPIO49

25 87

25 87

100
102
102 103
101

95
25

10K

25

25

25 13

SB_GPIO50

10K

RP2552
4

10K

5%
1/16W
SM1

RP2553

RP2553

5%
1/16W
SM1

SMU_TO_SB_INT_L

10K

5%
1/16W
SM1

5%
1/16W
SM1

SB_GPIO51

SB_GPIO52

5%
1/16W
SM1

RP2553
25

10K

RP2552

5%
1/16W
SM1

10K

5%
1/16W
SM1

RP2552

25

102

10K

10K

RP2551

5%
1/16W
SM1

25 77

98

RP2552

25

5%
1/16W
SM1

10K

5%
1/16W
SM1

25

102

10K

RP2550

25
25

10K

RP2551

SB_GPIO25

5%
1/16W
SM1

SB_GPIO24

25

5%
1/16W
SM1

5%
1/16W
SM1

SB_GPIO23

10K

10K

RP2551

6 25 76

102

RP2551

PCI_SLOTF_INT_L

6 94

102

RP2550

5%
1/16W
SM1

25

101

RP2550

13 25

101

10K

5%
1/16W
SM1

25

6 101

=PP3V3_PWRON_SB

RP2550

25

10K

RP2553
1

10K

5%
1/16W
SM1

25

Master: Link

25

SYS_SLEWING_L
SB_GPIO49
SB_GPIO50

13 25 27 33

Shasta Serial / Misc

25
25

SB_GPIO51
SB_GPIO52
NB_TO_SB_INT
SMU_TO_SB_INT_L

25

NOTICE OF PROPRIETARY PROPERTY

25

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

25
13 25

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

PLL_49
GND

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

REV.

051-6482
SHT
NONE

4 17:57:47 2004

R2567

SCALE

10K

5%
1/16W
MF
402

ENETFW_RESET

APPLE COMPUTER INC.

R2566

7 23 25 74

C2540

TITLE=FIZZY
ABBREV=DRAWING

SIZE

5%
1/16W
MF
402

SB_SATABR_RESET_L

REDUNDANT - NEED TO ADDRESS THIS

"Slot E" - AD21


PCI_SLOTE_REQ_L
AA19 PCI_SLOTE_GNT_L
"Slot F" - AD22
AB21 PCI_SLOTF_REQ_L
AA20 PCI_SLOTF_GNT_L

Y20

R2565
25

U17

PCI1REQ_5_L
PCI1GNT_5_L

10K

NO STUFF

20%
10V
2 CERM
402

10
11

R2564
10K

R2561

5%
1/16W
MF
402

0.1uF

U16

5%
1/16W
MF
402

74 25 23 7

6
7

5%
1/16W
MF
402

R2563

20%
6.3V 2
CERM
1206

DRAWING

LAST_MODIFIED=Wed Aug

1K

10K

5%
1/16W
MF
402

I2S1_RESET_L

25

200
PCI_SLOTD_INT_L

W17

Y12

AA13

I2S0

V10 I2S1DTI_H
AB5 I2S1DTO_H
V9 I2S1MCLK_H
AA8 I2S1BITCLK_H
AA7 I2S1SYNC_H

AB3 GPIO_H_2
W8 GPIO_H_3
W6 PCI_SEL32BIT_H

R2590

6 25 76

MODEM_RING2SYS_L

25

SB_INT_L
MODEM_RING2SYS_L
SB_PCI_SEL32BIT

R2558
1

U8 I2S0MCLK_H
AA4 I2S0BITCLK_H
Y6 I2S0SYNC_H

V5 GPIO_H_0

(I2S1_RESET_L)

4.7K

R2557

10K

(I2S1_DEV_TO_SB_DTI)
I2S1_SB_TO_DEV_DTO_R
I2S1_MCLK_R
I2S1_BITCLK_R
I2S1_SYNC_R

102 25

1 = 32-bit PCI & GPIOs


0 = 64-bit PCI & XGC

PCI_SLOTE_GNT_L

5%
1/16W
MF
402

R2556

10K

5%
1/16W
MF
402

33
5%
1/16W
SM1

R2552

R2553
1

RP2510

BGA
(2 OF 8)

W7 I2S0DTI_H
Y5 I2S0DTO_H

XGI

NO STUFF

OMIT

V1.0 GPIO

(I2S0_DEV_TO_SB_DTI)
I2S0_SB_TO_DEV_DTO_R
I2S0_MCLK_R
I2S0_BITCLK_R
I2S0_SYNC_R

SM

PCI_SLOTE_REQ_L

R2555

5%
1/16W
MF
402

5%
1/10W
FF
805

10uF

VIO
PME

XTAL_18 PLL_45 PLL_49


VDD
VDD
VDD

AB13

R2551
10K

5%
1/16W
MF
402

94 25 6

AA12

94 76 25 6

I2S1_DEV_TO_SB_DTI
I2S1_SB_TO_DEV_DTO
I2S1_MCLK
I2S1_BITCLK
I2S1_SYNC
I2S1_RESET_L

PCI 32-bit select

10K

33 27 25 13

SYS_SLEWING_L

1K

SHASTA

4
3

XTAL
VDD

I2S1

94 76 25 6

1uF

10%
6.3V
2 CERM
402

U2300

2N3904

R2550

NO STUFF

R2562

R2530

=PP3V3_PWRON_SB

PCI

103 95 25

C2511

(SCCA)

102 25

7 74 75 76 77

10uF

20%
6.3V
2 CERM
1206

I2S2

103 95 25

103 102 25

C2510

5%
1/16W
MF
402

I2S0_DEV_TO_SB_DTI
I2S0_SB_TO_DEV_DTO
I2S0_MCLK
I2S0_BITCLK
I2S0_SYNC

5%
1/16W
MF
402

=PP3V3_PCI

UDASH_RESET_L

90 25

94 25 6

87 25

MPIC_SB

C2530

1uF

AB12

30 29 14 6

Q2576

R2578
1

C2531

REDUNDANT - NEED TO ADDRESS THIS

1uF

10%
6.3V
2 CERM
402

(SCCB)

I2S1: Soft Modem


I2S0: Audio DAC
I2S2: S/P-DIF

To SouthBridge ->
NB_TO_SB_INT 25

95 25

74 25 23 7

5%
1/16W
MF
402 2

MPIC_SB
NB_INT_L_R

C2501

GPIO

<- To CPU
CPU_INT_L

R2511

5%
1/16W
MF
402

MPIC_NB

R25791

10K

PP1V2_PWRON_SB_PLL49VDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

PP2V5_PWRON_SB_XTALVDD
VOLTAGE=2.5V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

Re-pin within each RPAK as necessary


DO NOT swap between RPAKs

MPIC_SB

C2500
10uF

5%
1/10W
FF
805

3.3

R2575

5%
1/10W
FF
805

SYS_OVERTEMP_L

94 25 6

PP2V5_PWRON_SB_XTAL18VDD
VOLTAGE=2.5V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

R2505

=PP2V5_PWRON_SB

BOM options provided by this page:


- PCI_64BIT
Configures Shasta for 64-bit PCI
NOTE: XGC required for Shasta GPIOs
- MPIC_NB/MPIC_SB
Selects whether NorthBridge or
SouthBridge MPIC will be used for
interrupt controller.

-> From NorthBridge


NB_INT_L

CPU_SRESET_L

25

R2510

5%
1/16W
MF
2 402

3.3

=PP1V2_PWRON_SB

20%
6.3V 2
CERM
1206

10%
6.3V 2
CERM
402

10K

10uF

10%
6.3V 2
CERM
402

Signal aliases required by this page:


(NONE)

24

C2520

1uF

25 102

20%
6.3V
2 CERM
1206

R2576

R2520

25 102

Power aliases required by this page:


- _PP3V3_PCI
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PP1V2_PWRON_SB

27 25 16 13

PP1V2_PWRON_SB_PLL45VDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

6 25 94

Page Notes

PP3V3_RUN

R2560

5%
1/10W
FF
805

NorthBridge / SouthBridge MPIC Routing

1K

5%
1/16W
MF
402

6 25 76 94

6 25 76 94

I2C

SB_CLK25M_ATA

MIL
MIL
MIL
MIL

SB_TO_SMU_INT_L

25 95 103

PWR_MGT

15
15
15
15

25 13

25 102 103

TEST

SB_CLK18M_XTAL

=PP3V3_PWRON_SB

R2554

XTALS

I2S2_TO_SB
I2S2_TO_DEV
I2S2_TO_DEV
I2S2_BIDIR
I2S2_BIDIR

25 95 103
25 102

AUDIO GPIOS

I2S1_DEV_TO_SB_DTI
I2S1_SB_TO_DEV_DTO
I2S1_MCLK
I2S1_BITCLK
I2S1_SYNC

74 25 23 7

25 95

NOTE: It is the responsibility of


the audio circuit to provide the
necessary pull-ups & pull-downs.

I2S0_DEV_TO_SB_DTI
I2S0_SB_TO_DEV_DTO
I2S0_MCLK
I2S0_BITCLK
I2S0_SYNC

AUDIO

I2S1_TO_SB
I2S1_TO_DEV
I2S1_TO_DEV
I2S1_BIDIR
I2S1_BIDIR

DIFFERENTIAL_PAIR

Y13

NET_SPACING_TYPE

I2S0_TO_SB
I2S0_TO_DEV
I2S0_TO_DEV
I2S0_BIDIR
I2S0_BIDIR

W14

ELECTRICAL_CONSTRAINT_SET

OF

25
1

103

7
L2601

26 7

=PPVCORE_PWRON_PULSAR

26 7

180-OHM-1.5A
1

SYM 2 OF 2

=PPVCORE_PWRON_PULSAR

2
0603

C2645
2.2UF

20%
2 6.3V
CERM1
603

C2611
0.1UF
20%

C2609
0.1UF

20%
2 10V
CERM
402

40 37 26 7

=PP2V5_PWRON_RAM

0603

5%
1/16W
MF
402
1

C2669

PP1V5_PSL_PLL2
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
1
MIN_NECK_WIDTH=10MIL

C2617

20%
6.3V
2 CERM1
603

C2613
0.1UF

26 7

2 10V
CERM
402

20%
2 10V
CERM
402

PLACE NEAR PIN D2 D1

L2605
180-OHM-1.5A
1

=PPVCORE_PULSAR

0.1UF
20%

2.2UF

26 7

=PP1V2_PULSAR

26 7

=PPVCORE_PULSAR

R2603
4.7
2

VSS33 E2
VSS33_BC L7
VSS33_BC1 M5

A11 VDD_HCLK0
A9 VDD_HCLK0
A8 VDD_HCLK1
C5 VDD_HCLK2
B4 VDD_HCLK2

VSS_HCLK0 C10
VSS_HCLK0 B11

K10 VDD_HSYNC
H12 VDD_HSYNC

VSS_HSYNC H10
VSS_HSYNC K12

VSS_HCLK1 B7
VSS_HCLK2 A4
VSS_HCLK2 A7

A1 VDD_VCLK
A12 VDD_XTAL

PP1V5_PSL_PLL3

5%
1/16W
MF
402
1

VSS25 L2
VSS25 H2

J11 VDD15_HSYNC
M11 VDD15_PCLK

0603

VSS_NBSYNC F11
VSS_PCLK L12

E1 VDD33
L5 VDD33_BC
M9 VDD33_BC1

R2609

VSS_CML A6
VSS_I2C C2

H3 VDD25
K1 VDD25

PP3V3_PWRON
PP3V3_RUN

4.7 2

VSS_PLL4 M2

B2 VDD_I2C
G12 VDD_NBSYNC
M12 VDD_PCLK

=PP1V2_PULSAR

PLACE NEAR PIN D10 D12

180-OHM-1.5A

C4_VSS C9
VSS_PLL1 D12
VSS_PLL2 D1
VSS_PLL3 K8

M3 VDD_PLL4

26 7

FSBGA

PP3V3_PWRON

2 10V
CERM
402

L2603

PULSAR

D10 VDD_PLL1
D2 VDD_PLL2
L8 VDD_PLL3

PP1V5_PSL_PLL1
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C1_VSS G1
C2_VSS M4
C3_VSS E10

U2600

B9 C4_VDD

5%
1/16W
MF
402
1

OMIT

F1 C1_VDD
L3 C2_VDD
E12 C3_VDD

R2601
4.7

C2603
2.2UF

20%
6.3V
2 CERM1
603

C2615
0.1UF

20%
2 10V
CERM
402

L2607 PLACE

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2601
0.1UF

20%
2 10V
CERM
402

VSS_VCLK A3
VSS_XTAL C12

C
PINS G12, M12, H3, K1, L5, M9, A11, A9
A8, C5, B4, K10, H12 J11, M11, A1
CAN BE TURNED OFF IN SLEEP

NEAR PIN L8 K8

180-OHM-1.5A
1

PP3V3_PWRON

PP3V3_RUN

0603

R2605
4.7
1

PP1V5_PSL_PLL4

5%
1/16W
MF
402

C2607

0.1UF
20%

2.2UF

20%
6.3V
2 CERM1
603

C2619
0.1UF

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2605

0.1UF
20%

2 10V
CERM
402

2 10V
CERM
402

40 37 26 7

20%
2 10V
CERM
402

PLACE NEAR PIN M3 M2

0.1UF
20%

C2651 1 C2671
0.1UF

20%
2 10V
CERM
402

2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

=PP2V5_PWRON_RAM

L2609
180-OHM-1.5A

PP3V3_PWRON

C2665 1 C2667

C2639
0.1UF
20%

2 10V
CERM

402

C2640
0.1UF
20%

2 10V
CERM

402

0603

R2607
4.7
1

5%
1/16W
MF
402

PP3V3_PSL_XTAL
1

C2621
2.2UF

20%
2 6.3V
CERM1
603

C2620
0.1UF
20%

C2622
0.1UF
20%

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

26 7

=PPVCORE_PULSAR
1

C2631 1 C2632 1 C2633 1 C2634 1 C2635 1 C2636 1 C2637 1 C2638


0.1UF

2 10V
CERM
402

20%
2 10V
CERM
402

2 10V
CERM
402

402 CAPS NOT NEEDED


26 7

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

=PPVCORE_PWRON_PULSAR

IF 603 CAN BE PLACED CLOSE TO PULSAR


1

C2627 1 C2628 1 C2629 1 C2630


0.1UF

20%
2 10V
CERM
402

26 7

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

=PP1V2_PULSAR

C2623 1 C2624 1 C2625 1 C2626


0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

MASTER: GILA
LAST MODIFIED: APR 09, 04
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

PULSAR POWER

TABLE_5_ITEM

359S0076

PULSAR, PBGA

U2600

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6482 C
26 103
SHT

OF

NONE

7
ELECTRICAL_CONSTRAINT_SET

29 27
29 27
14 6
14 6
28 27
28 27
29 27
28 27

14 6

27 24
27 24

48 27
49 27

EI_CPU_CLK_P
EI_CPU_CLK_N
EI_CPU1_CLK_P
EI_CPU1_CLK_N
EI_NB_CLK_P
EI_NB_CLK_N
EI_CPU_SYNC
EI_NB_SYNC
EI_CPU1_SYNC

EI_CPU_CLK
EI_CPU_CLK
EI_CPU1_CLK
EI_CPU1_CLK
EI_NB_CLK
EI_NB_CLK
EI_SYNC

NET_PHYSICAL_TYPE

NET_SPACING_TYPE

DIFFERENTIAL_PAIR
EI_CPU_CLK
EI_CPU_CLK
EI_CPU1_CLK
EI_CPU1_CLK
EI_NB_CLK
EI_NB_CLK

EI_CPU1_SYNC

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

VSP_NB_CLK_P
VSP_NB_CLK_N

VSP_NB_CLK
VSP_NB_CLK

CLOCKS
CLOCKS

VSP_NB_CLK
VSP_NB_CLK

AGP_CLK66M_NB
AGP_CLK66M_GPU

AGP_NB_CLK
AGP_GPU_CLK

CLOCKS
CLOCKS

HT_CLK66M_NB
HT_CLK66M_SB

HT_NB_CLK
HT_SB_CLK

CLOCKS
CLOCKS

PCI_CLK66M_SB_INT
PCI_CLK33M_SB_EXT

CLOCKS_PCI
CLOCKS_PCI

CLOCKS
CLOCKS

R2701
5%

I86
I87

62 27

I117

74 8

3.3V

33MHZ

3.3V

33MHZ

R2761
0

I96

I97

5% 402

PCI_CLK_GP0

PCI_CLK_GP1

I98
I99

C2708

I118

0.001UF
50V 1

2 CERM

I94

10%

I95

402

VSP_NB_CLK_P
VSP_NB_CLK_N

C2710

0.001UF

I100

50V

I101

I102

PLS_EXTCLK

PLS_XTAL

I103

402

0.001UF

I90

1
10%

2 CERM
402

I91

CLOCKS

24 27

2 CERM

EI_CPU_CLK_P
EI_CPU_CLK_N

C2715
27

24 27

C2713

50V
74 27

I116

10%
60 27

0.001UF

I119

50V 1
10%

DIFFERENTIAL SIGNALS SHOULD HAVE 5 MIL SPACING TO EACH OTHER


ALL SPACING GROUPS SHOULD HAVE 15 MIL SPACING TO SIGNALS NOT IN THEIR GROUP

27 29
27 29

2 CERM
402

NET
SPACING
TYPE

EI_NB_SYNC IS PART OF EI_CPU_SYNC TOPOLOGY


SYM 1 OF 2
GPCLK33_0 L4
GPCLK33_1 K4

OMIT

U2600

PULSAR
FSBGA

13

R2704
0

CLOCK_RESET_L

18

I2C_CLOCK_SCL

C1 SCLK

18

I2C_CLOCK_SDA

B1 SDATA

PLS_RESET_L

D3

PLS_X_IN

C11 XIN

PLS_X_OUT

B12 XOUT

RESET*

5% 402

NOSTUFF
R2738
1K

0=IIC ADDR D2/D3

PLS_X_ADDRSEL

E3 ADDRSEL

5% 402

1=IIC ADDR D4/D5

6
6
6

TP_PLS_TEST1
TP_PLS_TEST2
TP_PLS_TEST3

K3 TEST1
E11 TEST2
D11 TEST3

VCLKN A2
VCLKP B3
HCLKN_0 B10
HCLKN_1 C8
HCLKN_2 C4
HCLKP_0 A10
HCLKP_1 B8
HCLKP_2 B5
GPCLK25_0 J3
GPCLK25_1 J1
PCLK25_0 K2
PCLK25_1 L1
PCLK33_0 K5
PCLK33_1 L6
PCLK33_2 M7
PCLK33_3 L9
PCLK33_4 M10

R2706 249
18 11 6

PP3V3_PWRON

R2722

PLS_SCAN_MODE

1%

PLS_REF15
PLS_REF25
PLS_REF33

402 1%
2 402 1%
402
1%
2

R2744 681 1
R2740 1K 1
R2746 1K 1

402

1K

NOSTUFF

R2748

SYS_OVERTEMP_L

25 16 13

5%
1/16W
MF
2 402

R2742

806 1

402 1%

G11 REF15
J2 REF25
M6 REF33

TP_PLS_REF_CML

A5 REF_CML

PLS_PRES_CML

B6 PRES_CML

PLS_FORCE_P0_L_R

M1 SCAN_MODE

5%
1/16W
MF
402

F2

FORCESPO*

=PULSAR_POWER_DOWN

R2750 47

R2724 1K

NO STUFF

R2752
NOSTUFF

J2700

U.FL-R_SMT
F-ST-SM
3

PLS_EXTCLK
NOSTUFF
1

27

24

1
2

NOSTUFF
1

330K2
5%
1/16W
MF
402

24

5%
1/16W
MF
2 402

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

PLS_CLK_66M_0_R
PLS_CLK_66M_1_R

CLOCKS
CLOCKS

HT_CLK66M_NB_R
RAM_CLK66M_NB_R

CLOCKS
CLOCKS

PCI_CLK66M_SB_INT_R
PCI_CLK_P1_R
AGP_CLK66M_GPU_R
PCI_CLK_P3_R
PCI_CLK_P4_R

402

EI_NB_CLK_P
EI_NB_CLK_N

C2702

50V 1

NOSTUFF 10%
0 R2775
1

5% 402

5% 402

0 R2711
1

CLOCKS
CLOCKS
CLOCKS

SB_CLK25M_ATA_R
SATA_CLK25M_R

CLOCKS
CLOCKS

5% 402
0 R2702
1

5% 402
1

66MHZ
66MHZ

TP_PLS_CLK_66M_0
TP_PLS_CLK_66M_1

2.5V
2.5V

66MHZ
66MHZ

HT_CLK66M_NB
RAM_CLK66M_NB

3.3V
3.3V
3.3V
3.3V

66MHZ
33MHZ
66MHZ
33MHZ

PCI_CLK66M_SB_INT
PCI_CLK_P1
AGP_CLK66M_GPU
PCI_CLK_P3
PCI_CLK_P4

27 49

1.2V

33MHZ

CPU_HTBEN

29 30

0 R2705

5% 402

5% 402

0 R2707
1

2.5V
2.5V
20 R2703
1

0 R2779
1

5% 402

0 R2768
1
1

27 60
37

27 74
8

8
8

1.2V

EI_NB_SYNC

27 28

1.2V

EI_CPU_SYNC

27 29

5% 402

5% 402

14

20 R2770
NOSTUFF
22 R2700
1

0 R2720
1

SYS_SLEWING_L

5% 402

2.5V
2.5V

25MHZ
25MHZ

SB_CLK25M_ATA
TP_SATA_CLK25M

1.2V
1.5V

66MHZ
66MHZ

HT_CLK66M_SB
AGP_CLK66M_NB

25
6

5% 402
13 25 33

5% 402

HT_CLK66M_SB_R
AGP_CLK66M_NB_R

5% 402

14

0 R2772

CLOCKS

27 28

402

NOSTUFF
0 R2776

20 R2709
1

27 28

2 CERM

0 R2715

EI_CPU_SYNC_R
EI_CPU1_SYNC_R

SLEWING_L_R
CLOCK_ERROR_L

2 CERM

0.001UF
14

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

EI_NB_SYNC_R

K9
M8

10%

5% 402

NBSYNC F12

REFCLK_0 G2
REFCLK_1 H1

14

5% 402

CLOCKS
CLOCKS

HSYNC_0 J10
HSYNC_1 H11

C2700
0.001UF
50V 1

0 R2717

CLOCKS
CLOCKS

5% 402

0 R2719
1

27 62
27 48

5% 402

PULSAR_POWER_DOWN_R

402 5%

5%
1/16W
MF
402

NO STUFF

R2764

EI_CPU_CLK_N_C
EI_CPU1_CLK_N_R
EI_NB_CLK_N_C
EI_CPU_CLK_P_C
EI_CPU1_CLK_P_R
EI_NB_CLK_P_C

R2754
0

R2758
1

NOSTUFF

402 5%

CLOCKS
CLOCKS

5%
1/16W
MF
402

R2762

5%
1/16W
MF
2 402
PLS_INTERM

VSP_NB_CLK_N_C
VSP_NB_CLK_P_C

CPU_HTBEN_R
CPU1_HTBEN_R

PCLK12 L11
PCLK15 L10
3

CLOCKS
CLOCKS

HTBEN_0 K11
HTBEN_1 J12

SLEWING*
ERROR*

C3 PD

PCI_CLK_GP0_R
PCI_CLK_GP1_R

R2756
0
1

5%
1/16W
MF
402

CRITICAL

Y2701

MASTER: GILA

25.0000M
1

LAST MODIFIED: JULY 12, 04

PLS_X_OUT_B

PLS_X_IN_B

8X4.5MM-SM

PULSAR CLOCKS

C2707

33PF
5%

C2705

NOTICE OF PROPRIETARY PROPERTY

33PF
5%

50V
CERM 2
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

2 50V
CERM
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

27

OF

C
103

=PP1V2_EI_NB

7 14 18 28

ELECTRICAL_CONSTRAINT_SET
29 28 14 6

C2800
0.1UF

20%
10V
2 CERM
402

C2801
0.1UF

20%
10V
2 CERM
402

C2802
0.1UF

C2803
0.1UF

20%
10V
2 CERM
402

C2804

0.1UF

C2805
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2806

0.1UF

C2808

0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2807

0.1UF

C2809
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2810
0.1UF

20%
10V
2 CERM
402

C2811
0.1UF

20%
10V
2 CERM
402

C2812
0.1UF

20%
10V
2 CERM
402

C2813
0.1UF

20%
10V
2 CERM
402

C2814
0.1UF

20%
10V
2 CERM
402

C2815
0.1UF

20%
10V
2 CERM
402

C2816
0.1UF

20%
10V
2 CERM
402

C2817

29 28 14 6

0.1UF

29 28 14 6

20%
10V
2 CERM
402

29 28 14 6

29 28 14 6
29 28 14 6

29 28 14 6

=PP1V5_PWRON_NB_AVDD

29 28 14 6

R2800
PP1V5_PWRON_EI_NB_AVDD
VOLTAGE=1.5V

C2818

C2819

=PP1V2_EI_NB

29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6

29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6

29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6

29 28 14 6
29 28 14 6
29 28 14 6

PLACE R2805 AND R2806


NEAR U3LITE

29 28 14 6

29 14 6

29 28 14 6

OMIT

U3
U3LITE
V1.0-300MM
PBGA
(SYM 1 OF 7)

F11 API0_ADI0
F12 API0_ADI1
G11 API0_ADI2
H11 API0_ADI3
G12 API0_ADI4

OMIT

H12 API0_ADI5
H14 API0_ADI6
G14 API0_ADI7

APPLE PI
INTERFACE

API0_BCLKOP D6
API0_BCLKON E6
API0_ADO0 J2
API0_ADO1 H1
API0_ADO2 J1
API0_ADO3 K1
API0_ADO4 E1
API0_ADO5 F2
API0_ADO6 J4
API0_ADO7 H4
API0_ADO8 G1
API0_ADO9 H2
API0_ADO10 F1

E11 API0_ADI11
A10 API0_ADI12
A9 API0_ADI13
A8 API0_ADI14
B9 API0_ADI15

API0_ADO11 H5
API0_ADO12 H3

C11 API0_ADI16
B11 API0_ADI17
A11 API0_ADI18

API0_ADO16 E3
API0_ADO17 F4
API0_ADO18 E2

A12 API0_ADI19
B12 API0_ADI20
C12 API0_ADI21

API0_ADO19 F5
API0_ADO20 H6
API0_ADO21 J7

D12 API0_ADI22
E12 API0_ADI23
A13 API0_ADI24
A14 API0_ADI25
B14 API0_ADI26

API0_ADO22 F3
API0_ADO23 J8

C14 API0_ADI27
A16 API0_ADI28
A15 API0_ADI29

API0_ADO27 E4
API0_ADO28 D8
API0_ADO29 A5

B15 API0_ADI30
C15 API0_ADI31
H15 API0_ADI32

API0_ADO30 C2
API0_ADO31 C3
API0_ADO32 C5

G15 API0_ADI33
F17 API0_ADI34
G17 API0_ADI35
G18 API0_ADI36
H18 API0_ADI37

API0_ADO33 C6
API0_ADO34 B2

F18 API0_ADI38
E18 API0_ADI39
A17 API0_ADI40

API0_ADO38 A6
API0_ADO39 C8
API0_ADO40 A2

A18 API0_ADI41
B17 API0_ADI42
C17 API0_ADI43

API0_ADO41 B3
API0_ADO42 A7
API0_ADO43 B8

EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_SR_N<1>

D17 API0_SRIP0
A19 API0_SRIN0
E17 API0_SRIP1

API0_SROP0 A3
API0_SRON0 A4
API0_SROP1 B5

B18 API0_SRIN1

API0_SRON1 B6

EI_QACK_L

D14 API_QACK0

API0_ADO13 J3
API0_ADO14 J5
API0_ADO15 J6

API0_ADO24 F6
API0_ADO25 E5
API0_ADO26 D5

API0_ADO35 D1
API0_ADO36 B1
API0_ADO37 C1

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

EI_CPU_TO_NB_AD<0..43>
EI_NB_TO_CPU_AD<0..43>

EI_CPU_TO_NB_CAD
EI_NB_TO_CPU_CAD

EI_CPU_TO_NB_AD
EI_NB_TO_CPU_AD

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK

EI_CPU_TO_NB_SR0
EI_CPU_TO_NB_SR0
EI_CPU_TO_NB_SR1
EI_CPU_TO_NB_SR1

EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_SR_N<1>

EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD

EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

EI_NB_TO_CPU_SR0
EI_NB_TO_CPU_SR0
EI_NB_TO_CPU_SR1
EI_NB_TO_CPU_SR1

I212
I213
I214
I215
I216
I217
I218
I219

I220
I221
I222
I223
I224
I225

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N

ZT2807

OMIT

OMIT

ZT2817

OMIT

ZT2827

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

6 14 28 29

ZT2848

6 14 28 29

ZT2858

HOLE-VIA-20R10

6 14 28 29

OMIT

ZT2867

HOLE-VIA-20R10

6 14 28 29

EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<11>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<15>
EI_CPU_TO_NB_AD<16>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<26>
EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<43>

OMIT

ZT2857

HOLE-VIA-20R10

HOLE-VIA-20R10

ZT2868

HOLE-VIA-20R10

ZT2808

HOLE-VIA-20R10

ZT2818

HOLE-VIA-20R10

OMIT

ZT2828

HOLE-VIA-20R10

ZT2837

HOLE-VIA-20R10

ZT2838

HOLE-VIA-20R10

6 14 28 29

OMIT

6 14 28 29

OMIT

ZT2849

6 14 28 29
6 14 28 29

OMIT

ZT2859

OMIT

ZT2869

ZT2809

OMIT

OMIT

ZT2819

OMIT

ZT2829

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2839

HOLE-VIA-20R10
1

6 14 28 29
6 14 28 29

ZT2850

6 14 28 29
6 14 28 29

ZT2860

ZT2800

ZT2810

ZT2820

OMIT

ZT2830

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2840

HOLE-VIA-20R10
1

6 14 28 29
6 14 28 29

ZT2851

6 14 28 29
6 14 28 29

ZT2861

ZT2801

ZT2811

ZT2821

OMIT

ZT2831

ZT2841

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

6 14 28 29
6 14 28 29

ZT2852

6 14 28 29
6 14 28 29

ZT2862

ZT2802

ZT2812

ZT2822

ZT2832

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2842

HOLE-VIA-20R10
1

6 14 28 29
6 14 28 29

ZT2853

6 14 28 29
6 14 28 29

ZT2863

ZT2803

ZT2813

ZT2823

OMIT

ZT2833

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2843

HOLE-VIA-20R10
1

6 14 28 29
6 14 28 29

ZT2854

6 14 28 29
6 14 28 29

ZT2864

ZT2804

ZT2814

ZT2824

OMIT

ZT2834

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2844

HOLE-VIA-20R10
1

6 14 28 29
6 14 28 29

ZT2855

6 14 28 29

ZT2865

HOLE-VIA-20R10

6 14 28 29

HOLE-VIA-20R10

ZT2805

HOLE-VIA-20R10
1

ZT2815

ZT2825

OMIT

ZT2835

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

ZT2845

HOLE-VIA-20R10
1

6 14 28 29
6 14 28 29

ZT2806

6 14 28 29

HOLE-VIA-20R10

6 14 28 29

ZT2816

HOLE-VIA-20R10
1

OMIT

ZT2826

HOLE-VIA-20R10
1

ZT2836

HOLE-VIA-20R10
1

6 14 28 29

OMIT

6 14 28 29
6 14 28 29

=PP1V2_EI_NB

6 14 28 29

HOLE-VIA-20R10

7 14 18 28

OMIT

ZT2856

HOLE-VIA-20R10

NOSTUFF

6 14 28 29

ZT2866

HOLE-VIA-20R10

R2802

6 14 28 29

100

6 14 28 29

NOSTUFF

6 14 28 29

6 14 28 29

C2821

1%
1/16W
MF
2 402

0.001UF

6 14 28 29

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

ZT2846

OMIT

10%
50V
2 CERM
402

6 14 28 29

NOSTUFF
1

R2801
100

6 14 28 29

6 14 28 29

C2820
0.1UF

1%
1/16W
MF
2 402

6 14 28 29

EI_APCLK_VREF
VOLTAGE=0.6V
NOSTUFF
NOSTUFF
1
20%
10V
2 CERM
402

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
NOSTUFF
1

R2803 R2804
121

121

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

API_QREQ0 E14

E8 API0_APSYNC
H17 API0_SE

NB_APSYNC

OMIT

ZT2847

D9 API0_ADI8
C9 API0_ADI9
D11 API0_ADI10

DIFFERENTIAL_PAIR

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

VDD_API

EI_NB_TO_CPU_AD<0>
EI_NB_TO_CPU_AD<1>
EI_NB_TO_CPU_AD<2>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<5>
EI_NB_TO_CPU_AD<6>
EI_NB_TO_CPU_AD<7>
EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<9>
EI_NB_TO_CPU_AD<10>
EI_NB_TO_CPU_AD<11>
EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<14>
EI_NB_TO_CPU_AD<15>
EI_NB_TO_CPU_AD<16>
EI_NB_TO_CPU_AD<17>
EI_NB_TO_CPU_AD<18>
EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<22>
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_AD<24>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<26>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<32>
EI_NB_TO_CPU_AD<33>
EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<35>
EI_NB_TO_CPU_AD<36>
EI_NB_TO_CPU_AD<37>
EI_NB_TO_CPU_AD<38>
EI_NB_TO_CPU_AD<39>
EI_NB_TO_CPU_AD<40>
EI_NB_TO_CPU_AD<41>
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_AD<43>

EI_NB_SYNC

B10
B19

29 28 14 6

F15 API0_BCLKIP
E15 API0_BCLKIN

EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK_N

R2805
27

7 14 18 28
29 28 14 6

D16
B7

20%
10V
2 CERM
402

API
APCLK_AVDD

29 28 14 6

29 28 14 6

0.1UF

10%
6.3V
2 CERM
402

29 28 14 6

29 28 14 6

D13

1UF

F10
D4

F7

5%
1/16W
MF
603

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

H16
G2

H13

2.2

K8
J13

F21

29 28 14 6

K4

60 48 37 7

NET_SPACING_TYPE

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK_N

API_APCLKP D18
API_APCLKN C18

402

API_CSTP F14

EI_NB_CLK_P

EI_NB_CLK_P
EI_NB_CLK_N

EI_NB_CLK_N

CPU_CHKSTOP_L

27
27

29

NOSTUFF

R2806
30 29 14 6

EI_SYNC_FROM_NB

API_APCLK_AVSS

G20

29

402

EI_SE

QREQ_L HACK
28 7

QREQ TO SMU

LAST MODIFIED: JULY 14, 04


28 7

=PP3V3_PWRON_EI

CRITICAL

C2850 1

25 24 13

POST-RAMP QUAL
ALTERNATE FOR
PART NUMBER

353S0920

353S0867

BOM OPTION

SMU_SUSPENDREQ_L

REF DES

COMMENTS:

U2850

PERICOM ANALOG SWITCH CRITICAL

10K
5%
1/16W
MF
2 402

SOT23-5

TI

VCC

EI_QREQ_L

TABLE_ALT_HEAD

PART NUMBER

EI_NB_QREQ_L

GND

R28511

NOSTUFF

TABLE_ALT_ITEM

TABLE_ALT_ITEM

353S0924

353S0867

U2850

MAXIM ANALOG SWITCH

PLACE QREQ CIRCUITS BETWEEN CPU AND U3LITE

10K

R2850
1

180

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

13

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOSTUFF
EI_NB_QREQ_L_R

II NOT TO REPRODUCE OR COPY IT

Q2899

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2N3904

5%
1/16W
MF
402

SM
2

SIZE

5%
1/16W
MF
402 2

5%
1/16W
MF
402

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

REV.

051-6482

SHT
NONE

NOTICE OF PROPRIETARY PROPERTY


SMU_QREQ

NOSTUFF

R2899
3

U3LITE APPLE PI

R2898

74LVC1G66

20%
10V
CERM 2
402

30 29 14 6

NOSTUFF
1

U2850

0.1UF

MASTER: GILA

=PP3V3_PWRON_EI

28

OF

C
103

PLACE NEAR PROCESSOR.


PLACE AT PROCESSOR PINS.

35 31 30 29 18 14 7

=PP1V2_EI_CPU
NOSTUFF

NOSTUFF

R2909

R2903

27

EI_CPU_CLK_P

100

46.4 2

1%
1/16W
MF
2 402

1%
1/16W
MF
402

NOSTUFF

R2901
27

EI_CPU_CLK_N

46.4 2
1%
1/16W
MF
402

MORE PROCESSOR DECOUPLING ON PAGES 31 & 32

=PPVCORE_CPU

SYSCLK_TERM
VOLTAGE=0.6V

NOSTUFF
1

36 32 31 7

NOSTUFF

10%
6.3V
2 CERM
402

R2907

C2901

100

0.22UF

1%
1/16W
MF
2 402

20%
6.3V
2 X5R
402

C2953
1UF

C2954

1UF

T22
R22

SYSCLK*

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14

28 14
28 14
28 14
28 14

6 EI_NB_TO_CPU_AD<0>
6 EI_NB_TO_CPU_AD<1>
6 EI_NB_TO_CPU_AD<2>
6 EI_NB_TO_CPU_AD<3>
6 EI_NB_TO_CPU_AD<4>
6 EI_NB_TO_CPU_AD<5>
6 EI_NB_TO_CPU_AD<6>
6 EI_NB_TO_CPU_AD<7>
6 EI_NB_TO_CPU_AD<8>
6 EI_NB_TO_CPU_AD<9>
6 EI_NB_TO_CPU_AD<10>
6 EI_NB_TO_CPU_AD<11>
6 EI_NB_TO_CPU_AD<12>
6 EI_NB_TO_CPU_AD<13>
6 EI_NB_TO_CPU_AD<14>
6 EI_NB_TO_CPU_AD<15>
6 EI_NB_TO_CPU_AD<16>
6 EI_NB_TO_CPU_AD<17>
6 EI_NB_TO_CPU_AD<18>
6 EI_NB_TO_CPU_AD<19>
6 EI_NB_TO_CPU_AD<20>
6 EI_NB_TO_CPU_AD<21>
6 EI_NB_TO_CPU_AD<22>
6 EI_NB_TO_CPU_AD<23>
6 EI_NB_TO_CPU_AD<24>
6 EI_NB_TO_CPU_AD<25>
6 EI_NB_TO_CPU_AD<26>
6 EI_NB_TO_CPU_AD<27>
6 EI_NB_TO_CPU_AD<28>
6 EI_NB_TO_CPU_AD<29>
6 EI_NB_TO_CPU_AD<30>
6 EI_NB_TO_CPU_AD<31>
6 EI_NB_TO_CPU_AD<32>
6 EI_NB_TO_CPU_AD<33>
6 EI_NB_TO_CPU_AD<34>
6 EI_NB_TO_CPU_AD<35>
6 EI_NB_TO_CPU_AD<36>
6 EI_NB_TO_CPU_AD<37>
6 EI_NB_TO_CPU_AD<38>
6 EI_NB_TO_CPU_AD<39>
6 EI_NB_TO_CPU_AD<40>
6 EI_NB_TO_CPU_AD<41>
6 EI_NB_TO_CPU_AD<42>
6 EI_NB_TO_CPU_AD<43>
6 EI_NB_TO_CPU_SR_P<0>
6 EI_NB_TO_CPU_SR_N<0>
6 EI_NB_TO_CPU_SR_P<1>
6 EI_NB_TO_CPU_SR_N<1>

H21
J21
H22
J22
C13
A13
K22
H23
J24
G20
F23
G21
D22
G24
G19
B15
A14
C15
D15
A16
C22
E20
E21
B23
B24
F21
B17
B19
C14
C17
D18
B21
D20
A22
C19
C18
A21
A23
A20
A18
A15
A17
C16
A19

L24
K24
L21
L22

EI_ADI0
EI_ADI1
EI_ADI2
EI_ADI3
EI_ADI4
EI_ADI5
EI_ADI6
EI_ADI7
EI_ADI8
EI_ADI9
EI_ADI10
EI_ADI11
EI_ADI12
EI_ADI13
EI_ADI14
EI_ADI15
EI_ADI16
EI_ADI17
EI_ADI18
EI_ADI19
EI_ADI20
EI_ADI21
EI_ADI22
EI_ADI23
EI_ADI24
EI_ADI25
EI_ADI26
EI_ADI27
EI_ADI28
EI_ADI29
EI_ADI30
EI_ADI31
EI_ADI32
EI_ADI33
EI_ADI34
EI_ADI35
EI_ADI36
EI_ADI37
EI_ADI38
EI_ADI39
EI_ADI40
EI_ADI41
EI_ADI42
EI_ADI43

28 14 6

EI_QACK_L

V21

QACK*

CHKSTOP_L

R20

CHKSTOP*

30 29 27

CPU_HTBEN
6

30 14 6

TP_PSYNCOUT

CPU_HRESET_L

AD17

TBEN

AD14

APSYNCOUT

V20

U2900
CBGA
(1 OF 3)

CPU_SRESET_L

AB4

SRESET*

PROC_THERM_INT_L

V22

THERM_INT*

30
30
30

PROCID0
PROCID1
PROCID2

EI_CLKO
EI_CLKO*

D3

EI_ADO0
EI_ADO1
EI_ADO2
EI_ADO3
EI_ADO4
EI_ADO5
EI_ADO6
EI_ADO7
EI_ADO8
EI_ADO9
EI_ADO10
EI_ADO11
EI_ADO12
EI_ADO13
EI_ADO14
EI_ADO15
EI_ADO16
EI_ADO17
EI_ADO18
EI_ADO19
EI_ADO20
EI_ADO21
EI_ADO22
EI_ADO23
EI_ADO24
EI_ADO25
EI_ADO26
EI_ADO27
EI_ADO28
EI_ADO29
EI_ADO30
EI_ADO31
EI_ADO32
EI_ADO33
EI_ADO34
EI_ADO35
EI_ADO36
EI_ADO37
EI_ADO38
EI_ADO39
EI_ADO40
EI_ADO41
EI_ADO42
EI_ADO43

N3

EI_SRO0
EI_SRO0*
EI_SRO1
EI_SRO1*

L3

30 28 14 6
14 6

30
30
30
30
30

30
30
30
30
30
29 14 6

30
30
30
30
30 14 6
30 14 6

EI_SE
TP_PROC_TRIGGER_OUT
6 TP_AFN
AVPRESET_L
BIMODE_L
C1UNDGLOBAL
C2UNDGLOBAL
DI2_L

LSSDMODE
LSSDSCANENABLE
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE
LSSDSTOPENABLE
MCP_L
6 TP_PSRO1
6 TP_PSRO2
PULSESEL0
PULSESEL1
PULSESEL2
RAMSTOPENABLE
RI_L
SYNCENABLE

N21
N19

AA12
W23
AC24
AC16
AC15
U24

AB5
U19
AD8
AD7
AD11
AD18

V23
V5
AC9
AB11
AC10
AB6
AA5
AB24

H2
K3
L1
M3
K4
K2
H3
H1
G4
F2
F4
E2
G3
B8
D11
E12
A11
B10
C11
C1
C5
B2
D6
A5
A2
D2
D8
C12
A12
B6
B4
C4
C7
A7
C8
C6
A4
A9
C9
A10
C10
A8
A6

L2
G1
F1

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N

6 14 28
6 14 28

EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<11>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<15>
EI_CPU_TO_NB_AD<16>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<26>
EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<43>

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

6 14 28
6 14 28
6 14 28
6 14 28

EI_QREQ_L

6 14 28 30

AB19

CPU_INT_L

6 14 25 30

APSYNCIN

AA10

IIC_SCL
IIC_SDA

AA20

PROCID0
PROCID1
PROCID2

EI_DISABLE

TRIGGER_IN
TRIGGER_OUT
AFN
AVPRESET*
BIMODE*
C1UNDGLOBAL
C2UNDGLOBAL
DI2*
LSSDMODE
LSSDSCANENABLE
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE
LSSDSTOPENABLE
MCP*

10%
6.3V
2 CERM
402

C2948

1UF

10%
6.3V
2 CERM
402

C2956

C2946

C2939
1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2900
1UF

10%
6.3V
2 CERM
402

C2911
1UF

10%
6.3V
2 CERM
402

C2951
1UF

10%
6.3V
2 CERM
402

C2952

1UF

10%
6.3V
2 CERM
402

C2950

C2940

10%
6.3V
2 CERM
402

C2937
1UF

10%
6.3V
2 CERM
402

1UF

C2960

C2959
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2910
1UF

10%
6.3V
2 CERM
402

C2909
1UF

10%
6.3V
2 CERM
402

C2943
1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

C2949
1UF

10%
6.3V
2 CERM
402

1UF

C2938

1UF

C2924
1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2928

C2929

1UF

10%
6.3V
2 CERM
402

C2920
1UF

10%
6.3V
2 CERM
402

C2925

1UF

10%
6.3V
2 CERM
402

C2914
1UF

10%
6.3V
2 CERM
402

C2921

1UF

10%
6.3V
2 CERM
402

C2912
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2915

1UF

10%
6.3V
2 CERM
402

C2913
1UF

10%
6.3V
2 CERM
402

C2944

1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2958
1UF

10%
6.3V
2 CERM
402

C2908
1UF

10%
6.3V
2 CERM
402

C2941

C2942

1UF

C2957
1UF

10%
6.3V
2 CERM
402

C2907
1UF

10%
6.3V
2 CERM
402

C2931

10%
6.3V
2 CERM
402

1UF

C2927

C2935

1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2923

1UF

C2934

C2919

10%
6.3V
2 CERM
402

C2917
1UF

10%
6.3V
2 CERM
402

C2933

C2932
1UF

10%
6.3V
2 CERM
402

1UF

1UF

C2916
1UF

1UF

C2904

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2918

10%
6.3V
2 CERM
402

1UF

C2905

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2906

1UF

1UF

10%
6.3V
2 CERM
402

C2922

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2936

1UF

10%
6.3V
2 CERM
402

1UF

C2926
1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2930

10%
6.3V
2 CERM
402

C2903 1C2902
1UF

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

R2910
0

EI_CPU_SYNC

27

5%
1/16W
MF
402

NOSTUFF

PSRO1
PSRO2
PULSESEL0
PULSESEL1
PULSESEL2
RAMSTOPENABLE
RI*
SYNCENABLE*

18
18

N22

I2CGO

30

AA14

CKTERMDIS_L

30

P20

EI_DISABLE

30

AA19

ATTENTION
GPUL_DBG
JTAGMODE

AD12

TCK
TDI
TDO
TMS
TRST*

AD21

SPARE

BUSCFG0
BUSCFG1
BUSCFG2

AC19
AB16

AA22
W4

AB21
AD13
AD22
W20

AB7
AA9
W22
T19

TP_ATTENTION
GPUL_DBG
JTAGMODE_SPARE2

6
30
30

JTAG_CPU_TCK
JTAG_CPU_TDI
JTAG_CPU_TDO
JTAG_CPU_TMS
JTAG_CPU_TRST_L

18
18
18
18
30

CPU_SPARE

AA13

30
8
30
30
30
30
30

B
PROCESSOR IIC ADDRESS:
80,84

=PP1V2_EI_CPU

R2908

1K

1K

5%
1/16W

5%
1/16W
MF
402

MF

2 402

R2902
1

PLACE BY PROCESSOR PIN.

28

28

30

R2906

1%
1/16W
MF
402

EI_SYNC_FROM_NB

30
30
30
30

49.9 2
1

5%
1/16W
MF
402

30
30
30

CPU_BYPASS_L
PLLLOCK
PLLMULT
PLLRANGE0
PLLRANGE1
PLLTEST
PLLTESTOUT

V24
T20
AA8

Y21

NOSTUFF

C2955
1UF

CPU_APSYNC
I2C_CPU_A_SCL
I2C_CPU_A_SDA

BUSCFG0
BUSCFG1
BUSCFG2

BYPASS*
PLLLOCK
PLLMULT
PLLRANGE0
PLLRANGE1
PLLTEST
PLLTESTOUT

MATCH TO SYSCLK

R2905
CPU_HTBEN

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

AB12

35 31 30 29 18 14 7

30 29 27

14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14

INT*

I2CGO

M18

E3

QREQ*

CKTERMDIS
L19
M19

10%
6.3V
2 CERM
402

R2911

HRESET*

30

30 25

OMIT

CRITICAL

EI_SRI0
EI_SRI0*
EI_SRI1
EI_SRI1*

29 14 8 6

C2945

SYSCLK

E24 EI_CLKI
D24
EI_CLKI*

NEO-10S-REV2
1.8GHZ-76C

28 14 6 EI_NB_TO_CPU_CLK_P
28 14 6 EI_NB_TO_CPU_CLK_N

1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2947

MASTER: GILA
LAST MODIFIED: APR 09, 04

CHKSTOP_L 6

NEO APPLE PI

8 14 29

5%
1/16W
MF
402

CPU_CHKSTOP_L

NOTICE OF PROPRIETARY PROPERTY

NOSTUFF

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

R2904
1

MCP_L

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

6 14 29

5%
1/16W
MF
402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

PROCESSOR LOGIC I/O

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

29

103

SELECT PROCESSOR CLOCK MULTIPLIER. PROCESSOR CLOCK(MHZ)= SYSTCLOCK * PLLMULT.


TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

114S1103

RES,1K OHM,1/16W,5%,0402

R3034

EI_3TO1

114S1103

RES,1K OHM,1/16W,5%,0402

R3018

EI_2TO1

SYSCLK * 12
TABLE_5_ITEM

=PP1V2_EI_CPU

7 14 18 29 30 31 35

SELECT EI BUS DIVIDER. BUS DATA RATE(BPS)= (PROCESSOR CLOCK) / BUSCFG.

R3039
29

JTAGMODE_SPARE2

SYSCLK * 8

TABLE_5_HEAD

35 31 30 29 18 14 7

=PP1V2_EI_CPU

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

29

C1UNDGLOBAL

R3077

R3043

1K

1K

5%
1/16W
MF
402

R3079

R3069

1K

1K

BIMODE_L

29

R3073

DI2_L

29 14 6

RI_L

5%
1/16W
MF
402

R3042

1K

1K

1K

29 25 14 6

CPU_INT_L

1K

LSSDSTOPC2ENABLE

PROC_THERM_INT_L

1K

29

LSSDSTOPC2STARENABLE

1K

2
29

LSSDSTOPENABLE

1K

2
29 28 14 6

EI_QREQ_L

1K

SYNCENABLE

EI_3TO1

114S1103

RES,1K OHM,1/16W,5%,0402

R3024,R3010,R3028

NOSTUFF

114S1103

RES,1K OHM,1/16W,5%,0402

R3024,R3010,R3012

NOSTUFF

114S1103

RES,1K OHM,1/16W,5%,0402

R3008,R3026,R3028

NOSTUFF

114S1103

RES,1K OHM,1/16W,5%,0402

R3008,R3026,R3012

NOSTUFF

114S1103

RES,1K OHM,1/16W,5%,0402

R3008,R3010,R3028

NOSTUFF

114S1103

RES,1K OHM,1/16W,5%,0402

R3008,R3010,R3012

NOSTUFF

PROC / 2
TABLE_5_ITEM

PROC / 3

PROC / 4
PROC / 6
TABLE_5_ITEM

PROC / 8
TABLE_5_ITEM

PROC / 12

PROC / 16
TABLE_5_ITEM

10K

SELECT ELASTIC MODE OR BYPASS.

TABLE_5_HEAD

5%
1/16W
MF
402

PART#

R3099
1

29 18 JTAG_CPU_TMS

10K

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

114S1103

RES,1K OHM,1/16W,5%,0402

R3036

114S1103

RES,1K OHM,1/16W,5%,0402

R3020

TABLE_5_ITEM

BYPASS MODE

NOSTUFF

SELECT PLL FREQUENCY RANGE.

5%
1/16W
MF
402

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

114S1103

RES,1K OHM,1/16W,5%,0402

R3030,R3032

CPU_PLL_LOW

114S1103

RES,1K OHM,1/16W,5%,0402

R3030,R3016

CPU_PLL_HIGH

114S1103

RES,1K OHM,1/16W,5%,0402

R3014,R3032

CPU_PLL_MEDIUM

114S1103

RES,1K OHM,1/16W,5%,0402

R3014,R3016

NOSTUFF

TABLE_5_ITEM

NOSTUFF

R3071
29

PLLTESTOUT

1K

>= 1.8 GHZ *


<= 1.6 GHZ *

TABLE_5_ITEM

5%
1/16W
MF
402

TABLE_5_ITEM

RESERVED

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

114S1103

RES,1K OHM,1/16W,5%,0402

1K

AVPRESET OFF

R3022

114S1103

RES,1K OHM,1/16W,5%,0402

29

RAMSTOPENABLE

1K

SYSTEM CONFIGURATION

=PP1V2_EI_CPU

CPU_SPARE

1K

7 14 18 29 30 31 35
35 31 30 29 18 14 7

R3068

R3067
29

=PP1V2_EI_CPU

10K
5%
1/16W
MF
2 402

5%
1/16W
MF
402

29 28 14 6

EI_SE

29

5%
1/16W
MF
402

29
29
29

PULSESEL0

R3003

29

29

1K

29

5%
1/16W
MF
402

R3083

29

1K

5%
1/16W
MF
1 402

R3005
29

PULSESEL1

1K

1 OMIT

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R3010
1K

OMIT

R3012
1K

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

2 402

R3014
1K

R3016
1K

R3018
1K

R3020
1K

R3022
1K
5%
1/16W
MF

BUSCFG0
BUSCFG1
BUSCFG2
PLLRANGE0
PLLRANGE1
PLLMULT
EI_DISABLE
AVPRESET_L

B
1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

2 402

R3024
1K

5%
1/16W
MF
402

6 14 29

1 OMIT

R3008
1K

R3081
1K

AVPRESET ON

NOSTUFF

* STUFF THESE ON Q45.

5%
1/16W
MF
402
NOSTUFF

R3038

R3055

7 14 18 29 30 31 35

CPU_HRESET_L

EI_2TO1

R3024,R3026,R3012

TABLE_5_ITEM

5%
1/16W
MF
402

29

=PP1V2_EI_CPU

5%
1/16W
MF
402

R3037

5%
1/16W
MF
402

R3024,R3026,R3028

RES,1K OHM,1/16W,5%,0402

TABLE_5_ITEM

R3089
CPU_HTBEN

10K

RES,1K OHM,1/16W,5%,0402

5%
1/16W
MF
402

5%
1/16W
MF
402

29 27

R3053

R3087
I2CGO

1K

114S1103

R3097
29 18 JTAG_CPU_TDI

5%
1/16W
MF
402

5%
1/16W
MF
402

29

10K

R3051

29 14 6

1K

114S1103

TABLE_5_ITEM

5%
1/16W
MF
402

R3085
CPU_SRESET_L

1K

5%
1/16W
MF
402

R3049

5%
1/16W
MF
402

29 25

29 18 JTAG_CPU_TCK

5%
1/16W
MF
402

R3065
29

1K

R3095

R3047
29

5%
1/16W
MF
402

5%
1/16W
MF
402

R3091

NOSTUFF

5%
1/16W
MF
402

LSSDSCANENABLE

5%
1/16W
MF
402

5%
1/16W
MF
402

R3040
1K

29

R3035

GPUL_DBG

5%
1/16W
MF
402

R3075
5%
1/16W
MF
402

1K

1K

TABLE_5_ITEM

R3041

R3033

5%
1/16W
MF
402

1K

1K

R3001

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

CKTERMDIS_L

1K

LSSDMODE

R3031
29

R3061

1K

NOSTUFF

29

R3063
5%
1/16W
MF
402
29

JTAG_CPU_TDO

PLLTEST
NOSTUFF

29

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

R3045

R3093
29 18

1K

5%
1/16W
MF
402

C2UNDGLOBAL

1K

5%
1/16W
MF
402

NOSTUFF

29

JTAG_CPU_TRST_L

NOSTUFF

R3000
JTAG_SEL

29

NOSTUFF

29

5%
1/16W
MF
402

R3009

R3026
1K

R3028
1K

R3030
1K

R3032
1K

R3034
1K

R3036
1K

R3038
1K
5%
1/16W
MF

13

CPU_HRESET

R3007

Q3000
2N7002DW

29 PULSESEL2

SOT-363

1K

5%
1/16W
MF
402

R3002
29 PROCID0

1K

5%
1/16W
MF
402

=PP1V2_EI_CPU

R3004

7 14 18 29 30 31 35

29 PROCID1

R3059

1K

CPU_BYPASS_L

Q3000
2N7002DW

13

CPU_BYPASS

SOT-363

LAST MODIFIED: APR 27, 04

CPU STRAPS

R3006
29
29 PROCID2

MASTER: GILA

5%
1/16W
MF
402

5%
1/16W
MF
2 402

1K

1K

NOSTUFF
1

R3057

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1K

5%
1/16W
MF
2 402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6482

SCALE

NOTICE OF PROPRIETARY PROPERTY

5%
1/16W
MF
402

OF

30

103

=PP1V2_EI_CPU

=PPVCORE_CPU

36 32 31 29 7

7 14 18 29 30 35

VOLTAGE=1.2V
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
=PP2V5_RUN_CPU

8 7 6 3

L3101

VR3100
SOT-25A
1

CPU_AVDD_EN

CONT NOISE

CPU_AVDD_NOISE

2.2

5%
1/16W
MF
603

0805

C3148
0.01UF

1UF

20%
16V
CERM 2
402

20%

2 10V
CERM
603

C3150

AVDD

C3199

1
1

C3102
10UF

C3100
0.22UF

10%
2 6.3V
CERM
402

20%
6.3V
2 X5R
402

10UF

20%
2 6.3V
CERM
805

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

CRITICAL 353S0806

VREG MM1572 2.6V

VR3100

CPU_AVDD_2V6
TABLE_5_ITEM

CRITICAL 353S0886

VREG MM1572 2.7V

VR3100

CPU_AVDD_2V7
TABLE_5_ITEM

CRITICAL 353S0807

VREG MM1572 2.8V

VR3100

C3117 1 C3116 1 C3115


10UF

10UF

10UF

20%
6.3V
2 CERM
805

20%
6.3V
2 CERM
805

20%
6.3V
2 CERM
805

C3114
10UF

20%
6.3V
2 CERM
805

CPU_AVDD_2V8

10%
6.3V
2 CERM
402

CRITICAL

CBGA
(2 OF 3)

VCORE

GND

X105

1UF

10%
6.3V
2 CERM
402

X105

KPGND1

A3
B1
B12
B14
B18
B22
B5
B9
C21
C23
C3
D1
D10
D12
D14
D16
D4
E11
E13
E15
E17
E19
E23
E5
E7
E9
F10
F12
F14
F16
F18
F20
F22
F24
F6
F8
G11
G13
G15
G17
G2
G23
G5
G7
G9
H10
H12
H14
H16
H18
H20
H4
H6
H8
J11
J13
J15
J17
J19
J23
J3
J5
J7
J9
K1
K10
K12
K14
K16
K18
K20
K6
K8
L11
L13
L15
L17
L23
L5
L7
L9
M10
M12
M14
M16
M2
M20
M22
M24
M4
M6
M8
N1
N11
N13
N15
N17
N23
N5
N7
N9
P10
P12
P14
P16

OMIT

GND_SPARE_GND

P1
P11
P13
P15
P17
P19
P21
P23
P3
P5
P7
P9
R10
R12
R14
R16
R18
R4
R6
R8
T1
T11
T13
T15
T17
T21
T23
T3
T5
T7
T9
U10
U12
U14
U16
U18
U2
U20
U22
U4
U6
U8
V1
V11
V13
V15
V17
V19
V3
V7
V9
W10
W12
W14
W16
W18
W2
W24
W6
W8
Y11
Y13
Y15
Y17
Y19
Y22
Y23
Y3
Y5
Y7
Y9
AA16
AA18
AA2
AA24
AA4
AA6
AB1
AB13
AB15
AB17
AB23
AB3
AB9
AC12
AC14
AC18
AC2
AC20
AC22
AC4
AC6
AC8
AD1
AD15
AD19
AD23
AD3
AD5
AD9

31

U2900
CBGA

(3 OF 3)

VCORE

GND

X100

X99

P18
P2
P22
P4
P6
P8
R1
R11
R13
R15
R17
R19
R21
R23
R3
R5
R7
R9
T10
T12
T14
T16
T18
T24
T4
T6
T8
U1
U11
U13
U15
U17
U21
U23
U3
U5
U7
U9
V10
V12
V14
V16
V18
V2
V4
V6
V8
W1
W11
W13
W15
W17
W19
W21
W3
W5
W7
W9
Y10
Y12
Y14
Y16
Y18
Y2
Y20
Y24
Y4
Y6
Y8
AA11
AA15
AA17
AA21
AA23
AA3
AA7
AB10
AB14
AB18
AB2
AB20
AB22
AB8
AC1
AC11
AC13
AC17
AC21
AC23
AC3
AC5
AC7
AD10
AD16
AD2
AD20
AD24
AD4
AD6

GND_Z_OUT

31

GND_Z_SENSE

31

10%
2 6.3V
CERM
402

C3113

10%
6.3V
2 CERM
402

C3105
1UF

C3103
1UF

10%
6.3V
2 CERM
402

C3126

1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

NET_SPACING_TYPE=PROC_DIFF
31 GND_Z_SENSE

10%
2 6.3V
CERM
402

C3108
1UF

C3118
1UF

10%
2 6.3V
CERM
402

C3121

C3119
1UF

10%
6.3V
2 CERM
402

C3124

1UF

10%
2 6.3V
CERM
402

C3129
1UF

10%
6.3V
2 CERM
402

C3122
1UF

10%
6.3V
2 CERM
402

1UF

1UF

C3137
1UF

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3134

1UF

10%
6.3V
2 CERM
402

C3135

10%
2 6.3V
CERM
402

C3141
1UF

C3132
1UF

C3133
1UF

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

C3146

1UF

1UF

C3130

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3145

10%
6.3V
2 CERM
402

1UF

C3123
1UF

1UF

1UF

C3131

10%
6.3V
2 CERM
402

C3138

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

C3125

10%
6.3V
2 CERM
402

C3136

R3129

10%
6.3V
2 CERM
402

R3131
31 GND_SPARE_GND1

1UF

C3139
1UF

10%
6.3V
2 CERM
402

C3142

1UF

10%
2 6.3V
CERM
402

C3140
1UF

10%
2 6.3V
CERM
402

5%
1/16W
MF
402

C3120

1UF

C3104

C
1

R3127
31 GND_Z_OUT

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C3128

C3107
1UF

1UF

1UF

TDIODE_NEG 6 36
DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL

C3110

10%
2 6.3V
CERM
402

C3127

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3109
1UF

1UF

T2

GND_CPU_AVDD

XW3100
SM

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

1UF

KPGND2

AA1

C3112
1UF

CRITICAL

1UF

2 OMIT

C3106

KPVDD2

U2900

R24

R2

Y1

KPVDD1
OMIT

AGND

C3111
1UF

1
A1
A24
B11
B13
B16
B20
B3
B7
C2
C20
C24
D13
D17
D19
D21
D23
D5
D7
D9
E1
E10
E14
E16
E18
E22
E4
E6
E8
F11
F13
F15
F17
F19
F3
F5
F7
F9
G10
G12
G14
G16
G18
G22
G6
G8
H11
H13
H15
H17
H19
H24
H5
H7
H9
J1
J10
J12
J14
J16
J18
J2
J20
J4
J6
J8
K11
K13
K15
K17
K19
K21
K23
K5
K7
K9
L10
L12
L14
L16
L18
L20
L4
L6
L8
M1
M11
M13
M15
M17
M21
M23
M5
M7
M9
N10
N12
N14
N16
N18
N2
N20
N24
N4
N6
N8

1UF

20%
2 6.3V
CERM
805

GND

C3149

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SM

DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=10MIL
TDIODE_POS 36
MIN_NECK_WIDTH=8MIL

PP2V5_RUN_CPU_AVDD_R_L

P24

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=2.5V

2
CPU_AVDD_2V6&CPU_AVDD_2V7&CPU_AVDD_2V8 1
CPU_AVDD_2V6&CPU_AVDD_2V7&CPU_AVDD_2V8
1
1

PP2V5_RUN_CPU_AVDD_R

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP2V5_RUN_CPU_AVDD

VOUT

VIN

35

R3101

MM1572JN

NET_SPACING_TYPE=PROC_DIFF

60-OHM-EMI

5%
1/16W
MF
603

OMIT

=PP5V_RUN_CPU

2.2

NEO-10S-REV2
1.8GHZ-76C

NOSTUFF

R3132

NEO-10S-REV2
1.8GHZ-76C

C3147
1UF

5%
1/16W
MF
402

C3144
1UF

10%
6.3V
2 CERM
402

C3143
1UF

10%
6.3V
2 CERM
402

5%
1/16W
MF
402

MASTER: GILA
LAST MODIFIED: JULY 9, 04

36 32 31 29 7

CPU POWER AND BYPASS

NOSTUFF

R3103

=PPVCORE_CPU

2
NOSTUFF

5%
1/16W
MF
402
NOSTUFF

0.22UF

R3105
1

5%
1/16W
MF
402

C3101

KPVDD2
MIN_LINE_WIDTH=10MIL

NOTICE OF PROPRIETARY PROPERTY

33 36

MIN_NECK_WIDTH=8MIL
DIFFERENTIAL_PAIR=P_KP2
NET_SPACING_TYPE=PROC_DIFF

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20%
6.3V
2 X5R
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


KPGND2
MIN_LINE_WIDTH=10MIL

II NOT TO REPRODUCE OR COPY IT


33 36

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

MIN_NECK_WIDTH=8MIL
DIFFERENTIAL_PAIR=P_KP2
NET_SPACING_TYPE=PROC_DIFF

SIZE

PLACE ALL THESE PARTS VERY CLOSE TO U2900

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

31

103

D
36 31 29 7

=PPVCORE_CPU

C3222
1UF

10%
6.3V
2 CERM
402

C3293

1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3294
1UF

10%
6.3V
2 CERM
402

C3295

C3296
1UF

10%
6.3V
2 CERM
402

C3297

10%
2 6.3V
CERM
402

C3298
1UF

10%
6.3V
2 CERM
402

C3299

10%
6.3V
2 CERM
402

C3202
1UF

10%
6.3V
2 CERM
402

C3203
1UF

10%
2 6.3V
CERM
402

C3271

10%
2 6.3V
CERM
402

C3270
1UF

10%
6.3V
2 CERM
402

C3282

C3281
1UF

10%
6.3V
2 CERM
402

C3284

C3283
1UF

10%
6.3V
2 CERM
402

C3292
1UF

10%
2 6.3V
CERM
402

C3261

10%
2 6.3V
CERM
402

C3264

1UF

10%
2 6.3V
CERM
402

C3266

10%
6.3V
2 CERM
402

C3276

1UF

10%
2 6.3V
CERM
402

C3277

C3279

1UF

C3280

C3275

10%
6.3V
2 CERM
402

C3291

1UF

C3290
1UF

10%
2 6.3V
CERM
402

C3235

10%
2 6.3V
CERM
402

C3236
1UF

10%
6.3V
2 CERM
402

C3239

10%
6.3V
2 CERM
402

C3240
1UF

10%
6.3V
2 CERM
402

C3252

10%
2 6.3V
CERM
402

C3253
1UF

10%
6.3V
2 CERM
402

C3257

10%
6.3V
2 CERM
402

C3258
1UF

10%
6.3V
2 CERM
402

C3288
1UF

10%
2 6.3V
CERM
402

C3237

10%
2 6.3V
CERM
402

C3238
1UF

10%
6.3V
2 CERM
402

C3250

C3251
1UF

10%
6.3V
2 CERM
402

C3254

C3255
1UF

10%
6.3V
2 CERM
402

C3287
1UF

10%
2 6.3V
CERM
402

C3226

10%
2 6.3V
CERM
402

C3227

1UF

10%
2 6.3V
CERM
402

C3231

10%
6.3V
2 CERM
402

C3243

1UF

10%
2 6.3V
CERM
402

C3244

C3248

1UF

C3246

C3249

C3247
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C3286
1UF

10%
2 6.3V
CERM
402

C3285
1UF

10%
2 6.3V
CERM
402

C3245

10%
2 6.3V
CERM
402

C3256
1UF

10%
6.3V
2 CERM
402

C3289

1UF

C3201
1UF

10%
6.3V
2 CERM
402

C3206

1UF

C3207
1UF

10%
6.3V
2 CERM
402

C3210

1UF

C3211
1UF

10%
6.3V
2 CERM
402

C3214
1UF

10%
2 6.3V
CERM
402

C3267
1UF

10%
2 6.3V
CERM
402

C3278
1UF

10%
6.3V
2 CERM
402

C3204
1UF

10%
2 6.3V
CERM
402

C3205
1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3234

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3223

10%
2 6.3V
CERM
402

1UF

10%
2 6.3V
CERM
402

C3200

10%
6.3V
2 CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

1UF

C3242

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

1UF

1UF

10%
6.3V
2 CERM
402

C3241

10%
2 6.3V
CERM
402

1UF

C3229

C3212
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C3228

10%
2 6.3V
CERM
402

1UF

C3225

10%
6.3V
2 CERM
402

C3230

1UF

1UF

10%
6.3V
2 CERM
402

C3224

10%
2 6.3V
CERM
402

1UF

C3215

10%
6.3V
2 CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3216
1UF

1UF

1UF

10%
2 6.3V
CERM
402

C3233
1UF

1UF

10%
2 6.3V
CERM
402

C3232

1UF

1UF

10%
2 6.3V
CERM
402

C3217
1UF

1UF

1UF

1UF

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3274

10%
2 6.3V
CERM
402

1UF

C3273

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

1UF

1UF

10%
6.3V
2 CERM
402

C3272

10%
2 6.3V
CERM
402

1UF

C3263

C3218
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C3262

10%
2 6.3V
CERM
402

1UF

C3260

10%
6.3V
2 CERM
402

C3265

1UF

1UF

10%
6.3V
2 CERM
402

C3259

10%
2 6.3V
CERM
402

1UF

C3219

10%
6.3V
2 CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3220
1UF

1UF

1UF

10%
2 6.3V
CERM
402

C3269
1UF

1UF

10%
2 6.3V
CERM
402

C3268

1UF

1UF

10%
2 6.3V
CERM
402

C3221

C3208
1UF

10%
2 6.3V
CERM
402

C3209
1UF

10%
6.3V
2 CERM
402

C3213
1UF

10%
2 6.3V
CERM
402

MASTER: GILA
LAST MODIFIED: APR 09, 04

PROC DECOUPLING

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

32

OF

C
103

7
33 7

=PP12V_RUN_CPU

C3310

R3329

U3310_BST_R

33

C3319

R3390

1UF

8 6
8 6
8 6
8 6
8 6
8 6

14 VID0
13 VID1
12 VID2

CPU_VID_R<0>
CPU_VID_R<1>
CPU_VID_R<2>
CPU_VID_R<3>
CPU_VID_R<4>
CPU_VID_R<5>

3 OS1
2 OS2
1 OS3
24 OS4

SC2643_OSCREF

R3391
0

5%
1/16W
MF
2 402

AUX2

AUX3

33

SC2643_DACSTEP

GSENSE 6

R3313
20.5K

20%
2 10V
CERM
402

AGND

U3310_BST

3 BST

SYS_POWERUP_L

VPN 5

R3301
30K

5%
1/16W
MF
2 402

34

SOT23

R3323

330PF

20.5K

10%
50V
2 CERM
402

1%
1/16W
MF
2 402

C3313
1UF

C3304

NOSTUFF

R3314
0.0082UF
10%
25V
X7R
402

20.5K

1%
1/16W
MF
2 402

NOSTUFF

C3305 R3315
20.5K
0.0082UF 1%

10%
25V
2 X7R
402

C3306 R3318
20.5K
0.0082UF

1%
1/16W
MF
2 402

10%
25V
2 X7R
402

1/16W
MF
2 402

4PHASE
1

SC2643_VCC

4.99K2
1%
1/16W
MF
402

FOR REMOTE SENSE

R3360
10K

U3320_BST_R

XW3300
SM
33

SC2643_AGND

VCORE_SENSE_VOUT

SC1211

OUT2

20%
16V
2 CERM
1206

1K

2.2

U3320_BST

VPN 5

330

R3320
1

SOT23

1UF

PPVCORE_CPU

33

PLACE REGULATOR SENSE POINTS AT DESIGNATED LOCATIONS.

UNDER PROCESSOR

R3336
1

5%
1/16W
MF
402

R3337
1

NOSTUFF
NEAR SIDE

FAR SIDE

NOSTUFF

36 31

KPGND2

R3342
1

TH-VERT

VCORE_SENSE_GND

1%
1W
MF
2512

6 33

DIFFERENTIAL_PAIR=P_SENSE_CORE
MIN_LINE_WIDTH=10MIL

C3326

0.0047UF

10%
25V
2 CERM
402

PN2
PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

376S0130

ON SEMI FET

Q3310,Q3320

ON_SEMI

376S0146

ON SEMI FET

Q3311,Q3321

ON_SEMI

114S2325

RES,232K,1%,402

R3328

4PHASE

114S3325

RES,332K,1%,402

R3328

3PHASE

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

OMIT
3

V+

SOT23-5

OUT

CORE_ISNS_P

XW3303
SM
1

R3345

100K 2

SCALE

COUNT

2.73224 A/V

.00675 A/COUNT

CPU_SENSE_I 13

CPU VREG
NOTICE OF PROPRIETARY PROPERTY

ADC IS 10BIT 0 TO 1023


0 TO 2.5V

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

C3331

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

20%
2 6.3V
CERM
805

1%
1/16W
MF
2 402

OMIT

GND_SMU_AVSS

XW3301
SM
2

CORE_ISNS_M

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
8 13 33 36

APPLE COMPUTER INC.

6 36

DRAWING NUMBER

SHT
NONE

REV.

051-6482

D
SCALE

SOT23

10UF

73.2K

5%
1/16W
MF
402

GND

D3300
BAS16

R3344
CPU_SENSE_I_R

3 NOSTUFF

6 36

OMIT

INA138
5

INA138_OUT

U3301

=PP3V3_RUN_CPU

XW3304
SM

VIN+ VIN-

5%
1/16W
MF
402

BOM OPTION
TABLE_5_ITEM

CURRENT SENSE
PLACE R3344 AND C3331 BY SMU

5%
1/16W
MF
402

C3326_1

KEEP SHORTS NEXT TO U3301

MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

R3341
0

6 33 34

VOLTAGE=12V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

0.0252

2 PP12V_CPU_R

NOSTUFF

KPVDD2
CPU SENSE SIDE

5%
1/16W
MF
402

5%
1/16W
MF
402
36 31

R3340
1

33 7

MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

PP12V_CPU

R3343

=PP12V_RUN_CPU 1UH-20A-4.5MOHM

R3339

NOSTUFF

1800UF

20%
2 6.3V
ELEC
TH-KZJ

TABLE_5_HEAD

L3300

6 33

DIFFERENTIAL_PAIR=P_SENSE_CORE

NOSTUFF

5%
1/16W
MF
402

5%
1/16W
MF
402

R3338
1

1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3333

CRITICAL

VCORE_SENSE_VOUT
MIN_LINE_WIDTH=10MIL

5%
1/16W
MF
402
NOSTUFF

5%
1/10W
FF
2 805

10%
50V
2 CERM
402

C3324

C3327

20%
50V
2 CERM
402

CONNECT BETWEEN THE INDUCTOR & BULK CAPS.

R3335

TO-252

0.001UF

6 7 33 34 35

0.0022UF

C3328

R3321

V30289

C3325

6 7 33 34 35

EXTRA_C
1

Q3321
1
G
S 3

AUX2

PPVCORE_CPU

2
TH1

20%
2 6.3V
ELEC
TH-KZJ

NOSTUFF
1

33

XW3302
SM

SC2643_OUTSEN_R

1%
1/16W
MF
402

MIN_LINE_WIDTH=10MIL

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

1800UF

U3320_BG

5%
1/16W
MF
2 402

20%
2 16V
CERM
1206

2
10% 16V
X7R 402

R3327

MIN_NECK_WIDTH=8MIL

CRITICAL
D 4 VISHAY

100

OMIT

PPVCORE_CPU

PN2

5%
1/16W
MF
402

R3322

C3323

L3320

0.6UH-24A
33

C3309

35 34 33 7 6

5%
1/16W
MF
2 402

R3325_2

0.015UF

1.5K 2

TO-252

S 3
10K

VPN2

COUNT
.01464 V/COUNT

ADC IS 10BIT 0 TO 1023


0 TO 2.5V

V30284

R3351

U3320_VREG

PLACE R3325 CLOSE TO INDUCTOR OUTPUT LEAD.


NOSTUFF

1
G
1

5%
1/16W
MF
2 402

1210

Q3320

U3320_TG

D3320
BAS16

R3324

8 13 33 36

10%
16V

2 CERM

CRITICAL

THMPAD

5%
1/16W
MF
402

SC2643_OUTSEN

GND_SMU_AVSS

10UF

20%
16V
ELEC
TH-KZJ

D 4 VISHAY

20%
6.3V
2 CERM
805

1%
1/16W
MF
2 402

C3322

C3303
10UF

2K

6 V/V

TG 2

3 BST

R3361

SCALE
BG 8

VREG 7

1 DRN

5%
1/16W
MF
603

1UF

NOSTUFF

C3330

R3326

R3325

SOIC

4 CO

NOSTUFF

C3321
1000UF

6 33

CPU_SENSE_V 13
1

U3320
6 VIN

33

100K 2

2
1

1%
1/16W
MF
2 402

R3308
5%
1/16W
MF
402

PP12V_CPU

R3306

1%
1/16W
MF
402

6 33

301

PPVCORE_CPU

PP12V_CPU

U3320_DRN

OMIT

34 33 6

1UF

33

10%
10V
CERM
402

PLACE NEXT TO SMU

PP12V_CPU
1

34 33 6

1%
1/16W
MF
402

0.068UF

VOLTAGE SENSE

20%
16V
CERM
1206

C3308

0.0047UF

PN1

1%
1/16W
MF
2 402

C3316

10%
2 25V
CERM
402

34 33 6

C3320

261

DIFFERENTIAL PAIR

1800UF

C3316_1

10%
50V
2 CERM
402

NOSTUFF

20.5K

SC2643_OS_HUB

NOSTUFF

C3315

5%
1/16W
MF
2 402

R3304

C3332

20%
2 6.3V
ELEC
TH-KZJ

5%
1/10W
FF
2 805

SC2643_AGND

1800UF

20%
2 6.3V
ELEC
TH-KZJ

TO-252

0.001UF

33

C3317

R3311

V30289
S 3

C3314

Q3311
1
G

6 7 33 34 35

NOSTUFF

C3318

20%
50V
2 CERM
402

R3302

VCORE_SENSE_GND

33

CRITICAL

1800UF

0.0022UF

33

PPVCORE_CPU

2
TH1

20%
2 6.3V
ELEC
TH-KZJ

35 34 33 7 6

C3307 1R3319
0.0082UF

R3305

U3310_BG

AUX1

NOSTUFF

10%
25V
2 X7R
402

PN1

CRITICAL
D 4 VISHAY

1
33

SC2643_OS4
NOSTUFF

5%
1/16W
MF
2 402

C3302

33

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

2 402

5%
1/16W
MF
402

R3312

20%
16V
2 CERM
1206

CRITICAL

L3310

0.6UH-24A

NOSTUFF

C3302_1

5%
1/16W
MF
603

1
33

S 3

5%
1/16W
MF

R3310

VPN1

33

SC2643_VCC

TO-252

10K

100

2.7M 2

V30284

R3350

6 7 10 11 13

R3303
1

1
G
1

THMPAD

1UF

Q3310

U3310_TG

TG 2

10%
2 6.3V
CERM
402

SC2643_AGND

SC2643_ERROUT

1%
1/16W
MF
2 402

C3301

NOSTUFF

1%
1/16W
MF
2 402

20.5K

1%
1/16W
MF
2 402

232K

R3317

20.5K

1%
1/16W
MF
2 402

C3300

18

R3316

SM

0.1UF

4PHASE

1 DRN

D3310
BAS16

2N7002

1210

CRITICAL

Q3312

10%
16V

2 CERM

D 4 VISHAY

U3310_VREG

AUX4

BG 8

VREG 7

5%
1/16W
MF
603

VRM_EN

5%
1/16W
MF
402

R3328

34

R3300

FB 7

SC2643_AGND
33

20%
2 16V
CERM
1206

34

OMIT

C3329 R3307
2.2
1UF

33

1.5K 2

SOIC

4 CO
1

SC2643_PGOOD

DACSTEP 8

OUT1

33

C3312
10UF

20%
16V
ELEC
TH-KZJ

U3310

PP12V_CPU

6 VIN

ERROUT 5

17 OSCREF

SC1211

34

CRITICAL
1

C3311
1000UF

25 27
34 33 6

U3300_BGOUT

BGOUT 4

23 OUTSEN

3PHASE

OUT1
OUT2
OUT3
OUT4

OUT4 22

PGOOD 16

SYS_SLEWING_L 13

33

OUT1 19
OUT2 20
OUT3 21

TSSOP

11 VID3
10 VID4
15 VID5

SC2643_OS1
SC2643_OS2
SC2643_OS3

AUX1

5%
1/16W
MF
2 402

U3300
SC2643VX

U3310_DRN

5%
1/16W
MF
402

9
VCC

20%
16V
2 CERM
1206

3PHASE

SC2643_AGND

PP12V_CPU

20%
16V
CERM
1206

R3330

CRITICAL

5%
1/16W
MF
2 402

33

34 33 6

1UF
SC2643_VCC

10

33

OF

C
103

PP12V_CPU

C3410

1UF
U3410_BST_R

2
2

20%
16V
CERM
1206

C3411

1000UF

20%
16V
ELEC
TH-KZJ

20%
16V
ELEC
TH-KZJ

C3412

1000UF

5
6 33 34

C3468
10UF
10%
16V

35 34 33 7 6

PPVCORE_CPU

2 CERM
1210

EXTRA_C

U3410_DRN

EXTRA_C

C3433
10UF

34 33 6

33

SC1211

PP12V_CPU

6 VIN

OUT3

4 CO

R3423
1
1

C3470

2.2

U3410_BST

20%
2 16V
CERM
1206

BG 8

1 DRN

TG 2

3 BST

VPN 5

1
G

L3410

R3410

D3410
BAS16

SOT23

0.6UH-24A

5%
1/16W
MF
2 402

VPN3

1UF

20%
16V
2 CERM
1206

33

1
G

1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3472

1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3473
1800UF

20%
2 6.3V
ELEC
TH-KZJ

TO-252

20%
6.3V
2 CERM
1206

10%
2 25V
CERM
402

C3414

C3441

20%
6.3V
2 CERM
1206

C3446

10UF

20%
2 6.3V
CERM
1206

1UF
2
2

20%
16V
CERM
1206

NOSTUFF

C3421

1000UF

20%
16V
ELEC
TH-KZJ

20%
16V
ELEC
TH-KZJ

4PHASE

C3422

1000UF

20%
6.3V
2 CERM
1206

C3435
10UF

20%
2 6.3V
CERM
1206

C3450

C3460
10UF

20%
2 6.3V
CERM
1206

C3465

20%
6.3V
2 CERM
1206

EXTRA_C

C3436

20%
2 6.3V
CERM
1206

C3466

10UF

20%
2 6.3V
CERM
1206

10UF

EXTRA_C

C3439
10UF

C3401
10UF

20%
6.3V
2 CERM
1206

C3440

10UF

20%
2 6.3V
CERM
1206

20%
6.3V
2 CERM
1206

EXTRA_C

C3402

10UF

20%
2 6.3V
CERM
1206

C3447
10UF

10UF

EXTRA_C

C3405
10UF

20%
6.3V
2 CERM
1206

C3400

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3467
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3464

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3463
10UF

20%
6.3V
2 CERM
1206

10UF

C3403
10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

EXTRA_C
1

10UF

20%
2 6.3V
CERM
1206

EXTRA_C

C3462

10UF

20%
6.3V
2 CERM
1206

EXTRA_C

C3456
10UF

10%
16V
CERM
1210

C3449
10UF

EXTRA_C

C3469
10UF

C3455

20%
6.3V
2 CERM
1206

4PHASE

C3420

10UF

10UF

EXTRA_C

10UF

6 33 34

C3442

C3459

EXTRA_C
1

10UF

EXTRA_C

PP12V_CPU

20%
6.3V
2 CERM
1206

20%
2 6.3V
CERM
1206

EXTRA_C
1

PN3

10UF

10UF

10UF

20%
2 6.3V
CERM
1206

U3420_BST_R

C3430

20%
2 6.3V
CERM
1206

EXTRA_C

C3445

20%
6.3V
2 CERM
1206

0.0047UF

C3438

20%
2 6.3V
CERM
1206

10UF

C3416

EXTRA_C

C3461

20%
6.3V
2 CERM
1206

EXTRA_C

C3444

EXTRA_C

C3416_1
1

C3437
10UF

20%
2 6.3V
CERM
1206

5%
1/10W
FF
2 805

10%
2 50V
CERM
402

10UF

10UF

0.001UF

10UF

20%
6.3V
2 CERM
1206

EXTRA_C

20%
50V
2 CERM
402
34

C3429
10UF

EXTRA_C

C3443

20%
6.3V
2 CERM
1206

V30289

C3415

C3418

C3432

20%
2 6.3V
CERM
1206

10UF

R3411

NOSTUFF

AUX3

6 7 33 34 35

S 3
1

C3417

20%
2 6.3V
ELEC
TH-KZJ

Q3411

0.0022UF

CRITICAL
D 4 VISHAY

5%
1/16W
MF
2 402

C3413

TH1

1800UF

U3410_BG

EXTRA_C

PPVCORE_CPU

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

100

5%
1/16W
MF
402

U3410_VREG

R3412

PN3

34

EXTRA_C
1

EXTRA_C

C3434

20%
2 6.3V
CERM
1206

TO-252

R3450
10K

20%
6.3V
2 CERM
1206

10UF

V30284
S 3

C3431

EXTRA_C
1

Q3410

U3410_TG

THMPAD

CRITICAL

D 4 VISHAY

VREG 7

5%
1/16W
MF
603

1UF

SOIC

10UF

20%
6.3V
2 CERM
1206

U3410

C3448

10UF

20%
2 6.3V
CERM
1206

C3406

10UF

20%
2 6.3V
CERM
1206

C3404
10UF

20%
2 6.3V
CERM
1206

U3420_DRN
EXTRA_C
1

U3420
34 33 6

33

SC1211

PP12V_CPU

6 VIN

OUT4

4 CO

4PHASE

R3424
1

4PHASE
1

1UF

U3420_BST

10UF

BG 8

TG 2

3 BST

VPN 5

U3420_VREG
VPN4

4PHASE
1

C3423
1UF

33

4PHASE
1

C3424

TO-252

C3425

10%
2 50V
CERM
402

NOSTUFF
1

C3427

C3428
1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3474
1800UF

20%
2 6.3V
ELEC
TH-KZJ

EXTRA_C

C3409
10UF

20%
6.3V
2 CERM
1206

C3407
10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

C3454
10UF

20%
2 6.3V
CERM
1206

C3452
10UF

20%
2 6.3V
CERM
1206

C3419

10UF

20%
2 6.3V
CERM
1206

C3408
10UF

20%
2 6.3V
CERM
1206

6 7 33 34 35

C3475

1800UF

20%
2 6.3V
ELEC
TH-KZJ

R3421

C3426_1
4PHASE
1

C3426
0.0047UF

TABLE_5_HEAD

PART#

10%
2 25V
CERM
402

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

376S0130

ON SEMI FET

Q3410

ON_SEMI

376S0146

ON SEMI FET

Q3411

ON_SEMI

376S0130

ON SEMI FET

Q3420

4PHASE_ON

376S0146

ON SEMI FET

Q3421

4PHASE_ON

376S0204

VISHAY FET

Q3420

4PHASE_VISH

376S0207

VISHAY FET

Q3421

4PHASE_VISH

TABLE_5_ITEM

20%
50V
2 CERM
402
34

5%
1/10W
FF
2 805

NOSTUFF

0.001UF

10UF

V30289

0.0022UF

AUX4

EXTRA_C

C3451

4PHASE

Q3421
1
G
S 3

20%
16V
2 CERM
1206

PPVCORE_CPU

2
TH1

20%
2 6.3V
ELEC
TH-KZJ

CRITICAL
D 4 OMIT

U3420_BG

5%
1/16W
MF
2 402

1800UF

5%
1/16W
MF
402

4PHASE

100

20%
2 6.3V
CERM
1206

0.6UH-24A
PN4

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R3422

4PHASE

34

2 402

C3458
10UF

L3420

5%
1/16W
MF

4PHASE

SOT23

TO-252

R3451
10K

20%
6.3V
2 CERM
1206

EXTRA_C

V30284

S 3
14PHASE

R3420

D3420
BAS16
1

1
G

3 4PHASE

C3453

Q3420

U3420_TG

THMPAD

10UF

20%
6.3V
2 CERM
1206

CRITICAL
D 4 OMIT

4PHASE VREG 7

1 DRN

5%
1/16W
MF
603

C3471

20%
16V
2 CERM
1206

2.2

SOIC

EXTRA_C

C3457

TABLE_5_ITEM

TABLE_5_ITEM

PN4

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CPU VREG
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

34

OF

C
103

D
35 34 33 7 6

PPVCORE_CPU
CRITICAL
EXTRA_C
1

C3500
10UF

20%
6.3V
2 CERM
1206

PPVCORE_CPU
31 30 29 18 14 7

6 7 33 34 35

PP2V5_RUN_CPU_AVDD_R

20%
2 6.3V
CERM
1206

DS3502
SM
1

C3524
10UF

10BQ040

20%
6.3V
2 CERM
1206

NOSTUFF

DS3501
SM
2

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3523
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3535
10UF

10BQ040

20%
2 6.3V
CERM
1206

C3511
10UF

20%
2 6.3V
CERM
1206

10UF

20%
6.3V
2 CERM
1206

C3510
10UF

20%
2 6.3V
CERM
1206

C3522
10UF

20%
6.3V
2 CERM
1206

20%
2 6.3V
CERM
1206

C3533
10UF

20%
2 6.3V
CERM
1206

C3521
10UF

20%
6.3V
2 CERM
1206

C3546
10UF

20%
6.3V
2 CERM
1206

C3544
10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

C3532
10UF

20%
2 6.3V
CERM
1206

C3557
10UF

20%
2 6.3V
CERM
1206

C3555
10UF

20%
2 6.3V
CERM
1206

10UF

20%
6.3V
2 CERM
1206

C3568
10UF

20%
6.3V
2 CERM
1206

C3566
10UF

20%
6.3V
2 CERM
1206

C3554
10UF

20%
2 6.3V
CERM
1206

C3565
10UF

20%
6.3V
2 CERM
1206

C3579
10UF

20%
2 6.3V
CERM
1206

C3577
10UF

20%
2 6.3V
CERM
1206

C3590
10UF

20%
6.3V
2 CERM
1206

20%
2 6.3V
CERM
1206

C3502
10UF

20%
2 6.3V
CERM
1206

20%
6.3V
2 CERM
1206

20%
2 6.3V
CERM
1206

C3531
10UF

20%
2 6.3V
CERM
1206

C3588
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3599
10UF

20%
2 6.3V
CERM
1206

C3587

C3598
10UF

20%
2 6.3V
CERM
1206

C3507
10UF

20%
2 6.3V
CERM
1206

C3589
10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3506
10UF

20%
2 6.3V
CERM
1206

C3519
10UF

20%
6.3V
2 CERM
1206

C3530
10UF

20%
2 6.3V
CERM
1206

C3542
10UF

20%
6.3V
2 CERM
1206

C3553
10UF

20%
2 6.3V
CERM
1206

C3518
10UF

20%
6.3V
2 CERM
1206

C3529
10UF

20%
2 6.3V
CERM
1206

C3517
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3564
10UF

20%
6.3V
2 CERM
1206

C3575
10UF

20%
2 6.3V
CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3528
10UF

20%
2 6.3V
CERM
1206

C3586
10UF

20%
6.3V
2 CERM
1206

C3516
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3541
10UF

20%
6.3V
2 CERM
1206

C3540
10UF

20%
6.3V
2 CERM
1206

C3552
10UF

20%
2 6.3V
CERM
1206

C3563
10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

C3574
10UF

20%
2 6.3V
CERM
1206

C3551
10UF

20%
2 6.3V
CERM
1206

C3585
10UF

20%
6.3V
2 CERM
1206

C3550
10UF

20%
2 6.3V
CERM
1206

10UF

EXTRA_C
1

C3527
10UF

20%
2 6.3V
CERM
1206

C3538
10UF

20%
6.3V
2 CERM
1206

C3504
10UF

EXTRA_C
1

C3549
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3515
10UF

20%
6.3V
2 CERM
1206

C3597
10UF

20%
2 6.3V
CERM
1206

C3596
10UF

20%
2 6.3V
CERM
1206

C3514
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3526
10UF

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3537
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3536
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3525
10UF

20%
2 6.3V
CERM
1206

C3548
10UF

EXTRA_C
1

C3547
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3562
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3573
10UF

20%
2 6.3V
CERM
1206

C3584
10UF

20%
6.3V
2 CERM
1206

C3561

C3560
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3572
10UF

20%
2 6.3V
CERM
1206

C3583
10UF

20%
6.3V
2 CERM
1206

C3571
10UF

20%
2 6.3V
CERM
1206

C3582
10UF

20%
6.3V
2 CERM
1206

C3570
10UF

10UF

EXTRA_C
1

C3595
10UF

20%
2 6.3V
CERM
1206

C3569
10UF

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3558

20%
6.3V
2 CERM
1206

EXTRA_C
1

EXTRA_C
1

C3559

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3581
10UF

20%
6.3V
2 CERM
1206

C3580
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3503
10UF

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3556

20%
6.3V
2 CERM
1206

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

C3539
10UF

EXTRA_C
1

20%
6.3V
2 CERM
1206

EXTRA_C
1

EXTRA_C
1

C3505

C3567
10UF

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

C3578
10UF

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

C3576
10UF

EXTRA_C
1

10UF

EXTRA_C
1

C3508

C3501
10UF

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

20%
6.3V
2 CERM
1206

EXTRA_C
1

EXTRA_C
1

C3543

C3545
10UF

EXTRA_C
1

EXTRA_C
1

C3520
10UF

EXTRA_C

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

C3509
10UF

EXTRA_C
1

EXTRA_C

C3534

EXTRA_C
1

EXTRA_C

2
1

10BQ040

C3513
10UF

31

NOSTUFF

C3512

EXTRA_C

=PP1V2_EI_CPU

DS3500
SM

EXTRA_C
1

EXTRA_C
1

C3594
10UF

20%
2 6.3V
CERM
1206

C3593
10UF

20%
2 6.3V
CERM
1206

C3592
10UF

C3591
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

CPU VREG OUTPUT CAPS

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

35

OF

C
103

NOSTUFF
7

=PP5V_PWRON_CPU

DS3602
SM
1

MBR0530

=PP5V_ALL_CPU

R3602

MIN_LINE_WIDTH=15MIL

C3603 1 C3604

2.2UF

2.2UF

C3605

2.2UF

20%
10V
2 CERM
805

20%
10V
2 CERM
805

XW3601
SM
1

DAVDD

36

DAGND

36

MIN_NECK_WIDTH=10MIL

5%
1/16W
MF
603

C3600
2.2UF

20%
10V
2 CERM
805

20%
10V
2 CERM
805

MIN_LINE_WIDTH=15MIL

OMIT

MIN_NECK_WIDTH=10MIL

XW3600, R3602, AND DS3602 MUST BE PLACED CLOSE TO SMU

100UA CURRENT SOURCE

R3606
36

DAGND 1

10K

0.1%
1/16W
FF
603

THESE SIGNALS HAVE A MIN_LINE_WIDTH=10MIL


AND MIN_NECK_WIDTH=8MIL

R3603
10K

2 TD_CURRENT
TD11
10MIL 0.1%
8MIL 1/16W
FF
603
36

DAVDD

U3601

5 LMV2011
SOT23-5

36

ADC_REF 1

20K

TD23

0.1%
1/16W
FF
603

BUFFER

R3604

R3608

DAGND

12.7K

36

36

DAVDD

U3602

5 LMV2011
SOT23-5

1%
1/16W
MF
2 603

1
3

R3607
36

DAGND 1

20K

0.1%
1/16W
FF
603

R3605
1
10MIL

8MIL

10K

DAGND
TD_BUFFERED

36

POWER MONITOR

MIN_LINE_WIDTH=10MIL
0.1%
1/16W
FF
603

C3607

MIN_NECK_WIDTH=8MIL

10UF
1

R3609
1

10K

R3611
100K 2

TD3

20%
6.3V
CERM
805

10MIL
0.1%
1/16W
FF
603

R3612
36

TDIODE_POS
1

C3610

0.0022UF

36 31 6

C3606

R3610

1K

1%
1/16W
MF
2 402

TDIODE_NEG

R3615
0

CPU_TEMP_R

DAGND

40.2K2

ADC_REF 1

0.1%
1/16W
FF
603

R3650

100K 2
5%
1/16W
MF
402

36

CPU_TEMP

C3613
10UF

TD4
10MIL

8MIL

0.1%
1/16W
MF
603

ADC_REF

PP3V3_CPU_DIODE
MIN_LINE_WIDTH=25MIL

R3601

8 13 33

200

36

36

10UF

MIN_LINE_WIDTH=10MIL

R3690

PPVREF_SMU_ADC_REF 1

D3600

5%
1/16W
MF
402
NOSTUFF

GND_SMU_AVSS_DAGND 1

2.5V

BM12B-SRSS-TB
F-ST-SM
14
6

1
2
3

4
5

7
8
9
10
11
12

13

2
3

DAGND

36 13

KPGND2

CPU_TEMP

31 33

FMAXT_P
DIFFERENTIAL_PAIR=P_FMAXT

NOSTUFF

NET_SPACING_TYPE=PROC_DIFF

TDIODE_POS 31

36

36

DAGND

51

5%
1/16W
MF
402

TDIODE_NEG 6

R3619
0

5%
1/10W
FF
2 805

R3621

OMIT

NOSTUFF

XW3614
SM

TDIODE_NEG_FMAX
DIFFERENTIAL_PAIR=TDIODE
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

51

5%
1/16W
MF
402

OMIT

36

NEEDED FOR FMAX

NOSTUFF

XW3613
SM

TDIODE_POS_FMAX
DIFFERENTIAL_PAIR=TDIODE
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

CORE_ISNS_P
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

0.47UF

R3620

31 33

XW3612
SM

KPGND2_FMAX
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

CORE_ISNS_M
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

KPVDD2

C3602

20%
10V
2 CERM
603

OMIT

SSOT-23

5%
1/16W
MF
402

XW3611
SM
J3600

2.2UF

20%
2 10V
CERM
805

ADC_REF

R3691

KPVDD2_FMAX
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

C3601

MIN_NECK_WIDTH=8MIL

PLACE CLOSE
TO U2900
OMIT

1%
1/16W
MF
2 603

20%
6.3V
CERM
805

NOSTUFF

MIN_NECK_WIDTH=10MIL

C3608
1

MBR0530
2

NEED TO CONNECT TO P65 OF 80PIN SMU OR PIN 49 OF 64PIN SMU

GND_SMU_AVSS

100K 2

DS3650
SM

5%
1/16W
MF
2 603

MIN_NECK_WIDTH=8MIL

1 NOSTUFF

0
13 36

MIN_LINE_WIDTH=10MIL

20%
2 6.3V
CERM
805

R3614

=PP3V3_PWRON_CPU

R3628

R3613
36

=PP3V3_ALL_CPU

5 LMV2011
SOT23-5

0.1%
1/16W
FF
603

5%
1/16W
MF
2 402

10K

DAVDD

U3603

R3616

10%
2 50V
CERM
402

36

0.1%
1/16W
FF
603

1NOSTUFF

0.0022UF

10%
2 50V
CERM
402

40.2K2

DAGND 1

32 31 29 7 =PPVCORE_CPU
36 31

0.1%
1/16W
MF
603

8MIL

FMAXT_M
DIFFERENTIAL_PAIR=P_FMAXT

NET_SPACING_TYPE=PROC_DIFF

CPU DIODE CONDITIONER

PLACE AT BOARD EDGE

31 36

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

6 33

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
6 33

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

36

103

1
U3TWINS DO NOT HAVE MASKS

=PP2V5_PWRON_RAM

R3702
PP1V5_PWRON_RAM_NB_AVDD

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

38
38
38
38
38
38
38
38
38
38
38

=PP2V5_PWRON_RAM

DDR_DQ64 AG27
DDR_DQ65 AF24
DDR_DQ66 AE24
DDR_DQ67 AG26

OMIT

AB20 DDR_DQ4
AC21 DDR_DQ5
AD23 DDR_DQ6

DDR_DQ68 AF26
DDR_DQ69 AD24
DDR_DQ70 AD25

MEMORY
DATA
INTERFACE

AD21 DDR_DQ7
AH26 DDR_DQ8
AH25 DDR_DQ9

RAM_DQ_R<64>
RAM_DQ_R<65>
RAM_DQ_R<66>
RAM_DQ_R<67>
RAM_DQ_R<68>
RAM_DQ_R<69>
RAM_DQ_R<70>
RAM_DQ_R<71>
RAM_DQ_R<72>
RAM_DQ_R<73>
RAM_DQ_R<74>
RAM_DQ_R<75>
RAM_DQ_R<76>
RAM_DQ_R<77>
RAM_DQ_R<78>
RAM_DQ_R<79>
RAM_DQ_R<80>
RAM_DQ_R<81>
RAM_DQ_R<82>
RAM_DQ_R<83>
RAM_DQ_R<84>
RAM_DQ_R<85>
RAM_DQ_R<86>
RAM_DQ_R<87>
RAM_DQ_R<88>
RAM_DQ_R<89>
RAM_DQ_R<90>
RAM_DQ_R<91>
RAM_DQ_R<92>
RAM_DQ_R<93>
RAM_DQ_R<94>
RAM_DQ_R<95>
RAM_DQ_R<96>
RAM_DQ_R<97>
RAM_DQ_R<98>
RAM_DQ_R<99>
RAM_DQ_R<100>
RAM_DQ_R<101>
RAM_DQ_R<102>
RAM_DQ_R<103>
RAM_DQ_R<104>
RAM_DQ_R<105>
RAM_DQ_R<106>
RAM_DQ_R<107>
RAM_DQ_R<108>
RAM_DQ_R<109>
RAM_DQ_R<110>
RAM_DQ_R<111>
RAM_DQ_R<112>
RAM_DQ_R<113>
RAM_DQ_R<114>
RAM_DQ_R<115>
RAM_DQ_R<116>
RAM_DQ_R<117>
RAM_DQ_R<118>
RAM_DQ_R<119>
RAM_DQ_R<120>
RAM_DQ_R<121>
RAM_DQ_R<122>
RAM_DQ_R<123>
RAM_DQ_R<124>
RAM_DQ_R<125>
RAM_DQ_R<126>
RAM_DQ_R<127>

DDR_DQ71 AG28
DDR_DQ72 AF28
DDR_DQ73 AE28

AH24 DDR_DQ10
AH23 DDR_DQ11
AH27 DDR_DQ12

DDR_DQ74 AD26
DDR_DQ75 AF27
DDR_DQ76 AC26

AG24 DDR_DQ13
AF23 DDR_DQ14
AH28 DDR_DQ15
U25 DDR_DQ16
AA23 DDR_DQ17

DDR_DQ77 AC25
DDR_DQ78 AC27

Y22 DDR_DQ18
AA22 DDR_DQ19
U24 DDR_DQ20

DDR_DQ82 AA24
DDR_DQ83 AA28
DDR_DQ84 Y26

DDR_DQ79 AD27
DDR_DQ80 AA27
DDR_DQ81 AA26

V23 DDR_DQ21
V22 DDR_DQ22
U22 DDR_DQ23

DDR_DQ85 Y25
DDR_DQ86 Y28
DDR_DQ87 Y24

P25 DDR_DQ24
R22 DDR_DQ25
R21 DDR_DQ26
U23 DDR_DQ27
P26 DDR_DQ28

DDR_DQ88 V26
DDR_DQ89 V27

R24 DDR_DQ29
P24 DDR_DQ30
P23 DDR_DQ31

DDR_DQ93 V28
DDR_DQ94 T28
DDR_DQ95 U26

M25 DDR_DQ32
M23 DDR_DQ33
P21 DDR_DQ34

DDR_DQ96 R27
DDR_DQ97 R26
DDR_DQ98 R28

P22 DDR_DQ35
M24 DDR_DQ36
L22 DDR_DQ37
L23 DDR_DQ38
J23 DDR_DQ39

DDR_DQ99 P27
DDR_DQ100 M28
DDR_DQ101 N28
DDR_DQ102 L28
DDR_DQ103 P28

D23 DDR_DQ40
D24 DDR_DQ41
C26 DDR_DQ42

DDR_DQ104 L25
DDR_DQ105 L26
DDR_DQ106 L27

C27 DDR_DQ43
A22 DDR_DQ44
A25 DDR_DQ45

DDR_DQ107 K28
DDR_DQ108 H27
DDR_DQ109 H28

C24 DDR_DQ46
C23 DDR_DQ47
B24 DDR_DQ48
B23 DDR_DQ49
A23 DDR_DQ50

DDR_DQ110 J27
DDR_DQ111 L24

A24 DDR_DQ51
A27 DDR_DQ52
A28 DDR_DQ53

DDR_DQ115 G28
DDR_DQ116 H25
DDR_DQ117 H24

B28 DDR_DQ54
A26 DDR_DQ55
F24 DDR_DQ56

DDR_DQ118 F27
DDR_DQ119 H26
DDR_DQ120 E28

J22 DDR_DQ57
E23 DDR_DQ58
H23 DDR_DQ59
J21 DDR_DQ60
H21 DDR_DQ61

DDR_DQ121 E27
DDR_DQ122 F26

G21 DDR_DQ62
H22 DDR_DQ63

DDR_DQ126 E25
DDR_DQ127 E24

DDR_DQ90 V24
DDR_DQ91 W28
DDR_DQ92 U27

DDR_DQ112 J25
DDR_DQ113 J24
DDR_DQ114 J26

DDR_DQ123 E26
DDR_DQ124 D28
DDR_DQ125 C28

7 26 37 40

38

DDR
CLK_AVDD

38

B25

D22
D27

F19

K27
G25

K19
K23

20%
2 10V
CERM
402

VDD_DDR

U3

38
38

27

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

U3LITE
V1.0-300MM

RAM_CLK66M_NB

AC20 DDR_CLKP

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R

AA12 DDR_CK_A
AB12 DDR_CK_AN
AB14 DDR_CK_B
AA14 DDR_CK_BN

RAM_CKE_R<0>
RAM_CKE_R<1>
RAM_CKE_R<2>
RAM_CKE_R<3>
RAM_CKE_R<4>
RAM_CKE_R<5>
RAM_CKE_R<6>
RAM_CKE_R<7>

AC17 DDR_CKE0
AD17 DDR_CKE1
AE17 DDR_CKE2

PBGA
(SYM 3 OF 7)

38
38
38
38
8
38
8
38
38
38
38
38
8
38
8

=PP2V5_PWRON_RAM

38

1K

1%
1/16W
MF
402 2

38
38
38

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

DDR_MAD10 AF14
DDR_MAD11 AG14
DDR_MAD12 AH17
DDR_MAD13 AG17
DDR_CS0 AF18
DDR_CS1 AE18
DDR_CS2 AG20

AA21 DDR_VREF4
M21 DDR_VREF5
V21 DDR_VREF6
J20 DDR_VREF7

DDR_CS10 AG18
DDR_CS11 AH19

VOLTAGE=1.25V

R37011

38

1K

38

38

0.1UF

1%
1/16W
MF
402 2

38

C3730

C3746

0.1UF

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C3747

C3748
0.1UF

20%
2 10V
CERM
402

RAM_CS_L_R<0>
RAM_CS_L_R<1>
RAM_CS_L_R<2>
RAM_CS_L_R<3>
RAM_CS_L_R<8>
RAM_CS_L_R<9>
RAM_CS_L_R<10>
RAM_CS_L_R<11>

DDR_CS3 AH20
DDR_CS8 AC18
DDR_CS9 AD18

PP1V25_PWRON_RAM_VREF_NB

38

RAM_A_R<0>
RAM_A_R<1>
RAM_A_R<2>
RAM_A_R<3>
RAM_A_R<4>
RAM_A_R<5>
RAM_A_R<6>
RAM_A_R<7>
RAM_A_R<8>
RAM_A_R<9>
RAM_A_R<10>
RAM_A_R<11>
RAM_A_R<12>
RAM_A_R<13>

DDR_MAD7 AC12
DDR_MAD8 AG15
DDR_MAD9 AF15

Y21 DDR_VREF0
U21 DDR_VREF1
L21 DDR_VREF2
H20 DDR_VREF3

R37001

38

RAM_MUXEN0
RAM_MUXEN4

DDR_MAD4 AF12
DDR_MAD5 AE12
DDR_MAD6 AD12

AA18 DDR_CKE7

38

RAM_BA_R<0>
RAM_BA_R<1>

DDR_MAD0 AG12
DDR_MAD1 AH13
DDR_MAD2 AH14
DDR_MAD3 AH15

MEMORY
CONTROL
INTERFACE

AF17 DDR_CKE3
AB17 DDR_CKE4
AA17 DDR_CKE5
AB18 DDR_CKE6

7 26 37 40

38

DDR_MUXEN0 AH16
DDR_MUXEN4 AH18

38

38

38

RAM_WE_L_R

DDR_BA0 AF21
DDR_BA1 AE20

AD14 DDR_CK_DN
AD15 DDR_CK_E
AC15 DDR_CK_EN
AA15 DDR_CK_F
AB15 DDR_CK_FN

38

38

RAM_CAS_L_R

DDR_WE AC23

AE15 DDR_CK_C
AE14 DDR_CK_CN
AC14 DDR_CK_D

38

RAM_RAS_L_R

DDR_CAS AD20

OMIT

38
38

DDR_RAS AE21

DDR_DQSP0 AC24
DDR_DQSP1 AG23

20%
2 10V
CERM
402

RAM_DQS_R<0>
RAM_DQS_R<1>
RAM_DQS_R<2>
RAM_DQS_R<3>
RAM_DQS_R<4>
RAM_DQS_R<5>
RAM_DQS_R<6>
RAM_DQS_R<7>
RAM_DQS_R<8>
RAM_DQS_R<9>
RAM_DQS_R<10>
RAM_DQS_R<11>
RAM_DQS_R<12>
RAM_DQS_R<13>
RAM_DQS_R<14>
RAM_DQS_R<15>

DDR_DQSP2 Y23
DDR_DQSP3 R23
DDR_DQSP4 M22

38
38
38

DDR_DQSP5 B26
DDR_DQSP6 B27
DDR_DQSP7 F23

38
38
38

DDR_DQSP8 AE23
DDR_DQSP9 AD28

38
38

DDR_DQSP10 Y27
DDR_DQSP11 U28
DDR_DQSP12 M27

38
38
38

DDR_DQSP13 J28
DDR_DQSP14 F28
DDR_DQSP15 F25

38
38
38
38

38
38

8
8

38
38
38
38
38
38
38
38
38
38
38
38

38
38

38
38
8
8
38
38
8
8

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

38

DDR_CLK_AVSS
AA20

38

(SYM 2 OF 7)

=PP2V5_PWRON_RAM

C3744
0.1UF

10%
2 6.3V
CERM
402

PBGA

AF20 DDR_DQ0
AH22 DDR_DQ1
AH21 DDR_DQ2
AG21 DDR_DQ3

RAM_DQ_R<0>
RAM_DQ_R<1>
RAM_DQ_R<2>
RAM_DQ_R<3>
RAM_DQ_R<4>
RAM_DQ_R<5>
RAM_DQ_R<6>
RAM_DQ_R<7>
RAM_DQ_R<8>
RAM_DQ_R<9>
RAM_DQ_R<10>
RAM_DQ_R<11>
RAM_DQ_R<12>
RAM_DQ_R<13>
RAM_DQ_R<14>
RAM_DQ_R<15>
RAM_DQ_R<16>
RAM_DQ_R<17>
RAM_DQ_R<18>
RAM_DQ_R<19>
RAM_DQ_R<20>
RAM_DQ_R<21>
RAM_DQ_R<22>
RAM_DQ_R<23>
RAM_DQ_R<24>
RAM_DQ_R<25>
RAM_DQ_R<26>
RAM_DQ_R<27>
RAM_DQ_R<28>
RAM_DQ_R<29>
RAM_DQ_R<30>
RAM_DQ_R<31>
RAM_DQ_R<32>
RAM_DQ_R<33>
RAM_DQ_R<34>
RAM_DQ_R<35>
RAM_DQ_R<36>
RAM_DQ_R<37>
RAM_DQ_R<38>
RAM_DQ_R<39>
RAM_DQ_R<40>
RAM_DQ_R<41>
RAM_DQ_R<42>
RAM_DQ_R<43>
RAM_DQ_R<44>
RAM_DQ_R<45>
RAM_DQ_R<46>
RAM_DQ_R<47>
RAM_DQ_R<48>
RAM_DQ_R<49>
RAM_DQ_R<50>
RAM_DQ_R<51>
RAM_DQ_R<52>
RAM_DQ_R<53>
RAM_DQ_R<54>
RAM_DQ_R<55>
RAM_DQ_R<56>
RAM_DQ_R<57>
RAM_DQ_R<58>
RAM_DQ_R<59>
RAM_DQ_R<60>
RAM_DQ_R<61>
RAM_DQ_R<62>
RAM_DQ_R<63>

38

M19

U3
38

C3745
1UF

U3LITE
V1.0-300MM

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

VOLTAGE=1.5V

N21
N25

VDD_DDR

P20

5%
1/16W
MF
603

T21
T25

2.2

T19

=PP1V5_PWRON_NB_AVDD

W27
V20

W23

Y16
Y19

AA16

AB25
AA13

AC19

AE22
AE27

AE13
AE16

AG25

AG19

60 48 28 7

AB21

40 37 26 7

38
38
38
38
38
38
38
38
38

7 26 37 40

MASTER: GILA
1

C3700
0.1UF

20%
10V
2 CERM
402

C3701
0.1UF

20%
10V
2 CERM
402

C3702
0.1UF

20%
10V
2 CERM
402

C3703
0.1UF

20%
10V
2 CERM
402

C3704
0.1UF

20%
10V
2 CERM
402

C3705
0.1UF

20%
10V
2 CERM
402

C3706
0.1UF

20%
10V
2 CERM
402

C3707
0.1UF

20%
10V
2 CERM
402

C3708
0.1UF

20%
10V
2 CERM
402

C3709
0.1UF

20%
10V
2 CERM
402

C3710
0.1UF

20%
10V
2 CERM
402

C3711
0.1UF

20%
10V
2 CERM
402

C3712
0.1UF

20%
10V
2 CERM
402

C3713
0.1UF

20%
10V
2 CERM
402

C3714
0.1UF

20%
10V
2 CERM
402

C3731
0.1UF

20%
10V
2 CERM
402

C3732
0.1UF

20%
10V
2 CERM
402

C3733
0.1UF

20%
10V
2 CERM
402

C3734
0.1UF

20%
10V
2 CERM
402

C3735
0.1UF

20%
10V
2 CERM
402

C3736
0.1UF

20%
10V
2 CERM
402

C3737

LAST MODIFIED: APR 12, 04

0.1UF

20%
10V
2 CERM
402

U3LITE MEMORY

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1

C3715
0.1UF

20%
2 10V
CERM
402

C3716
0.1UF

20%
2 10V
CERM
402

C3717
0.1UF

20%
2 10V
CERM
402

C3718
0.1UF

20%
2 10V
CERM
402

C3719
0.1UF

20%
2 10V
CERM
402

C3720
0.1UF

20%
2 10V
CERM
402

C3721
0.1UF

20%
2 10V
CERM
402

C3722

0.1UF

C3724
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C3725
0.1UF

20%
2 10V
CERM
402

C3726
0.1UF

C3727
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C3728
0.1UF

20%
2 10V
CERM
402

C3729
0.1UF

20%
2 10V
CERM
402

C3743
0.1UF

20%
2 10V
CERM
402

C3742
0.1UF

20%
2 10V
CERM
402

C3740
0.1UF

20%
2 10V
CERM
402

C3739
0.1UF

20%
2 10V
CERM
402

C3738

II NOT TO REPRODUCE OR COPY IT

0.1UF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

20%
2 10V
CERM
402

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

37

OF

C
103

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37

38 37
38 37
38 37
38 37

RAM_DQ_R<7>
RAM_DQ_R<2>
RAM_DQ_R<0>
RAM_DQ_R<3>
RAM_DQ_R<1>
RAM_DQ_R<4>
RAM_DQ_R<6>
RAM_DQ_R<5>
RAM_DQ_R<9>
RAM_DQ_R<10>
RAM_DQ_R<11>
RAM_DQ_R<14>
RAM_DQ_R<12>
RAM_DQ_R<13>
RAM_DQ_R<15>
RAM_DQ_R<8>
RAM_DQ_R<17>
RAM_DQ_R<22>
RAM_DQ_R<19>
RAM_DQ_R<18>
RAM_DQ_R<20>
RAM_DQ_R<16>
RAM_DQ_R<21>
RAM_DQ_R<23>
RAM_DQ_R<30>
RAM_DQ_R<26>
RAM_DQ_R<24>
RAM_DQ_R<27>
RAM_DQ_R<28>
RAM_DQ_R<31>
RAM_DQ_R<29>
RAM_DQ_R<25>
RAM_DQ_R<32>
RAM_DQ_R<35>
RAM_DQ_R<38>
RAM_DQ_R<37>
RAM_DQ_R<39>
RAM_DQ_R<33>
RAM_DQ_R<34>
RAM_DQ_R<36>
RAM_DQ_R<47>
RAM_DQ_R<46>
RAM_DQ_R<43>
RAM_DQ_R<41>
RAM_DQ_R<45>
RAM_DQ_R<42>
RAM_DQ_R<40>
RAM_DQ_R<44>
RAM_DQ_R<51>
RAM_DQ_R<50>
RAM_DQ_R<49>
RAM_DQ_R<48>
RAM_DQ_R<52>
RAM_DQ_R<53>
RAM_DQ_R<54>
RAM_DQ_R<55>
RAM_DQ_R<56>
RAM_DQ_R<63>
RAM_DQ_R<59>
RAM_DQ_R<61>
RAM_DQ_R<57>
RAM_DQ_R<60>
RAM_DQ_R<58>
RAM_DQ_R<62>

ELECTRICAL_CONSTRAINT_SET

RP3836
RP3836
RP3836
RP3836
RP3816
RP3816
RP3816
RP3816
RP3835
RP3801
RP3801
RP3801
RP3835
RP3801
RP3835
RP3835
RP3822
RP3822
RP3822
RP3822
RP3823
RP3823
RP3823
RP3823
RP3808
RP3824
RP3808
RP3824
RP3808
RP3808
RP3824
RP3824
RP3826
RP3807
RP3826
RP3807
RP3826
RP3807
RP3807
RP3826
RP3811
RP3811
RP3814
RP3814
RP3811
RP3814
RP3814
RP3811
RP3830
RP3830
RP3830
RP3830
RP3812
RP3812
RP3812
RP3812
RP3813
RP3831
RP3813
RP3831
RP3831
RP3831
RP3813
RP3813

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

RAM_DQ<7>
RAM_DQ<2>
RAM_DQ<0>
RAM_DQ<3>
RAM_DQ<1>
RAM_DQ<4>
RAM_DQ<6>
RAM_DQ<5>
RAM_DQ<9>
RAM_DQ<10>
RAM_DQ<11>
RAM_DQ<14>
RAM_DQ<12>
RAM_DQ<13>
RAM_DQ<15>
RAM_DQ<8>
RAM_DQ<17>
RAM_DQ<22>
RAM_DQ<19>
RAM_DQ<18>
RAM_DQ<20>
RAM_DQ<16>
RAM_DQ<21>
RAM_DQ<23>
RAM_DQ<30>
RAM_DQ<26>
RAM_DQ<24>
RAM_DQ<27>
RAM_DQ<28>
RAM_DQ<31>
RAM_DQ<29>
RAM_DQ<25>
RAM_DQ<32>
RAM_DQ<35>
RAM_DQ<38>
RAM_DQ<37>
RAM_DQ<39>
RAM_DQ<33>
RAM_DQ<34>
RAM_DQ<36>
RAM_DQ<47>
RAM_DQ<46>
RAM_DQ<43>
RAM_DQ<41>
RAM_DQ<45>
RAM_DQ<42>
RAM_DQ<40>
RAM_DQ<44>
RAM_DQ<51>
RAM_DQ<50>
RAM_DQ<49>
RAM_DQ<48>
RAM_DQ<52>
RAM_DQ<53>
RAM_DQ<54>
RAM_DQ<55>
RAM_DQ<56>
RAM_DQ<63>
RAM_DQ<59>
RAM_DQ<61>
RAM_DQ<57>
RAM_DQ<60>
RAM_DQ<58>
RAM_DQ<62>

THE FOLLOWING IS A SWAPPABLE GROUP


RP3841 3
6
15
RAM_CKE_R<4>
RAM_CKE<4>
RP3841 4
5
15
RAM_CKE_R<5>
RAM_CKE<5>
RP3841
2
7
15
RAM_CKE_R<0>
RAM_CKE<0>
RP3841 1
8
15
RAM_CKE_R<1>
RAM_CKE<1>

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 37
38 37
38 37

RAM_CS_L_R<8>
RAM_CS_L_R<9>
RAM_CS_L_R<1>
RAM_CS_L_R<0>

RP3842
RP3842
RP3842
RP3842

15
15
15
15

RAM_CS_L<8>
RAM_CS_L<9>
RAM_CS_L<1>
RAM_CS_L<0>

38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37

38 37
38 37

RAM_A_R<12>
RAM_A_R<2>
RAM_A_R<0>
RAM_A_R<5>
RAM_A_R<13>
RAM_A_R<3>

RP3834
RP3800
RP3834
RP3833
RP3832
RP3800
RP3800

RAM_CAS_L_R
RAM_BA_R<0>

RP3804
RP3804

RAM_BA_R<1>
RAM_RAS_L_R
RAM_A_R<9>
RAM_A_R<8>

RP3804
RP3804
RP3834
RP3834

15
15
15
15
15
15
15

RAM_A<12>
RAM_A<2>
RAM_A<0>
RAM_A<5>
RAM_A<13>
RAM_A<3>

15
15

RAM_CAS_L
RAM_BA<0>

38 37

15
15
15
15

RAM_BA<1>
RAM_RAS_L
RAM_A<9>
RAM_A<8>

38 37
38 37
38 37

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

RAM_DQ<68>
RAM_DQ<65>
RAM_DQ<70>
RAM_DQ<66>
RAM_DQ<71>
RAM_DQ<64>
RAM_DQ<67>
RAM_DQ<69>
RAM_DQ<74>
RAM_DQ<73>
RAM_DQ<72>
RAM_DQ<75>
RAM_DQ<78>
RAM_DQ<79>
RAM_DQ<77>
RAM_DQ<76>
RAM_DQ<87>
RAM_DQ<86>
RAM_DQ<81>
RAM_DQ<80>
RAM_DQ<84>
RAM_DQ<85>
RAM_DQ<83>
RAM_DQ<82>
RAM_DQ<91>
RAM_DQ<93>
RAM_DQ<94>
RAM_DQ<90>
RAM_DQ<88>
RAM_DQ<89>
RAM_DQ<92>
RAM_DQ<95>
RAM_DQ<98>
RAM_DQ<96>
RAM_DQ<103>
RAM_DQ<97>
RAM_DQ<100>
RAM_DQ<99>
RAM_DQ<102>
RAM_DQ<101>
RAM_DQ<111>
RAM_DQ<106>
RAM_DQ<105>
RAM_DQ<108>
RAM_DQ<107>
RAM_DQ<110>
RAM_DQ<104>
RAM_DQ<109>
RAM_DQ<119>
RAM_DQ<112>
RAM_DQ<117>
RAM_DQ<118>
RAM_DQ<113>
RAM_DQ<115>
RAM_DQ<116>
RAM_DQ<114>
RAM_DQ<121>
RAM_DQ<124>
RAM_DQ<120>
RAM_DQ<123>
RAM_DQ<125>
RAM_DQ<122>
RAM_DQ<126>
RAM_DQ<127>

38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38

38 40 45
38 37
38 40 45
38 37
38 40 45
44 40 38
38 40 45
44 40 38
38 40 45
45 40 38
38 40 45
45 40 38
38 40 45
38 37
38 40 45
38 37
38 40 45
44 40 38
38 40 45
44 40 38
38 40 45
45 40 38
38 40 45
45 40 38

38 37
38 40 44

38 40 45

38 37

38 40 45

38 37

38 40 44

38 37

38 40 44

38 37

38 37
38 40 44

38 37

38 40 44

38 37

38 40 45

38 37

38 40 45

38 37

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R

R3816
R3817
R3818
R3819
R3820
R3821
R3822
R3823
R3824
R3825
R3826
R3827

15
15
15
15
15
15
15
15
15
15
15
15

RAM_CLK_A_P
RAM_CLK_A_N
RAM_CLK_B_P
RAM_CLK_B_N
RAM_CLK_C_P
RAM_CLK_C_N
RAM_CLK_D_P
RAM_CLK_D_N
RAM_CLK_E_P
RAM_CLK_E_N
RAM_CLK_F_P
RAM_CLK_F_N

38 40 45

38 37

38 40 45

38 37

38 40 45

45 44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

45 40 38

38 40

45 40 38

38 40

45 40 38

38 40

45 40 38

38 40

45 40 38

38 40

38 37

38 40

38 37

38 40

38 37

38 40

38 37

38 40

38 37

38 40

45 44 40 38

38 40

45 40 38
45 40 38

38 40 44

45 40 38
38 37
38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 45

38 37

38 40 45

38 37

38 40 45

38 37

38 40 45

38 37

38 40 44

38 37

38 40 44

38 37

RAM_DQS_R<0>
RAM_DQS_R<1>
RAM_DQS_R<2>
RAM_DQS_R<3>
RAM_DQS_R<4>
RAM_DQS_R<5>
RAM_DQS_R<6>
RAM_DQS_R<7>
RAM_DQS_R<8>
RAM_DQS_R<9>
RAM_DQS_R<10>
RAM_DQS_R<11>
RAM_DQS_R<12>
RAM_DQS_R<13>
RAM_DQS_R<14>
RAM_DQS_R<15>

R3800
R3801
R3802
R3803
R3804
R3805
R3806
R3807
R3808
R3809
R3810
R3811
R3812
R3813
R3814
R3815

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

RAM_DQS<0>
RAM_DQS<1>
RAM_DQS<2>
RAM_DQS<3>
RAM_DQS<4>
RAM_DQS<5>
RAM_DQS<6>
RAM_DQS<7>
RAM_DQS<8>
RAM_DQS<9>
RAM_DQS<10>
RAM_DQS<11>
RAM_DQS<12>
RAM_DQS<13>
RAM_DQS<14>
RAM_DQS<15>

RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK

DIFFERENTIAL_PAIR
RAM_CLK_A_R
RAM_CLK_A_R
RAM_CLK_B_R
RAM_CLK_B_R
RAM_CLK_C_R
RAM_CLK_C_R
RAM_CLK_D_R
RAM_CLK_D_R
RAM_CLK_E_R
RAM_CLK_E_R
RAM_CLK_F_R
RAM_CLK_F_R
RAM_CLK_A
RAM_CLK_A
RAM_CLK_B
RAM_CLK_B
RAM_CLK_C
RAM_CLK_C
RAM_CLK_D
RAM_CLK_D
RAM_CLK_E
RAM_CLK_E
RAM_CLK_F
RAM_CLK_F

RAM_CKE_R<1..0>
RAM_CKE_R<5..4>
RAM_CKE<0>
RAM_CKE<1>
RAM_CKE<4>
RAM_CKE<5>
RAM_CS_L_R<1..0>
RAM_CS_L_R<9..8>
RAM_CS_L<0>
RAM_CS_L<1>
RAM_CS_L<8>
RAM_CS_L<9>

RAM_CKECS0
RAM_CKECS0
RAM_CKECS1
RAM_CKECS1

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_DQS0
RAM_DQS0
RAM_DQS1
RAM_DQS1
RAM_DQS2
RAM_DQS2
RAM_DQS3
RAM_DQS3
RAM_DQS4
RAM_DQS4
RAM_DQS5
RAM_DQS5
RAM_DQS6
RAM_DQS6
RAM_DQS7
RAM_DQS7
RAM_DQS8
RAM_DQS8
RAM_DQS9
RAM_DQS9
RAM_DQS10
RAM_DQS10
RAM_DQS11
RAM_DQS11
RAM_DQS12
RAM_DQS12
RAM_DQS13
RAM_DQS13
RAM_DQS14
RAM_DQS14
RAM_DQS15
RAM_DQS15

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_A_CTL
RAM_A_CTL
RAM_A_CTL
RAM_A_CTL
RAM_A_CTL

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_CKECS0
RAM_CKECS0
RAM_CKECS1
RAM_CKECS1

I209
I210
I211
I212
I213
I214
I215

I216
I217
I218
I219
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229

I234
I236
I235
I237
I238
I241
I243
I242
I245

RAM_DQS_R<15..0>
RAM_DQ_R<127..0>
RAM_DQ<127..0>
RAM_DQS<0>
RAM_DQ<7..0>
RAM_DQS<1>
RAM_DQ<15..8>
RAM_DQS<2>
RAM_DQ<23..16>
RAM_DQS<3>
RAM_DQ<31..24>
RAM_DQS<4>
RAM_DQ<39..32>
RAM_DQS<5>
RAM_DQ<47..40>
RAM_DQS<6>
RAM_DQ<55..48>
RAM_DQS<7>
RAM_DQ<63..56>
RAM_DQS<8>
RAM_DQ<71..64>
RAM_DQS<9>
RAM_DQ<79..72>
RAM_DQS<10>
RAM_DQ<87..80>
RAM_DQS<11>
RAM_DQ<95..88>
RAM_DQS<12>
RAM_DQ<103..96>
RAM_DQS<13>
RAM_DQ<111..104>
RAM_DQS<14>
RAM_DQ<119..112>
RAM_DQS<15>
RAM_DQ<127..120>

I244

I305
I294
I293
I246
I248
I251
I252
I253
I254
I255
I256
I257
I258
I259
I260
I261
I262
I263
I264
I265
I267
I266
I268
I270
I269

I272
I271
I273
I275
I274
I277
I276
I278
I280

38 40 44

45 40 38

RAM_A_R<13..0>
RAM_BA_R<1..0>
RAM_RAS_L_R
RAM_CAS_L_R
RAM_WE_L_R
RAM_A<13..0>
RAM_BA<1..0>
RAM_RAS_L
RAM_CAS_L
RAM_WE_L

I279

I295
I296
I297
I298
I299
I300
I304
I303
I302
I301

38 40 44
38 40 44
38 40 44

SERIES TERM

RAM_CLK PRIMARY SPACING SET BASED ON DIFF IMPEDANCE


RAM_CLK LINE-LINE SPACING SET TO 15MIL
TOTAL LENGTH TOLERENCE = 20PS = 2.82MM

38 40 44
38 40 44
38 40 44
38 40 44

NOTICE OF PROPRIETARY PROPERTY

RAM_CAD SPACING IS 10MIL

38 40 45

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

38 40 45
38 40 45

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

38 40 45

II NOT TO REPRODUCE OR COPY IT

38 40 45

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

38 40 45
38 40 45

SIZE
38 40 45

DRAWING NUMBER

REV.

051-6482

SHT
NONE

I208

I232

SCALE

I207

I230

APPLE COMPUTER INC.

I206

38 40

38 40 44

38 40 44

RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1

NET_SPACING_TYPE

38 40 45

45 40 38
38 40 44

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R
RAM_CLK_A_P
RAM_CLK_A_N
RAM_CLK_B_P
RAM_CLK_B_N
RAM_CLK_C_P
RAM_CLK_C_N
RAM_CLK_D_P
RAM_CLK_D_N
RAM_CLK_E_P
RAM_CLK_E_N
RAM_CLK_F_P
RAM_CLK_F_N

NET_PHYSICAL_TYPE

38 40 45

THE FOLLOWING ARE 0402 5% RESISTORS

38 37
38 37

38 40 45

38 37
38 37

45 40 38
38 40 45

38 37

THE FOLLOWING IS A SWAPPABLE GROUP


RP3832 3
6
15
RAM_A_R<11>
RAM_A<11>
RP3832 4
5
15
RAM_A_R<1>
RAM_A<1>
RP3832
2
7
15
RAM_A_R<10>
RAM_A<10>
RP3800 4
5
15
RAM_WE_L
RAM_WE_L_R
RP3833 3
6
15
RAM_A_R<4>
RAM_A<4>
RP3833
2
7
15
RAM_A_R<6>
RAM_A<6>
RP3833
1
8
15
RAM_A_R<7>
RAM_A<7>

RP3818
RP3805
RP3818
RP3805
RP3818
RP3805
RP3805
RP3818
RP3817
RP3802
RP3817
RP3817
RP3802
RP3817
RP3802
RP3802
RP3806
RP3821
RP3821
RP3821
RP3806
RP3806
RP3821
RP3806
RP3819
RP3819
RP3803
RP3819
RP3803
RP3819
RP3803
RP3803
RP3820
RP3820
RP3820
RP3820
RP3825
RP3825
RP3825
RP3825
RP3809
RP3809
RP3809
RP3829
RP3829
RP3829
RP3809
RP3829
RP3828
RP3815
RP3815
RP3828
RP3815
RP3828
RP3828
RP3815
RP3827
RP3827
RP3827
RP3810
RP3827
RP3810
RP3810
RP3810

45 40 38

38 37
38 37

RAM_DQ_R<68>
RAM_DQ_R<65>
RAM_DQ_R<70>
RAM_DQ_R<66>
RAM_DQ_R<71>
RAM_DQ_R<64>
RAM_DQ_R<67>
RAM_DQ_R<69>
RAM_DQ_R<74>
RAM_DQ_R<73>
RAM_DQ_R<72>
RAM_DQ_R<75>
RAM_DQ_R<78>
RAM_DQ_R<79>
RAM_DQ_R<77>
RAM_DQ_R<76>
RAM_DQ_R<87>
RAM_DQ_R<86>
RAM_DQ_R<81>
RAM_DQ_R<80>
RAM_DQ_R<84>
RAM_DQ_R<85>
RAM_DQ_R<83>
RAM_DQ_R<82>
RAM_DQ_R<91>
RAM_DQ_R<93>
RAM_DQ_R<94>
RAM_DQ_R<90>
RAM_DQ_R<88>
RAM_DQ_R<89>
RAM_DQ_R<92>
RAM_DQ_R<95>
RAM_DQ_R<98>
RAM_DQ_R<96>
RAM_DQ_R<103>
RAM_DQ_R<97>
RAM_DQ_R<100>
RAM_DQ_R<99>
RAM_DQ_R<102>
RAM_DQ_R<101>
RAM_DQ_R<111>
RAM_DQ_R<106>
RAM_DQ_R<105>
RAM_DQ_R<108>
RAM_DQ_R<107>
RAM_DQ_R<110>
RAM_DQ_R<104>
RAM_DQ_R<109>
RAM_DQ_R<119>
RAM_DQ_R<112>
RAM_DQ_R<117>
RAM_DQ_R<118>
RAM_DQ_R<113>
RAM_DQ_R<115>
RAM_DQ_R<116>
RAM_DQ_R<114>
RAM_DQ_R<121>
RAM_DQ_R<124>
RAM_DQ_R<120>
RAM_DQ_R<123>
RAM_DQ_R<125>
RAM_DQ_R<122>
RAM_DQ_R<126>
RAM_DQ_R<127>

ALL R PACKS ARE 1/16W 5%

38

OF

C
103

8
40 37 26 7

=PP2V5_PWRON_RAM

=PP2V5_PWRON_RAM

J4000
DDR-DIMM-STD
F-28DEG-TH

40
44 38

44 38

RAM_DQ<10>
RAM_DQS<1>
RAM_DQ<9>

44 38

RAM_DQ<15>

44 38
44 38

PP1V25_RAM_VREF_DIMM
RAM_DQ<14>

2
3
4
5
6
7
8

NC
6

44 38
44 38
44 38

38
38

44 38
44 38
44 38

44 38
44 38
44 38

44 40 38
44 38
44 40 38

TP_J4000_SJRESET_L
RAM_DQ<2>
RAM_DQ<0>
RAM_DQS<0>
RAM_CLK_A_P
RAM_CLK_A_N
RAM_DQ<6>
RAM_DQ<5>
RAM_CKE<0>
RAM_DQ<19>
RAM_DQ<18>
RAM_DQS<2>
RAM_A<9>
RAM_DQ<23>
RAM_A<7>

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

44 38
44 40 38
44 38

44 38
44 38
44 40 38

RAM_DQ<16>
RAM_A<5>
RAM_DQ<27>
RAM_DQ<29>
RAM_DQS<3>
RAM_A<4>

31
32
33
34
35
36
37
38

44 38
44 38
44 40 38

44 40 38

RAM_DQ<31>
RAM_DQ<28>
RAM_A<2>
RAM_A<1>

39
40
41
42
43

NC 44
NC 45
46

NC 47
44 40 38

45 40 38

44 38

44 38
44 38
44 38

RAM_A<0>

RAM_BA<1>
RAM_DQ<34>
RAM_DQ<37>
RAM_DQS<4>
RAM_DQ<38>

44 38

44 38

45 40 38
44 38
45 40 38

RAM_BA<0>
RAM_DQ<32>
RAM_DQ<61>
RAM_WE_L
RAM_DQ<57>
RAM_CAS_L

44 38
44 38

44 38
44 38

38
38

RAM_DQS<7>
RAM_DQ<59>
RAM_DQ<56>

RAM_DQ<43>
RAM_DQ<41>
RAM_CLK_B_N
RAM_CLK_B_P

44 38
44 38

RAM_DQS<5>
RAM_DQ<47>
RAM_DQ<44>

44 38
44 38
44 38

40 18
40 18

VSS
NC

DQ3
NC

NC

NC
VSS
DQ8

A13
VDDQ

DQ9

DQ12

DQS1
VDDQ

DQ13
DM1/DQS10

CK1

VDD

CK1*
VSS

DQ14
DQ15

DQ10
DQ11

CKE1
VDDQ

CKE0

BA2

VDDQ
DQ16

DQ20
A12

DQ17

VSS

DQS2
VSS

DQ21
A11

A9

DM2/DQS11

DQ18
A7

VDD
DQ22

VDDQ
DQ19

A8
DQ23

A5

VSS

DQ24
VSS

A6
DQ28

DQ25

DQ29

DQS3
A4

VDDQ
DM3/DQS12

VDD

A3

DQ26
DQ27

DQ30
VSS

A2
VSS

DQ31
NC

A1

NC

NC
NC

VDDQ
CK0

VDD

CKO*

A10

50
NC 51
52
53
54
55
56
57
59
60
61
62
63
64
65
67
68
69
70
NC 71
72
73
74
75
76
78
79
80

RAM_DQ<50>
RAM_DQ<51>

83

RAM_DQS<6>
RAM_DQ<53>
RAM_DQ<52>

86
87

I2C_DIMM_SDA
I2C_DIMM_SCL

DQ6
DQ7

DQ2
VDD

VSS
NC

81

44 38

DM0/DQS9

NC

NC 82
44 38

DQ5
VDDQ

NC
A0

77
44 38

VSS
DQ4

VSS
DQ1
DQS0

84
85

88
89
NC 90
91
92

VSS
NC

NC
VDDQ

BA1

NC

DQ32
VDDQ

VSS
DQ36

DQ33

DQ37

DQS4
DQ34

VDD
DM4/DQS13

VSS

DQ38

BA0
DQ35

DQ39
VSS

DQ40
VDDQ

DQ44
RAS*

WE*

DQ45

DQ41
CAS*

VDDQ
S0*

VSS

S1*

DQS5
DQ42

DM5/DQS14
VSS

DQ43

DQ46

VDD
NC,S2*

DQ47
NC,S3*

DQ48
DQ49

VDDQ
DQ52

VSS

DQ53

CK2*
CK2

NC,FETEN
VDD

VDDQ

DM6/DQS15

DQS6
DQ50

DQ54
DQ55

DQ51

VDDQ

VSS
VDDID

NC
DQ60

DQ56
DQ57

DQ61
VSS

VDD

DM7/DQS16

DQS7
DQ58

DQ62
DQ63

DQ59

VDDQ

VSS
WP

SA0
SA1

SDA

SA2

SCL

516-0086

TOP SIDE

OMIT

DQ0

48

66
44 38

VREF

NC 49

58
45 40 38

BOT SIDE

VVDDSPD

7 26 37 40

40 37 26 7

=PP2V5_PWRON_RAM

95
96

45 38

PP1V25_RAM_VREF_DIMM
RAM_DQ<75>

2
3

38 44
38 44

97

45 38

98
99

45 38

RAM_DQ<79>
RAM_DQS<9>
RAM_DQ<73>

45 38

RAM_DQ<77>

45 38

RAM_DQ<8>
RAM_DQ<12>

4
5
6

38 44

38 44

100

8
9

NC

101 NC
102 NC

103 NC FETEN
104
105

45 38

RAM_DQ<3>
RAM_DQ<7>

106
107

45 38
38 44
45 38

111
112
113 NC
114
115

38

45 38
38 44

38 44

38 40 44

116

RAM_DQ<22>
RAM_A<11>

45 38
7 26 37 40

C4036 1 C4006

45 38

10UF

45 38

10UF

20%
6.3V
2 CERM
1206

38 44

20%
6.3V
2 CERM
1206

45 38

44 40 38

C4039
0.1UF

RAM_DQ<21>
RAM_A<8>
RAM_DQ<20>

122
123
124

38 44
38 40 44

C4037
0.1UF

C4023

45 38

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

44 40 38

45 38

38 44
44 40 38

125
126

RAM_A<6>
RAM_DQ<26>
RAM_DQ<25>

127

C4040
0.1UF

38 40 44

20%
2 10V
CERM
402

38 44
38 44

128
129

C4038
0.1UF

20%
2 10V
CERM
402

C4024

45 38

RAM_A<3>
RAM_DQ<24>

131
132
133

RAM_DQ<30>

C4044
0.1UF

38 40 44

20%
2 10V
CERM
402

38 44

136
137

10V
2 CERM

C4045
0.1UF
20%

138

C4041
0.1UF

20%
2 10V
CERM
402

21
22
23

RAM_DQ<83>
RAM_DQ<80>
RAM_DQS<10>

24
25
27
28

RAM_A<9>
RAM_DQ<82>
RAM_A<7>

29
30
31

RAM_DQ<87>
RAM_A<5>
RAM_DQ<90>

32
33
34

20%
2 10V
CERM
402

45 38
45 38

35
36

RAM_DQ<89>
RAM_DQS<11>
RAM_A<4>

37

C4025
0.1UF

44 40 38

RAM_DQ<88>
RAM_DQ<94>
RAM_A<2>

44 40 38

RAM_A<1>

45 38

20%
2 10V
CERM
402

45 38

38
39
40
41
42

38 44

134 NC
135 NC

RAM_CLK_C_P
RAM_CLK_C_N

19
20

RAM_DQ<71>
RAM_DQ<70>
RAM_CKE<4>

0.1UF

44 40 38

130

16
17

RAM_CLK_F_P
RAM_CLK_F_N

26

38 40 44

119
120
121

13
14

18

45 38

117
118

12

38 44
38 44

=PP2V5_PWRON_RAM
RAM_DQ<17>
RAM_A<12>

RAM_DQ<66>
RAM_DQ<67>
RAM_DQS<8>

15

108

RAM_DQ<1>
RAM_DQ<4>
RAM_CKE<1>

TP_J4001_SJRESET_L

10
11

38 44

38

109
110

402

38

C4043
0.1UF

20%
10V
2 CERM
402

C4026

43
44

0.1UF

NC
NC 45

20%
10V
2 CERM
402

46
47

38

NC

139
140 NC
141

C4048
0.1UF

RAM_A<10>

20%
2 10V
CERM
402

38 40 45

142 NC
143

C4046
0.1UF

20%
2 10V
CERM
402

C4029

44 40 38

C4031

0.1UF

145
146

RAM_DQ<35>
RAM_DQ<33>

147

38 44

C4047

NC 49

20%
2 10V
CERM
402

20%
10V
402

2 CERM

C4050

38 44

0.1UF

2 CERM

50

NC 51

C4030
0.1UF

45 38

20%
10V
402

20%
10V
402

2 CERM

C4049

150

RAM_DQ<36>
RAM_DQ<39>

151
152
153

RAM_DQ<60>
RAM_RAS_L
RAM_DQ<63>

154
155
156
157

RAM_CS_L<0>
RAM_CS_L<1>

158

0.1UF

38 44

20%
2 10V
CERM
402

38 44

0.1UF

20%
10V
2 CERM
402

45 38

45 38

C4032

20%
10V
2 CERM
402

45 40 38
45 38
45 38

C4028
0.1UF

38 44

20%
2 10V
CERM
402

38 44

C4022
0.1UF

45 40 38

20%
2 10V
CERM
402

45 38
45 40 38

38 44
45 38
45 38

RAM_DQ<62>
RAM_DQ<58>

162
163 NC
164

RAM_DQ<40>
RAM_DQ<42>
RAM_A<13>

167
168

55
56

RAM_DQ<103>
RAM_DQS<12>
RAM_DQ<101>

57
58
59

RAM_BA<0>
RAM_DQ<102>
RAM_DQ<106>

60
61
62

45 38

63

RAM_WE_L
RAM_DQ<111>
RAM_CAS_L

64
65
66
67

RAM_DQS<13>
RAM_DQ<107>
RAM_DQ<110>

68
69
70

38 44
38 44

71

NC
45 38

165
166

53
54

RAM_DQ<98>

0.1UF

159
160
161

52

RAM_BA<1>

38 44
38 40 45

45 38

72
73

RAM_DQ<114>
RAM_DQ<113>

38 44

74

38 44
38
38 40 44
38

75
76

RAM_CLK_E_N
RAM_CLK_E_P

77
78

169
170
171

RAM_DQ<46>
RAM_DQ<45>

45 38
38 44
45 38
38 44
45 38

172
173 NC
174

RAM_DQ<49>
RAM_DQ<48>

175

45 38
38 44
45 38

183
184

79
80
81
83
84

RAM_DQ<124>
RAM_DQ<125>

85

RAM_DQ<54>
RAM_DQ<55>

45 38
38 44
45 38
38 44
45 38

180
181
182

RAM_DQS<14>
RAM_DQ<115>
RAM_DQ<118>

NC 82
38 44

176
177
178
179

88
89

NC 90
40 18

R4014

40 18

10K 2
1

5%
1/16W
MF
ADDR=0(A0/A1) 402

86
87

RAM_DQS<15>
RAM_DQ<127>
RAM_DQ<126>

SD_A_SA0
SA1
SA2

91
92

I2C_DIMM_SDA
I2C_DIMM_SCL

BOT SIDE

VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC

TOP SIDE

OMIT

VSS
DQ4
DQ5
VDDQ

DM0/DQS9
DQ6
DQ7
VSS
NC

NC
VSS

NC
A13

DQ8

VDDQ

DQ9
DQS1

DQ12
DQ13

VDDQ

DM1/DQS10

CK1
CK1*

VDD
DQ14

VSS
DQ10

DQ15
CKE1

DQ11

VDDQ

CKE0
VDDQ

BA2
DQ20

DQ16

A12

DQ17
DQS2

VSS
DQ21

VSS

A11

A9
DQ18

DM2/DQS11
VDD

A7
VDDQ

DQ22
A8

DQ19

DQ23

A5
DQ24

VSS
A6

VSS
DQ25
DQS3
A4

DQ28
DQ29
VDDQ
DM3/DQS12

VDD
DQ26

A3
DQ30

DQ27
A2

VSS
DQ31

VSS

NC

A1
NC

NC
VDDQ

NC

CK0

VDD
NC
A0
NC
VSS
NC
BA1

CKO*
VSS
NC
A10
NC
VDDQ
NC

R4008

93
94
95

RAM_DQ<74>
RAM_DQ<72>

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

CONN,DDR DIMM 30 DEG

J4000,J4001

CRITICAL

17_INCH_LCD

V
V
R
R
V

TABLE_5_ITEM

516-0087

CONN,DDR DIMM REVERSE 30 DEG

J4000,J4001

150
1%
1/16W
MF
2 402

38 45
38 45

96
97
98

RAM_DQ<76>
RAM_DQ<78>

99

PP1V25_RAM_VREF_DIMM
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
38 45

105
106

C4035 R4010

10%
6.3V
2 CERM
603

RAM_DQ<65>
RAM_DQ<64>

DQ32

VSS

VDDQ

DQ36

DQ33
DQS4

DQ37
VDD

DQ34

DM4/DQS13

VSS
BA0

DQ38
DQ39

DQ35

VSS

DQ40
VDDQ

DQ44
RAS*

WE*
DQ41

DQ45
VDDQ

CAS*

S0*

VSS
DQS5

S1*
DM5/DQS14

DQ42

VSS

DQ43
VDD

DQ46
DQ47

NC,S2*

NC,S3*

DQ48
DQ49

VDDQ
DQ52

VSS
CK2*

DQ53
NC,FETEN

CK2

VDD

VDDQ
DQS6

DM6/DQS15
DQ54

DQ50

DQ55

DQ51
VSS

VDDQ
NC

VDDID

DQ60

DQ56
DQ57

DQ61
VSS

VDD
DQS7

DM7/DQS16
DQ62

DQ58

DQ63

DQ59
VSS
WP
SDA
SCL

VDDQ
SA0
SA1
SA2
VVDDSPD

20_INCH_LCD

CRITICAL

150
1%
1/16W
MF
2 402

38 45
38 45

107
108
109

RAM_DQ<69>
RAM_DQ<68>
RAM_CKE<5>

110
111
112

38 45
38 45
38 45

=PP2V5_PWRON_RAM

113 NC
114

RAM_DQ<81>
RAM_A<12>

115

38 40 44

C4008 1 C4007
10UF

116
117

RAM_DQ<86>
RAM_A<11>

118

38 40 44

RAM_DQ<85>
RAM_A<8>
RAM_DQ<84>

122
123
124
125

RAM_A<6>
RAM_DQ<91>
RAM_DQ<93>

126
127
128

10UF

20%
6.3V
2 CERM
1206

38 45

119
120
121

7 26 37 40

38 45

C4011
0.1UF

38 45

20%
10V
2 CERM
402

38 40 44
38 45

38 40 44

C4014
0.1UF

38 45

20%
10V
2 CERM
402

38 45

20%
6.3V
2 CERM
1206

C4010

0.1UF

20%
10V
2 CERM
402
1

C4012

20%
10V
2 CERM
402

C4009
0.1UF
20%
10V
402

2 CERM

0.1UF

C4033
0.1UF
20%
10V
402

2 CERM

129
130
131

RAM_A<3>
RAM_DQ<92>

38 40 44

C4000
0.1UF

38 45

20%

2 10V
CERM

132
133
134 NC
135 NC
136

RAM_DQ<95>

137

RAM_CLK_D_P
RAM_CLK_D_N

402

38 45

C4020
20%

138
139
140 NC
141
142 NC

402

38

RAM_A<10>

C4017
0.1UF

38 40 45

20%
2 10V
CERM
402

143

0.1UF
20%

2 10V
CERM

402

0.1UF
2 10V
CERM

38

C4013

C4015
20%
402

C4016

0.1UF
20%
402

C4001
0.1UF
20%

10V
2 CERM
402

0.1UF

20%
2 10V
CERM
402

C4042

2 10V
CERM

0.1UF
10V
2 CERM

C4027
0.1UF
20%

2 10V
CERM

402

144 NC
145
146

C4019

0.1UF
RAM_DQ<96>
RAM_DQ<97>

147
148

38 45
38 45

149
1

150
151

RAM_DQ<99>
RAM_DQ<100>

152
153
154

RAM_DQ<104>
RAM_RAS_L
RAM_DQ<105>

155
156
157

RAM_CS_L<8>
RAM_CS_L<9>

158
159

C4021

20%
10V
2 CERM
402

38 45

0.1UF
2 CERM

0.1UF

38 45

C4051

20%
10V
402

2 CERM

C4004
0.1UF

20%
10V
402

2 CERM

C4018

20%
10V
402

0.1UF

20%
10V
2 CERM
402

C4005
0.1UF
20%
10V
402

2 CERM

38 45
38 40 45

C4052
0.1UF

38 45

20%
10V
2 CERM
402

38 45

C4002
0.1UF

20%
10V
2 CERM
402

C4003
0.1UF

20%
10V
2 CERM
402

38 45

160
161
162

RAM_DQ<108>
RAM_DQ<109>

163 NC
164
165

RAM_DQ<112>
RAM_DQ<117>
RAM_A<13>

166
167
168
169
170

RAM_DQ<119>
RAM_DQ<116>

171
172
173 NC
174

RAM_DQ<120>
RAM_DQ<121>

175
176

38 45
38 45

38 45
38 45
38 40 44

38 45
38 45

38 45
38 45

DIMMS

177
178
179
180
181
182
183
184

RAM_DQ<122>
RAM_DQ<123>
SA0
SA1
SA2

38 45

RS ADJACENT TO VS OR GS
VS ADJACENT TO GS FORBIDDEN

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SD_B_SA2

R4006

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

10K 2

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

REV.

051-6482

D
SCALE

38 45

SHT
NONE

40

1UF

38 45

100
101 NC
102 NC
103 NC FETEN
104

5%
1/16W
MF
402
ADDR=1(A2/A3)

TABLE_5_HEAD

PART#

7 26 37 40

516-0086

=PP2V5_PWRON_RAM

45 38

148
149

48

RAM_A<0>

0.1UF

45 40 38

144 NC

7 26 37 40

F-28DEG-TH
40

RAM_DQ<11>
RAM_DQ<13>

=PP2V5_PWRON_RAM

J4001

DDR-DIMM-STD

93
94

5
PIN 82:
NC: VDD & VDDQ ARE THE SAME
GND: VDD & VDDQ ARE DIFFERENT

40

OF

C
103

46 45 44 7

RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5 RAM_VTT

RP4400
82

RP4400
82

RP4401
82

RP4401
82

RP4401
82

RP4401
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38

46 45 44 7

0.1UF

46 45 44 7

PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4400

RP4400
82

1
40 38

RAM_VTT

RP4400
82

C4412
0.1UF

20%
10V
2 CERM
402

RAM_DQ<7>
RAM_DQ<0>
RAM_DQ<3>
RAM_DQ<2>
RAM_DQ<5>
RAM_DQ<4>
RAM_DQ<1>
RAM_DQ<6>

40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

C4407

RP4416
82

RP4416
82

RP4416
82

RP4416
82

RP4417
82

RP4417
82

RP4417
82

RP4417
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

40 38

0.1UF

RAM_VTT

RAM_VTT

0.1UF

20%
10V
2 CERM
402

40 38

40 38
40 38
40 38
40 38

RAM_VTT

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

46 45 44 7

RP4404
82

RP4404
82

RP4404
82

RP4405
82

RP4405
82

RP4405
82

RP4405
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4401

RP4404
82
1

40 38

120

120

120

120

120

120

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

0.1UF

C4413
0.1UF

20%
2 10V
CERM
402

RAM_DQ<10>
RAM_DQ<13>
RAM_DQ<11>
RAM_DQ<14>
RAM_DQ<15>
RAM_DQ<12>
RAM_DQ<8>
RAM_DQ<9>

40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

C4406

RP4420
82

RP4420
82

RP4420
82

RP4420
82

RP4421
82

RP4421
82

RP4421
82

RP4421
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

40 38

PP1V25_RAM_VTT

46 45 44 7

RAM_VTT

40 38
40 38

RAM_VTT

6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5


RAM_VTT

RAM_VTT

0.1UF

RP4437

C4415

150
5%
1/16W

0.1UF

20%
2 10V
CERM
402

SM1

1
40 38

RAM_DQ<43>
RAM_DQ<42>
RAM_DQ<40>
RAM_DQ<41>
RAM_DQ<44>
RAM_DQ<45>
RAM_DQ<47>
RAM_DQ<46>

40 38
40 38
40 38
40 38
40 38
40 38
40 38

PP1V25_RAM_VTT

RP4408
82

RP4408
82

RP4408
82

RP4409
82

RP4409
82

RP4409
82

RP4409
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4402

RP4408
82
1

40 38

0.1UF

C4416
0.1UF

20%
2 10V
CERM
402

RAM_DQ<22>
RAM_DQ<18>
RAM_DQ<19>
RAM_DQ<17>
RAM_DQ<20>
RAM_DQ<16>
RAM_DQ<21>
RAM_DQ<23>

40 38
40 38
40 38
40 38
40 38
40 38
40 38

C4405

RP4424
82

RP4424
82

RP4424
82

RP4424
82

RP4425
82

RP4425
82

RP4425
82

RP4425
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

40 38

RAM_VTT

0.1UF

46 45 44 7

150
5%
1/16W

20%
2 10V
CERM
402

SM1

40 38
40 38
40 38
40 38
40 38

8RAM_VTT 7RAM_VTT 6RAM_VTT

40 38

40 38

40 38
40 38
40 38

5RAM_VTT 8
RAM_VTT

RAM_VTT

5 RAM_VTT

RP4412
82

RP4412
82

RP4412
82

RP4412
82

RP4413
82

RP4413
82

RP4413
82

RP4413
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

7RAM_VTT 6

RAM_VTT

PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4403
0.1UF

C4417
0.1UF

20%
10V
2 CERM
402

RAM_DQ<30>
RAM_DQ<28>
RAM_DQ<31>
RAM_DQ<24>
RAM_DQ<29>
RAM_DQ<25>
RAM_DQ<26>
RAM_DQ<27>

46 45 44 7

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

C4404

RP4428
82

RP4428
82

RP4428
82

RP4428
82

RP4429
82

RP4429
82

RP4429
82

RP4429
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

RAM_DQ<58>
RAM_DQ<62>
RAM_DQ<56>
RAM_DQ<59>
RAM_DQ<57>
RAM_DQ<63>
RAM_DQ<60>
RAM_DQ<61>

0.1UF

20%
10V
2 CERM
402

40 38
40 38

C4409

RP4436
150

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

0.1UF

C4421
0.1UF

20%
2 10V
CERM
402

RP4438
150

RP4438
150

RP4438
150

RP4439
150

RP4439
150

RP4439
150

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

1/16W
MF
2 402

5%
1/16W
MF
2 402

RP4439
150
5%
1/16W
SM1

RP4441
150

RP4441
150

5%
1/16W
SM1

5%
1/16W
SM1

RP4441 R4416
150
150
5%
5%
1/16W
SM1

R4417
150

C4410
0.1UF

20%
10V
2 CERM
402

C4422
0.1UF

20%
10V
2 CERM
402

B
7

RP4442
150

RP4442
150

RP4442
150

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
MF
2 402

2 402

R4420
150

R4421
150
5%
1/16W
MF

=PP2V5_RUN_RAM
1

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R4408
120

0.1UF

40 38

RP4436
150

PP1V25_RAM_VTT

C4418

40 38

RP4436
150

RP4441_NC
RAM_A<8>
RAM_A<9>
RAM_A<11>
RAM_A<12>
RAM_A<13>

RAM_VTT
1

RP4436
150

RP4441

0.1UF

PP1V25_RAM_VTT

RP4437
150

C4419

RAM_DQ<51>
RAM_DQ<48>
RAM_DQ<50>
RAM_DQ<49>
RAM_DQ<52>
RAM_DQ<55>
RAM_DQ<53>
RAM_DQ<54>

RP4437
150

SM1

40 38

0.1UF

20%
2 10V
CERM
402

150
5%
1/16W

40 38

C4420

=PP2V5_RUN_RAM

RAM_VTT
1

RP4437
150
2

RP4442

40 38

20%
2 10V
CERM
402

RAM_A<0>
RAM_A<1>
RAM_A<2>
RAM_A<3>
RAM_A<4>
RAM_A<6>
RAM_A<5>
RAM_A<7>

46 45 44 7

RAM_VTT
1

0.1UF

=PP2V5_RUN_RAM

RAM_VTT
1

46 45 44 7

40 38

C4408

SM1

40 38

RAM_VTT
1

RAM_DQS<0>
RAM_DQS<1>
RAM_DQS<2>
RAM_DQS<3>
RAM_DQS<4>
RAM_DQS<5>
RAM_DQS<6>
RAM_DQS<7>

40 38

RAM_VTT

5%
1/16W
MF
2 402

150
5%
1/16W

40 38

RAM_VTT

120

RP4438

40 38

RAM_VTT

5%
1/16W
MF
2 402

46 45 44 7

RAM_VTT

120

RAM_VTT 5RAM_VTT

40 38

RAM_VTT

R4400 1R4401 1R4402 1R4403 1R4404 1R4405 1R4406 1R4407

46 45 44 7

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6

40 38

RAM_VTT

C4414

RAM_DQ<33>
RAM_DQ<37>
RAM_DQ<35>
RAM_DQ<34>
RAM_DQ<32>
RAM_DQ<39>
RAM_DQ<36>
RAM_DQ<38>

PP1V25_RAM_VTT

RAM_VTT
1

PP1V25_RAM_VTT

PP1V25_RAM_VTT

PP1V25_RAM_VTT

46 45 44 7

R4409
120

R4410
150

R4411
150

7 44 45 46

C4411
0.1UF

20%
10V
2 CERM
402

RAM_CKE<0>
RAM_CKE<1>
RAM_CS_L<0>
RAM_CS_L<1>

PARALLEL TERM
R4412
4.7K

5%
1/16W
MF
402

R4413
4.7K

R4414
150

R4415
150

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

44

OF

C
103

8
46 45 44 7

PP1V25_RAM_VTT
46 45 44 7

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

40 38

40 38
40 38
40 38
40 38
40 38

C4500

RP4500
82

RP4500
82

RP4500
82

RP4501
82

RP4501
82

RP4501
82

RP4501
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

1
40 38

RAM_VTT

RP4500
82
2

0.1UF

46 45 44 7

PP1V25_RAM_VTT

RAM_VTT
1

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4510
0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38

C4507

RP4516
82

RP4516
82

RP4516
82

RP4517
82

RP4517
82

RP4517
82

RP4517
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

0.1UF

RAM_VTT

RAM_VTT
1

46 45 44 7

46 45 44 7

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

40 38
40 38
40 38
40 38

40 38
40 38
40 38
40 38

RAM_VTT

RAM_VTT

0.1UF

20%
10V
2 CERM
402

40 38

40 38
40 38
40 38
40 38
40 38
40 38

RP4504
82

RP4504
82

RP4504
82

RP4505
82

RP4505
82

RP4505
82

RP4505
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4501 1 C4511

RP4504
82

0.1UF

0.1UF

20%
2 10V
CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

C4506

RP4520
82

RP4520
82

RP4520
82

RP4520
82

RP4521
82

RP4521
82

RP4521
82

RP4521
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

RAM_DQ<79>
RAM_DQ<72>
RAM_DQ<74>
RAM_DQ<75>
RAM_DQ<77>
RAM_DQ<78>
RAM_DQ<76>
RAM_DQ<73>

PP1V25_RAM_VTT
46 45 44 7

0.1UF

120

120

120

120

120

120

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

40 38
40 38
40 38

40 38
40 38
40 38

7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

RAM_DQS<8>
RAM_DQS<9>
RAM_DQS<10>
RAM_DQS<11>
RAM_DQS<12>
RAM_DQS<13>
RAM_DQS<14>
RAM_DQS<15>

C4509

C4502

RP4508
82

RP4508
82

RP4508
82

RP4508
82

RP4509
82

RP4509
82

RP4509
82

RP4509
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

0.1UF

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4514
0.1UF

20%
2 10V
CERM
402

RAM_DQ<84>
RAM_DQ<87>
RAM_DQ<85>
RAM_DQ<82>
RAM_DQ<86>
RAM_DQ<80>
RAM_DQ<83>
RAM_DQ<81>

40 38
40 38
40 38
40 38
40 38
40 38
40 38

0.1UF

RAM_VTT

C4505

RP4524
82

RP4524
82

RP4524
82

RP4524
82

RP4525
82

RP4525
82

RP4525
82

RP4525
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

0.1UF

46 45 44 7

40 38

40 38
40 38
40 38

RAM_VTT

C4503

RP4512
82

RP4512
82

RP4512
82

RP4512
82

RP4513
82

RP4513
82

RP4513
82

RP4513
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
10V
2 CERM
402

0.1UF

RAM_VTT
1

C4516

0.1UF

RAM_VTT

RP4530

RP4530

RP4531

RP4531

RP4532

RP4532

RP4533

RP4533

150

150

150

150

150

150

150

150

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

2
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

R4508

R4509

120

120

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

RAM_RAS_L
RAM_BA<0>
RAM_CAS_L
RAM_WE_L
RAM_CS_L<9>
RAM_CS_L<8>
RAM_BA<1>
RAM_A<10>
RAM_CKE<4>
RAM_CKE<5>

RP4530

RP4530

RP4531

RP4531

RP4532

RP4532

RP4533

RP4533

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

1/16W
SM1

R4510 1R4511
4.7K

4.7K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4515
0.1UF

20%
10V
2 CERM
402

RAM_DQ<95>
RAM_DQ<94>
RAM_DQ<92>
RAM_DQ<88>
RAM_DQ<93>
RAM_DQ<89>
RAM_DQ<91>
RAM_DQ<90>

20%
10V
2 CERM
402

RAM_DQ<117>
RAM_DQ<112>
RAM_DQ<113>
RAM_DQ<114>
RAM_DQ<118>
RAM_DQ<116>
RAM_DQ<115>
RAM_DQ<119>

RAM_VTT
1

PP1V25_RAM_VTT

46 45 44 7

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

20%
10V
2 CERM
402

=PP2V5_RUN_RAM

PP1V25_RAM_VTT

C4519

PP1V25_RAM_VTT

40 38

40 38

0.1UF

0.1UF

40 38

40 38

C4518

20%
10V
2 CERM
402

C4513

40 38

40 38

20%
10V
2 CERM
402

RAM_VTT
1

20%
10V
2 CERM
402

40 38

40 38

0.1UF

C4508

RAM_DQ<111>
RAM_DQ<105>
RAM_DQ<106>
RAM_DQ<104>
RAM_DQ<109>
RAM_DQ<108>
RAM_DQ<110>
RAM_DQ<107>

RAM_VTT

40 38

46 45 44 7

RAM_VTT
1

RAM_VTT
1

46 44 7

40 38

RAM_VTT

120

20%
10V
2 CERM
402

40 38

RAM_VTT

5%
1/16W
MF
2 402

0.1UF

RAM_VTT

120

RAM_VTT

PP1V25_RAM_VTT

RAM_VTT

40 38

46 45 44 7

RAM_VTT

R4500 1R4501 1R4502 1R4503 1R4504 1R4505 1R4506 1R4507

40 38

PP1V25_RAM_VTT

RAM_VTT

C4512

RAM_DQ<97>
RAM_DQ<103>
RAM_DQ<96>
RAM_DQ<98>
RAM_DQ<102>
RAM_DQ<100>
RAM_DQ<99>
RAM_DQ<101>

PP1V25_RAM_VTT

40 38

40 38

RAM_VTT

RP4516
82
1

RAM_DQ<64>
RAM_DQ<67>
RAM_DQ<65>
RAM_DQ<66>
RAM_DQ<70>
RAM_DQ<71>
RAM_DQ<68>
RAM_DQ<69>

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

C4504

RP4528
82

RP4528
82

RP4528
82

RP4528
82

RP4529
82

RP4529
82

RP4529
82

RP4529
82

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

20%
2 10V
CERM
402

0.1UF

RAM_VTT
1

C4517
0.1UF

20%
2 10V
CERM
402

RAM_DQ<126>
RAM_DQ<123>
RAM_DQ<127>
RAM_DQ<122>
RAM_DQ<125>
RAM_DQ<124>
RAM_DQ<121>
RAM_DQ<120>

PARALLEL TERM
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

45

OF

C
103

ONLY STUFF ONE VTT VREG

46 45 44 7

=PP2V5_RUN_RAM
NOSTUFF

NOSTUFF
1

C4601

PHILIPS
353S0603

U4700_REFOUT

VDD
REFOUT

RAM_VTT
1

C4610

10K

0.1UF
10%
16V
X7R
603

R4603

5%
1/16W
MF
402

10UF
20%
6.3V
CERM
805

VTT 1

RAM_VTT
1

C4606

SHTDWN 4

VR4700_SHTDWN

0.1UF

VSS
3

VSS
U4600

10%
16V
X7R
603

NE57811
SPAK-5

RAM_VTT

NOTE: U4700 PIN 4 IS LOW ACTIVE.

NOSTUFF

PP1V25_RAM_VTT

R4610
3

TURN_ON_VTT

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.25V

5%
1/16W
MF
402

3 NOSTUFF
D

50 11 10 9 8 6

C4609

Q4600

SM

20%
2 2V
TANT
7343

220UF

2N7002

SYS_SLEEP

7 44 45

C4608

C4600

10UF

10UF

20%
6.3V
CERM
1206

20%
6.3V
CERM
1206

C4602
10UF

20%
6.3V
CERM
1206

C
PLACE 10UF CAPS NEAR DIMMS

=PP5V_RUN_RAM
VTT_ALT

C4651

0.1UF

20%
10V
CERM 2
402

NTD70N03R
CASE369
3

=PP2V5_RUN_RAM
4

46 45 44 7

VTT_ALT

Q4651

VTT_ALT

SEMTECH
353S0880

VTT_ALT
1
VCC

U4650

U4650_3

3 REF
5 FB

DRVH 6

SC1116

DRVL 4
SOT23-6L

.5%
1/16W
603 FF

5%
402
MF
1/16W

0.0047UF

NTD70N03R

CASE369

5%
402
MF
1/16W

R4674_1

C4652

10%
25V
2 CERM
402

R4674

1K

VTT_ALT

Q4652
VTT_ALT

R4673
1K

R4673_1
VTT_ALT

0.1UF 1K

20%
10V
2 CERM
402

R4672

VTT_ALT

GND

VTT_ALT

C4650

VTT_ALT
1

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
U4650_6
MIN_NECK_WIDTH=10MIL
U4650_4
MIN_LINE_WIDTH=25MIL
2

.5%
1/16W
603 FF

1K

R4671

VTT_ALT

22uF

C4655

20%
2 6.3V
CERM
1206

VTT_ALT
1

C4653
0.0047UF

10%
2 25V
CERM
402

MEM TERM VREGS


A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

46

OF

C
103

ELECTRICAL_CONSTRAINT_SET

R4800
2.2
1

5%
1/16W
MF
603

C4811 C4816
1UF
10%

2 6.3V
CERM
402

0.1UF
20%

2 10V
CERM
402

AGP_AD_0
AGP_AD_1

AGP_DATA
AGP_DATA

AGP_SB_STBF
AGP_SB_STBS
AGP_AD_STBF<0>
AGP_AD_STBS<0>
AGP_AD_STBF<1>
AGP_AD_STBS<1>

AGP_SB_STBS
AGP_SB_STBS
AGP_AD_STB_0
AGP_AD_STB_0
AGP_AD_STB_1
AGP_AD_STB_1

AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE

AGP_DBI_LO
AGP_DBI_HI

AGP_AD_1
AGP_AD_1

AGP_DATA
AGP_DATA

I55

AGP_AD<15..0>
AGP_AD<31..16>

AGP_AD_0
AGP_AD_1

AGP_DATA
AGP_DATA

I57

49 48

49 48

AGP_SBA_L<7..0>

AGP_SBA

AGP_DATA

I59

49 48

49 48
49 48
49 48

VDD_AGP

49 48

OMIT

49 48

U3

AG8 AGP_CBE0
AF8 AGP_CBE1

AGP_CBE<0>
AGP_CBE<1>

49 48
49 48

49 48

49 48
49 48

U3LITE
V1.0-300MM

AGP_AD0 AB11
AGP_AD1 AA11

PBGA

AGP_AD2 AG11

(SYM 4 OF 7)

AGP_DBI_LO

AA6 AGP_DBI_LO

AGP_AD_STBF<0>
AGP_AD_STBS<0>

AE8 AGP_AD_STBF0
AD8 AGP_AD_STBS0

AGP_AD5

AGP_AD8
AGP_AD9
AGP_AD10

AGP
INTERFACE

AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15

49 48

Y8 AGP_CBE2
AA5 AGP_CBE3

49 48

AGP_DBI_HI

AA4 AGP_DBI_HI

AGP_AD19

AGP_AD_STBF<1>
AGP_AD_STBS<1>

AA3 AGP_AD_STBF1
AA2 AGP_AD_STBS1

AGP_AD20
AGP_AD21

49 48
49 48

AD11
AE11
AF11
AH8
AH9
AH10
AH11
AG9
AF9
AE9
AD9

AGP_AD16 Y4

AGP_CBE<2>
AGP_CBE<3>

49 48

AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>

AGP_AD3 AH12
AGP_AD4 AC11
AGP_AD6
AGP_AD7

DBIHI AND DBILO


GROUPS WITH STROBE1
FOR CONSTRAINTS

AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>

AGP_AD17 Y3
AGP_AD18 Y6

AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25

AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

Y5
AA1
Y2
Y1
Y7
V5
V6
V4
V3
V8
V7
W1
AA7

48 49
49 48
48 49

AGP_SBA0 AG2

AD1 AGP_SB_STBF
AE1 AGP_SB_STBS

AGP_SB_STBF
AGP_SB_STBS

49 48

AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

49
49

49
49
49
49
49
49

49

AG3
AD2
AF2
AG1
AF1

AGP_ST<0>
AGP_ST<1>
AGP_ST<2>

AC4 AGP_ST0
AC1 AGP_ST1
AB1 AGP_ST2

AGP_RBF
AGP_WBF
AGP_TRDY
AGP_IRDY
AGP_GNT
AGP_FRAME
AGP_DEVSEL

AC6
AD6
AH5
AG6
AC3
AH6
AF6

AGP_REFCLK AH2

AGP_CLK66M_NB

49 48

48 49
49 48
48 49

AC8
AD4

NB_AGP_BUSY_L
NB_STOP_AGP_L

48 49

I52
I53
I54

D
I58

48 49
48 49

DBI_HI IS NOT A STROBE BUT SHARES THE SAME TOPOLOGY AS A STROBE

48 49
48 49
48 49
48 49
48 49
48 49

48 49

LEVEL SHIFTER FOR U3LITE

48 49
48 49

AGP BUSY AND STOP ARE NOT USED IN ALL DESIGNS


48 49
48 49
48 49

59 58 57 56 52 51 50 49 48 7

=PP3V3_AGP

48 49

49 48 7

=PP1V5_AGP

48 49
48 49

AGP_BUSYSTOP

48 49

48 49

R4812

48 49

10K
5%
1/16W
MF
2 402

48 49
48 49
48 49

R4807

10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

NB_AGP_BUSY_L

AGP_BUSY_L_F
AGP_BUSYSTOP

AGP_BUSYSTOP

Q4801

2N7002DW

48 49
48 49

49

AGP_BUSY_L

48 49

2N7002DW

SOT-363

48

Q4801

48 49

R4811

48 49

SOT-363

48 49
48 49
48 49
48 49

27

48

59 58 57 56 52 51 50 49 48 7

=PP3V3_AGP

=PP3V3_AGP

48

=PP1V5_AGP

R4810

AGP_BUSYSTOP
1

AGP_IRDY
AGP_GNT

AGP_FRAME
AGP_DEVSEL

5%
1/16W
MF
2 402

R4813

TP_VREF_CG
AGP_VREF_GC

AGP_MB_AGP8X_DET AA8

TP_AGP_MB_AGP8X_DET_L

NB_STOP_AGP_L

1K

5%
1/16W
MF
402

6
49

STOP_AGP_L

STOP_AGP_L_F

AGP_BUSYSTOP
48

AGP_VREFCG AC5

5%
1/16W
MF
2 402

10K

1%
1/16W
MF
402

5%
1/16W
MF
2 402

10K

R4809

R4801
182

10K

R4808

PVTREF RESISTOR

AC9 AGP_TYPEDET
AB8 AGP_GC_AGP8X_DET

AGP_TYPEDET_L
NB_AGP_GCDET_L

49

I51

48 49

49 48 7

AGP_TRDY

AGP_VREFGC AA9
49

I50

48 49

AGP_RBF
AGP_WBF

AB9 AGP_REQ
AH4 AGP_STOP

AGP_REQ
AGP_STOP

49

I49

I56

59 58 57 56 52 51 50 49 48 7

AGP_BUSY*
AGP_STP_AGP*

AGP_PVTREF1 AG5 AGP_PVTREF1


AGP_PVTREF2 AF5 AGP_PVTREF2
49

I48

AGP_SB_STB
AGP_SB_STB
AGP_AD_STB0
AGP_AD_STB0
AGP_AD_STB1
AGP_AD_STB1

AH7 AGP_PAR

AGP_PAR

49

AGP_SBA_L<0>
AGP_SBA_L<1>
AGP_SBA_L<2>
AGP_SBA_L<3>
AGP_SBA_L<4>
AGP_SBA_L<5>
AGP_SBA_L<6>
AGP_SBA_L<7>

AGP_SBA1 AF3
AGP_SBA2 AH1
AGP_SBA3

49

I46

48 49

6
49 48

DIFFERENTIAL_PAIR

7 48 49

49 48

AGP
REFCLK_AVDD

NET_SPACING_TYPE

AGP_CBE<1..0>
AGP_CBE<3..2>

49 48

=PP1V5_AGP

PP1V5_PWRON_AGP_NB_AVDD
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
1
1

AG4
AG10
AE2
AE7
AC10
AB4
Y11
W2
W6
W10
V9

=PP1V5_PWRON_NB_AVDD

AE6

60 37 28 7

NET_PHYSICAL_TYPE

49

3 AGP_BUSYSTOP
3

Q4803

AGP_BUSYSTOP

Q4802

2 STOP_AGP_L_R 1

2N3904

2N7002

SM

SM
2

AE5

AGP_REFCLK_AVSS

C4817
0.01UF

20%
2 16V
CERM
402

MASTER: GILA
LAST MODIFIED: APR 12, 04

=PP1V5_AGP

U3LITE AGP

7 48 49

C4800 1 C4801 1 C4802 1 C4803 1 C4804 1 C4805 1 C4806 1 C4807 1 C4808


0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

C4810 1 C4812 1 C4813 1 C4814 1 C4815


0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

10V
2 CERM
402

NOTICE OF PROPRIETARY PROPERTY

0.1UF
20%

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

10V
2 CERM
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT

NONE

REV.

051-6482
C
48 103
OF

NVIDIA RECOMMENDS A WIDER RANGE OF CAP VALUES, EMC LIKES ONE VALUE
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
49 48 7

=PP1V5_AGP

OUTPUT DRIVER BYPASS

TABLE_5_ITEM

338S0176

IC,NV18B,GRAPHIC CTRL,C1

U4900

NV18B

338S0175

IC,NV34,GRAPHIC CTRL,B1

U4900

NV34

TABLE_5_ITEM

U4900
NV18B
BGA
(1 OF 5)

U3LITE AGP I/O REFERENCE


(PLACE CLOSE TO GPU AGP BALL)

48
48

=PP1V5_AGP

48
48

R4914

48

3.32K

48

1%
1/16W
MF
2 402

48
48
48
48

48

48

R4940 1 C4940
1.02K

48

0.01UF

1%
1/16W
MF
2 402

48

20%
16V
2 CERM
402

48
48
48
48
48
48
48
48
48
48
48
48
48
48
48

48
48
48

48
48
48
48

R4912
8

GPU_RESET_L

27

5%
1/16W
MF
402

48
48

48
48

=PP3V3_AGP 7

48

48 49 50 51 52 56 57 58 59

48

R4908
4.99K
1

48
48

AGP_INT_L

49 25
6
48
48

48
48
48

NB_AGP_GCDET_L

48

AGP_TYPEDET_L

48
48

48

R4913 1R4909
0

5%
1/16W
MF
2 402

48

10K

5%
1/16W
MF
2 402

48
48

48
48

48
48
48
48
48

DOES HOOP UP AGP_BUSY_L &


STOP_AGP_L TO 3.3V OR 1.5V?

48

48

48

49

GPU_AGP_VREF

AG12 PCICLK
AF15 PCIRST*

: CLK
: RST*

AGP_GNT
AGP_REQ

AE15 PCIGNT*
AF13 PCIREQ*

: GNT
: REQ

AGP_FRAME
AGP_IRDY
AGP_TRDY
AGP_DEVSEL
AGP_STOP
AGP_PAR

AK16
AG16
AJ17
AJ16
AH17
AK18

:
:
:
:
:
:

AG15
AE10
AG14
AG17
AJ18
AJ19
AG13
AE16
AE13

AGP_INT_L
TP_GPU_INTB_L
AGP_RBF
AGP_WBF
AGP_DBI_HI
AGP_DBI_LO
AGP_ST<0>
AGP_ST<1>
AGP_ST<2>
AGP_AD_STBF<0>
AGP_AD_STBS<0>
AGP_AD_STBF<1>
AGP_AD_STBS<1>

AK24
AJ25
AG21
AF21

PCIINTA*
:
NC_PCIINTB*:
AGPRBF*
:
AGPWBF*
:
AGPPIPE*
:
<RESRVD>
:
AGPST0
:
AGPST1
:
AGPST2
:

AK13 AGPSBSTBF
AJ13 AGPSBSTBS*
AJ11 AGPSBA0
AH11 AGPSBA1
AJ12 AGPSBA2
AH12 AGPSBA3
AJ14 AGPSBA4
AH14 AGPSBA5
AJ15 AGPSBA6
AH15 AGPSBA7
AF16 <RESRVD>
AF12 AGPBUSY*
AG11 AGPSTOP*
AK29 AGPVREF

AGP_SB_STBF
AGP_SB_STBS
AGP_SBA_L<0>
AGP_SBA_L<1>
AGP_SBA_L<2>
AGP_SBA_L<3>
AGP_SBA_L<4>
AGP_SBA_L<5>
AGP_SBA_L<6>
AGP_SBA_L<7>

INTA
INTB
RBF
WBF
DBI_HI
DBI_LO
ST0
ST1
ST2

: AGPVREF

(LOW = AGP V3.X)


(HIGH = AGP V2.X)

5%
1/16W
MF
2 402

=PP3V3_AGP

NOSTUFF

R49501

NOSTUFF
1

R4951

10K

10K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

R7
T7

56 52 51 50 49 48 7
59 58 57

NO_TEST

AGP VERSION SELECT

R4903

A1
TP_GPU<0>
TP_GPU<1>AK30
G6
TP_GPU<2>

NC
1

C4906
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4913
1 0.1UF
2

C4907
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4908
1 0.1UF
2

C4909
1 0.1UF

20%
10V
CERM
402

C4910
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

CORE BYPASS

PPVCORE_GPU

C4914
1 0.01UF

C4915
1 0.01UF

10%
16V
CERM
402

C4925
1 0.01UF

C4926
1 0.01UF

10%
16V
CERM
402

C4916
1 0.1UF

10%
16V
CERM
402

C4917
1 0.1UF

20%
10V
CERM
402

C4927
1 0.1UF

10%
16V
CERM
402

20%
10V
CERM
402

C4928
1 0.1UF

20%
10V
CERM
402

C4918
1 0.1UF

20%
10V
CERM
402

C4919
1 0.1UF

20%
10V
CERM
402

C4929
1 0.1UF
2

20%
10V
CERM
402

C4930
1 0.1UF

20%
10V
CERM
402

C4920
1 0.1UF

20%
10V
CERM
402

C4921
1 0.1UF

20%
10V
CERM
402

C4931
1 0.1UF
2

C4922
1 0.1UF

20%
10V
CERM
402

C4961

C4960

10UF

10UF

20%
6.3V
CERM
805

20%
6.3V
CERM
805

C4902
10UF

20%
6.3V
CERM
805

C4900
10UF

20%
6.3V
CERM
805

C4903
10UF

20%
6.3V
CERM
805

C4901
10UF

20%
6.3V
CERM
805

C4933
1 0.1UF
2

C4934
1 0.1UF

20%
10V
CERM
402

48 49 50 51 52 56 57 58 59

NV34

1000-OHM-EMI
1

2
SM

NV34

NV34

1 C4956
0.1UF
20%
2 10V
CERM

C4959
4.7UF

1 C4955
0.001UF
10%
2 50V
CERM
402

402

I/O BYPASS
C4936
1 0.01UF
2

VD50CLAMP0 N4
VD50CLAMP1 AE9
AGP_PLLVDD AE12

AGPCALPD AA13

C4942
1 0.01UF
2

10%
16V
CERM
402

C4938
1 0.1UF
2

20%
10V
CERM
402

C4939
1 0.1UF
2

C4941
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4937
1 0.1UF
2

20%
10V
CERM
402

B
50 59

C4953
1 0.1UF

50 OHM
TO VDDQ

10%
16V
CERM
402

C4954
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4943
10UF

20%
6.3V
CERM
805

C4944
1 0.01UF
2

10%
16V
CERM
402

C4945
1 0.01UF
2

10%
16V
CERM
402

C4946
1 0.1UF
2

20%
10V
CERM
402

C4947
1 0.1UF
2

C4949
1 0.1UF

20%
10V
CERM
402

C4950
1 0.1UF

20%
10V
CERM
402

C4951
1 0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C4952
1 0.1UF
2

20%
10V
CERM
402

GPU_50PULLUP
GPU_50PULLDWN

10K OHM
TO GND

=PP1V5_AGP 7

GPU_TMODE

1 R4901
10K
5%
1/16W
2 MF
402

48 49

1 R4902
49.9

1 R4900
49.9

1%
1/16W

1%
1/16W
2 MF
402

2 MF

402

49 48 7

FROM Q27 PAGE 24

=PP1V5_AGP

1
=PP3V3_AGP 7

48 49 50 51 52 56 57 58

59

NV34

R4905
1
2
1K

NVAGP_TRST_L
TP_NVAGP_TDO
TP_NVAGP_TDI
TP_NVAGP_TMS

R4910
10K

5%
1/16W
2 MF
402

R4911
10K

5%
1/16W
2 MF
402

NVIDIA AGP

3.32K

GPU AGP I/O REFERENCE


(PLACE CLOSE TO U3LITE AGP BALLS)
GPU_AGP_VREF

VOLTAGE=0.35V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

49

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

R4907 1 C4957
1.02K

1%
1/16W
MF
2 402

R4904
1
2

II NOT TO REPRODUCE OR COPY IT

0.01UF
20%

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2 16V
CERM
402

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6482

SCALE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

NVAGP_TCLK

R4906

1%
1/16W
MF
2 402

NV34

1K

=PP3V3_AGP

L4901

20%
10V
CERM
402

BOUNDRY SCAN AVAILABLE ONLY ON NV3X SERIES

20%
10V
CERM
402

C4935
1 0.1UF

20%
10V
CERM
402

20%
6.3V
2 CERM
805

GPU_BALLR7
GPU_BALLT7

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

=PP5V_AGP 7

TESTMODE AE5

C4924
1 0.1UF

59 58 57 56 52 51 50 49 48 7

H6
AC6
U7
G14
U6
AD15
VDD33 H7
AD16
AD19
AD22
AC7
AD12
P24

50 OHM
TO GND

20%
10V
CERM
402

20%
10V
CERM
402

NV34

AGPCALPU AA14

C4923
1 0.1UF

20%
10V
CERM
402

C4932
1 0.1UF

20%
10V
CERM
402

SBA0*
SBA1*
SBA2*
SBA3*
SBA4*
SBA5*
SBA6*
SBA7*

: MBDET*
: BUSY*
: STOP*

C4905
1 0.1UF

20%
10V
CERM
402

=PP3V3_AGP 7

: SBSTBF
: SBSTBS
:
:
:
:
:
:
:
:

C4904
1 0.1UF

10%
16V
CERM
402

D
58 50

AGP_PLLVDD

FRAME
IRDY
TRDY
DEVSEL
STOP
PAR

AGPADSTBF0 : ADSTBF0
AGPADSTBS0* : ADSTBS0
AGPADSTBF1 : ADSTBF1
AGPADSTBS1* : ADSTBS1

NO_TEST

AGP 8X
C0*/BE0
C1*/BE1
C2*/BE2
C3*/BE3

AGP_CLK66M_GPU
NV_PCIRST_L

GPU_MBDET_L
AGP_BUSY_L
STOP_AGP_L

48

:
:
:
:
:

AJ24
AH19
AF25
AG22

C4911
1 0.01UF

10%
16V
CERM
402

AA17
AA18
L20
Y20
L13
Y13
N20
P20
U20
V20
VDD L11
N11
P11
U11
V11
Y11
L14
Y14
L17
Y17
L18
Y18

25 49

1%
1/16W
MF
402

48

OMIT

AGP_CBE<0>
AGP_CBE<1>
AGP_CBE<2>
AGP_CBE<3>

PCIFRAME*
PCIIRDY*
PCITRDY*
PCIDEVSEL*
PCISTOP*
PCIPAR

AE14
AE11
AE17
AE20
AGPVDDQ AE23
AD11
AD14
AD23
AD20
AD17

C2 TCLK
C1 TMS
D1 TDI
E2 TDO
D2 TRST*

AGP_VREF_GC

PCIAD0
PCIAD1
PCIAD2
PCIAD3
PCIAD4
PCIAD5
PCIAD6
PCIAD7
PCIAD8
PCIAD9
PCIAD10
PCIAD11
PCIAD12
PCIAD13
PCIAD14
PCIAD15
PCIAD16
PCIAD17
PCIAD18
PCIAD19
PCIAD20
PCIAD21
PCIAD22
PCIAD23
PCIAD24
PCIAD25
PCIAD26
PCIAD27
PCIAD28
PCIAD29
PCIAD30
PCIAD31
AGP 2X,4X
PCIC0/BE0*
PCIC1/BE1*
PCIC2/BE2*
PCIC3/BE3*

NO_TEST

49 48 7

AJ28
AK28
AH27
AK27
AJ27
AH26
AJ26
AH25
AH23
AJ23
AH22
AJ22
AJ21
AK21
AH20
AJ20
AG26
AE24
AG25
AG24
AF24
AG23
AE22
AF22
AE21
AG20
AG19
AF19
AE19
AF18
AG18
AE18

AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>
AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>

48

C4912
1 0.01UF

OF

49

103

GPU VCORE VREG


TABLE_5_HEAD

PPVCORE_GPU

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

1.60VDC

114S2803

RES,2.8K OHM,1/16W,1%,0402

R5003

NV18B

1.40VDC

114S1213

RES,1.21K OHM,1/16W,1%,0402

R5003

NV34

TABLE_5_ITEM

59 7

=PP12V_AGP

=PP3V3_AGP

D
59 49 7

=PP5V_AGP

R5000

20%
25V
CERM 2
805

20%
2 25V
CERM
805

5%
1/10W
FF
2 805

1UF

C5016
1UF

4.7

C5004

R5002

HD

U5000_COMP

VC

Q5001_GATE

0.1UF

68PF

R5001_2

20%
16V
2 CERM
603

Q5002

C5013

C5023

C5006
NOSTUFF

5%
25V
2 CERM
402

C5005

1%
1/16W
MF
2 402
1

R5004_P2

C5008
1800UF

C5012

20%
2 6.3V
ELEC
TH-KZJ

R5005

0.1UF

10K

20%
50V
2 CERM
1206

10%
50V
2 CERM
603

3900PF

10%
2 50V
CERM
603

49 50 58

VOLTAGE=1.65V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

OMIT
1

C5007 R5003
2.8K
3300PF

5%
1/4W
FF
2 1206

0.022UF

5%
50V
2 CERM
603

CASE369

220PF

5%
50V
2 CERM
603

NTD70N03R

0.51

4
1

NOSTUFF

R5004

U5000_FEEDBACK

GND

1%
1/16W
MF
2 402

C5014

PPVCORE_GPU

2
TH

U5000_GATE_L

COMP

27.4K

1.6UH

FB

PEAK CURRENT OF TOTAL RAILS


7.2A WITH NV34

L5001

U5000_GATE_H

R5001

20%
2 6.3V
ELEC
8X11.5-TH

CASE369

Q5002_DRAIN
3

C5003
390UF

20%
2 6.3V
ELEC
8X11.5-TH

NTD70N03R

SS
LD

C5002

Q5001

5%
1/10W
FF
805

IRU3037CS
SOI
8

390UF

20%
6.3V
2 CERM
1206

NOTE:
SET OUTPUT=1.60V FOR NV18B
SET OUTPUT=1.40V FOR NV34
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R5004+R5005)/R5005=1.60(OR 1.40) VDC

U5000
U5000_SS

C5001
10UF

U5000_VC

VCC

7 48 49 51 52 56
57 58 59

C5009
1800UF

GPU VTT VREG

20%
2 6.3V
ELEC
TH-KZJ

1%
1/16W
MF
2 402

55 54 52 7

PP2V5_GPU
NOSTUFF

NOSTUFF
1

C5051

U5000_FEEDBACK
2

U5050_REFOUT

VDD
REFOUT

10%
16V
X7R
603

R5050

5%
1/16W
MF
402

PP1V25_GPU_VTT

10UF
20%
6.3V
CERM
805

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.25V

NOSTUFF

C5050

SHTDWN 4

U5050_SHTDWN

C5053

U5050

VSS

VSS
3

10%
16V
X7R
603

52

NOSTUFF
1

330UF

0.1UF
2

C5052

VTT 1

NOSTUFF
1

NOSTUFF
1

10K

0.1UF

20%
2 6.3V
ELEC
SM-1

C5054
10UF

20%
6.3V
CERM
1206

NE57811
SPAK-5

NOSTUFF

AGP 1.5V VREG


PP2V5_PWRON

PLACE 10UF CAP NEAR GPU

PP1V5_PWRON
58 50 49

NOTE:
SET OUTPUT=1.5V
SC4215 VREF=0.8VDC
VOUT=VREF*(R5015+R5017)/R5017=1.5 VDC
PEAK CURRENT OF TOTAL RAILS
0.95A

PPVCORE_GPU
PP1V5_RUN

D5001
10BQ040

NOSTUFF

VR5001

SC4215
SOIC ADJ 7

EN

1%
1/10W
FF
2 805

C5020
10UF

NOSTUFF
1

R5017

SOI

NOSTUFF
1

20%
6.3V
CERM
1206

NOSTUFF
1

C5022

NOSTUFF
1

330UF
20%
2 6.3V
ELEC
SM-2

R5007
0

5%
1/10W
FF
805

PP5V_PWRON

4
5

1 2

GND

NC
THM
PAD

NC
NC
NC

10UF
2

SI4410DY

174
1

C5000
20%
6.3V
CERM
1206

Q5006

R5015

VR5001_ADJ

NOSTUFF
1

NOSTUFF

7 8

SM

VO 6

VIN

NOSTUFF

RDSON=0.012 OHM
@ VGS=3.5 V
NOSTUFF

200

C5060

1%
1/10W
FF
2 805

R5021
2

100K

0.1UF

5%
1/16W
MF
402

20%
10V
CERM
402

3
D

Q5007

NOTE:CONNECT VR5001 PIN 9 TO GND PLANE.

Q5006G

2N7002
SM

SYS_SLEEP

6 8 9 10 11 46

GRAPHICS VREGS
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

50

103

59 58 57 56 52 51 50 49 48 7

=PP3V3_AGP

TMDS_XMIT_SI

TMDS_XMIT_SI

L5102

PP3V3_SI_VCC

FERR-EMI-100-OHM
1

PP3V3_SI_AVCC

=PP3V3_AGP 7

L5101

48 49 50 51 52 56 57 58 59

FERR-EMI-100-OHM

51

VOLTAGE=3.3V

VOLTAGE=3.3V

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SM

SM

C5107

10UF
20%
6.3V
CERM
805

C5106

TMDS_XMIT_SI

C5104

100PF

100PF

5%
50V
CERM
402

5%
50V
CERM
402

TMDS_XMIT_SI

C5103

C5102

100PF

100PF

5%
50V
CERM
402

5%
50V
CERM
402

TMDS_XMIT_SI

TMDS_XMIT_SI

C5101
10UF

20%
6.3V
CERM
805

TMDS_XMIT_SI

TMDS_XMIT_SI

L5100
FERR-EMI-100-OHM
VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL

TMDS_XMIT_SI

3V_SI_PLLVCC

MIN_NECK_WIDTH=10MIL

NOTE:

SM

C5100

C5109

10UF

10UF
20%
6.3V
CERM
805

20%
6.3V
CERM
805

TMDS_XMIT_SI

C5108

C5105

100PF
2

5%
50V
CERM
402

330OHM HI SWING
RESISTOR MAY NEED TO BE
HIGHER

100PF
5%
50V
CERM
402

TMDS_XMIT_SI

TMDS_XMIT_SI

TMDS_XMIT_SI
TMDS_XMIT_SI

PLL NOISE SHOULD BE LESS THAN 100MV PEAK-TO-PEAK

R5127
330

58
58

PCI_RESET_L

2 SI_PCI_RESET_L

51

51

5%
1/16W
MF
402

4.7K

4.7K

4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

R5129

5%
1/16W
MF
402

SI_SCL
SI_SDA

27
26

57 51
57 56
57 56
57 51
57 51
57 51
57 51
57 56
57 51
57 51
57 51
57
57 56
57
57

24
25

SI_PCI_RESET_L
SI_EDGE

57 51

4.7K

SI_I2C_OFF

R5130
74 58 8 6

R5113

NC

TMDS_XMIT_SI

R5128

NOSTUFF

47
44

DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11
DVODE
DVOHSYNC
DVOVSYNC
DVOCLKOUT

5%
1/16W
MF
402

28

R5100

NOSTUFF

PVCC1
46
PVCC2 40
AVCC
34
AVCC
22
VCC
3
VCC

NOSTUFF

TMDS_XMIT_SI

18
17
16
15
14
13
10
9
8
7
6
5
19
20
21
12

MSEN 48

NC

PD*
EDGE/HTPLG

TMDS_XMIT_SI

22

TMDS_XMIT_SI

22

SI_TMDS_D1P
SI_TMDS_D1M

22

TMDS_XMIT_SI
1

TMDS_XMIT_SI

SI_TMDS_D2P
SI_TMDS_D2M

22
TMDS_XMIT_SI

22

58 59

TMDS_CKM

58 59

TMDS_D0P
TMDS_D0M

58 59

R5108

TMDS_D1P
TMDS_D1M

58 59

R5107
TMDS_XMIT_SI

TMDS_CKP

R5110

R5109
22

TMDS_XMIT_SI

R5112

R5111
22

SI_TMDS_D0P
SI_TMDS_D0M

R5106

R5105

TMDS_D2P
TMDS_D2M

58 59

58 59

58 59
58 59

5%
1/16W
MF
402

PLACE TMDS RESISTORS ON OPPOSITE SIDE TO TMDS


RESISTORS ON PAGE 25

SI_EXT_SWING_SET

PP3V3_SI_VCC

51

TMDS_XMIT_SI

R5116

49

37

23

43

31

45

29

TMDS_XMIT_SI

22

SI_TMDS_CKP
SI_TMDS_CKM

TXC+ 33
TXC- 32
U5100
D0
SIL1162
D1
TX0+ 36
TSSOP
TX0- 35
D2
D3
TMDS_XMIT_SI
TX1+ 39
D4
TX1- 38
D5
CRITICAL
TX2+ 42
D6
TX2- 41
D7
D8
D9
D10
D11
DE
HSYNC
EXT_SWING 30
VSYNC
IDCK+
VREF 2
IDCKPGND
PGND
AGND
AGND
AGND
GND
GND
GND
THRML
PAD

11

SCL/DK1
IPD
SDA/DK0
IPD
CTL3/A2
ISEL/RST* IPD

0
5%
1/16W
MF

2 402

SI_VREF

NOSTUFF

R5104 1

59 58 57 56 52 51 50 49 48 7

=PP3V3_AGP

TMDS_XMIT_SI

NOSTUFF

R5103 1

R5102 1

TMDS_XMIT_SI

R5101 1

4.7K

4.7K

4.7K

4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

NOSTUFF
1

R5117
1K

1%
1/16W
MF
402

SILICON IMAGE 1162 TMDS


1

R5120

R5119

R5124

57 51
57 51

57 51
57 51
57 51
57 51

57 51
57 51

R5126

10K

10K

10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R5118

10K

10K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R5123
1

R5122

10K

10K

5%
1/16W
MF
402

5%
1/16W
MF
2 402

2
57 51

R5121

R5125
10K

5%
1/16W
MF
2 402

DVOD11
DVOD10
DVOD9
DVOD7
DVOD6
DVOD5
DVOD4

EXTERNAL TMDS TRANSMITTER

DVOD1
DVOD0

NOTICE OF PROPRIETARY PROPERTY


LAST_MODIFIED=Wed Aug

UNDEFINED RESET CONFIGURATION STRAPS

4 17:58:08 2004

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

51

103
DRAWING

H
55 54 52 50 7 PP2V5_GPU

EVENLY DISTRIBUTE 0.01UF & 0.1 UF CAPS

NVIDIA RECOMMENDS WIDER RANGE OF CAP VALUES, EMC LIKE ONE VALUE

C5208
0.01UF

10%
16V
CERM
402

C5215
0.01UF

C5216
0.1UF

C5217
0.1UF

C5218

0.1UF

C5221
0.01UF

C5219

0.1UF

C5220
0.01UF

C5213
0.1UF

C5212
0.1UF

C5211

0.1UF

C5210
0.1UF

10%

20%

20%

20%

10%

20%

10%

20%

20%

20%

20%

1 16V
CERM

1 10V
CERM

1 10V
CERM

1 10V
CERM

1 16V
CERM

1 10V
CERM

1 16V
CERM

1 10V
CERM

1 10V
CERM

1 10V
CERM

1 10V
CERM

402

402

402

402

402

402

402

402

402

402

402

PP2V5_GPU

F17

U4900

1 C5201
10UF
2

20%
6.3V
CERM
805

C5222
0.1UF

C5224
0.1UF

C5225
0.1UF

C5226
0.01UF

C5227
0.1UF

AMONGST FBVDDQ PINS ON NV ASIC

C5228
0.1UF

C5229
0.01UF

C5200
0.1UF

C5223

0.01UF

C5214
0.1UF

C5209
0.1UF

20%

20%

20%

10%

20%

20%

10%

20%

10%

20%

20%

1 10V
CERM

1 10V
CERM

1 10V
CERM

1 16V
CERM

1 10V
CERM

1 10V
CERM

1 16V
CERM

1 10V
CERM

1 16V
CERM

1 10V
CERM

1 10V
CERM

402

402

402

402

402

402

402

402

402

402

402

1 C5202
10UF
2

20%
6.3V
CERM
805

G
7 50 52 54 55

G11
53
53

M25
K26

53

FBD<5>

53

FBD<6>

K27
J27

53

FBD<8>

H27
N29

53

FBD<9>

M29

FBD<7>

M28
L29

FBD<10>

53

FBD<11>
FBD<12>

53

FBD<13>

J28

53

FBD<14>

H29
G30

53
53
53
53

J29

FBD<15>
FBD<16>

K25
J26

FBD<17>

J25

FBD<18>

53

FBD<19>

G26

53

FBD<20>

53

FBD<21>

F28
F26
E27

53

FBD<22>
FBD<23>

53

FBD<24>

53

FBD<25>

H28
G29

53

D27

F29

53

FBD<26>
FBD<27>

53

FBD<28>

C30

53

FBD<29>

C29
B30

53

53
53
53
53
53
53

E29

FBD<30>
FBD<31>

A30
AJ29

FBD<32>
FBD<33>

AJ30
AH29

FBD<34>

AH30
AF29

FBD<35>

53

FBD<36>
FBD<37>

53

FBD<38>

AD29

53

FBD<39>

53

FBD<40>

AC28
AG28

53

FBD<41>
FBD<42>

AF27
AE26

53

FBD<43>

AE28

53

53

AE29

53

FBD<44>

AD25

53

FBD<45>

AB25

53

FBD<46>

AB26
AA25

53
53
53
53
53
53
53

FBD<47>
FBD<48>

AD30
AC29

FBD<49>
FBD<50>

AB28
AB29

FBD<51>
FBD<52>

Y29
W28

FBD<53>
FBD<55>

W29
V29

FBD<56>
FBD<57>

AC27
AB27

53

FBD<58>
FBD<59>

AA27
AA26

53

FBD<60>

W25

53
53
53
53
53

53
53
53

FBD<54>

FBD<62>
FBD<63>

FBDQM<0>

54

FBDQM<1>

54

V26
V27

FBD<61>

54

54

V25

L27
K29
G25

FBDQM<2>
FBDQM<3>

E28
AF28

54

FBDQM<4>
FBDQM<5>

54

FBDQM<6>

AA30

54

FBDQM<7>

Y27

54

54

FBA<0>

54

FBA<1>

54
54
54
54
54

N27
N26

FBD<4>

53

FBD<2>

53

53

N25

FBD<1>

53

53

FBD<0>

FBD<3>

53

54
54
54

54
54
54

T27
T30
T26
T25

FBA<8>
FBA<9>

FBA<12>

54

T28
T29

FBA<6>
FBA<7>

54

54

U29

FBA<4>
FBA<5>

54

54

V30
U28

FBA<2>
FBA<3>

FBA<10>
FBA<11>

54

AD27

R27
R25
R30
U24
R26

FBABA<0>
FBABA<1>

R29
P28

FBARAS_L

P29

FBACAS_L
FBAWE_L

R28
U27

FBACS0_L
TP_FBACS1_L

TESTPOINT

GPU_FB_VREF
56
56

ROMA14

TESTPOINT

ROMA15
TP_ROMCS_L

TESTPOINT
TESTPOINT

P27

NV18B
BGA

G8
FBAD0
F8
FBAD1 (3 OF 5)
L25
FBAD2
OMIT
Y25
FBAD3
F11
FBAD4
F14
FBAD5
F20
FBAD6
FBAD7
FBVDDQ F23
Y24
FBAD8
L24
FBAD9
G20
FBAD10
G23
FBAD11
H24
FBAD12
AC24
FBAD13
H25
FBAD14
P25
FBAD15
U25
FBAD16
AC25
FBAD17
FBAD18
G9
FBAD19
G12
G15
FBAD20
G16
G19
FBAD21
G22
NC_VTT J24
FBAD22
M24
R24
FBAD23
T24
W24
FBAD24
AB24
FBAD25
A25
FBAD26
AK25
AA5
FBAD27
AF20
AH16
FBAD28
AK15
AF11
FBAD29
AH21
U26
FBAD30
AD28
AH18
FBAD31
F25
C18
FBAD32
E14
AF8
FBAD33
Y8
K3
FBAD34
G3
F6
FBAD35
AF17
AF23
FBAD36
AH24
AH28
FBAD37
AG27
AF26
FBAD38
AF14
AH13
FBAD39
L8
P26
FBAD40
G28
K28
FBAD41
N28
V28
FBAD42
AA28
F30
FBAD43
J30
M30
FBAD44
W30
AB30
FBAD45
AE30
H26
FBAD46
L26
Y26
FBAD47
AC26
GND E17
FBAD48
D28
C7
FBAD49
E8
A9
FBAD50
C10
E11
FBAD51
C13
E20
FBAD52
C21
E23
FBAD53
C24
A6
FBAD54
A12
AH10
FBAD55
AK12
C3
FBAD56
D4
E5
FBAD57
AG4
AH3
FBAD58
AK6
AH7
FBAD59
AF5
AE6
FBAD60
AK9
N3
FBAD61
H11
AC11
FBAD62
H20
AC20
FBAD63
L23

FBCAL_PD_VDDQ F5
FBCAL_TERM_GND D3
FBCAL_CLK_GND E3
FB_DLLVDD C27

PP1V25_GPU_VTT

NV36

C5250
0.1UF

20%
10V
2 CERM
402

FBVREF

R2
R1

ROMA14
ROMA15
ROMCS*

F27
D29
AG29
AE27
Y28
W26

53

FBD<66>

E13

53

FBD<67>

F12

53

FBD<68>

E10
D10

53

FBD<69>
FBD<70>

53

FBD<71>

53

FBD<72>

53

FBD<73>

B13
B12

53

FBD<74>

C12

53

FBD<75>

B11

FBD<76>
FBD<77>

B9

53
53

FBD<78>

B8

53

FBD<79>

A7
F10

NV36

C5251
0.1UF

20%
10V
2 CERM
402

NV36

C5252
0.1UF

20%
10V
2 CERM
402

NV36

C5253
0.1UF

20%
10V
2 CERM
402

NV36

C5254
0.1UF

20%
10V
2 CERM
402

NV36

C5255

C5256

0.1UF

NV36

0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

NV36

C5257
0.1UF

20%
10V
2 CERM
402

C5258
0.1UF

20%
10V
2 CERM
402

NV36
1

NV36

C5259
0.1UF

20%
10V
2 CERM
402

C5260
0.1UF

20%
10V
2 CERM
402

NV36
1

C5261
0.1UF

20%
10V
2 CERM
402

FBD<82>
FBD<83>

53

FBD<84>

F7
C6

53

FBD<85>

53

FBD<86>

53

FBD<87>

53

FBD<88>
FBD<89>

53

FBD<90>

53

FBD<93>

B3

53

FBD<94>

A2

FBD<95>
FBD<96>

B2

53

54 53 52

FBACLK0_L
FBACLK1

54 53 52

FBACLK1_L

54 53 52

53

I373

FBCLK
FBCLK
FBCLK

I375

I374

FBBCLK0

FBACLK1
FBBCLK0

FBBCLK0_L
FBBCLK1

FBBCLK0
FBBCLK1

FBCLK

I377

55 53 52

FBCLK

I378

55 53 52

FBBCLK1_L

FBBCLK1

FBCLK

I379

55 53 52
55 53 52

53

FBD<104>

E26
D26

53
53

FBD<107>

E25
C25

53

FBD<108>

E24

FBD<109>

F22

FBD<110>
FBD<111>

E22

FBD<112>
FBD<113>

A24

FBD<114>
FBD<115>

C22

53
53
53
53
53
53

FBD<119>

B18
D23

53

FBD<124>

F19
E18

53

FBD<125>
FBD<126>

53

FBD<127>

F18

FBDQM<8>

D11

55

FBDQM<9>

B10
D7

55
55

FBDQM<12>

C26

55

FBDQM<13>
FBDQM<14>

F24
B21

55

FBDQM<15>

D20

1 NV34
R5203
49.9

55

FBBA<0>

1%
1/16W
MF

55

FBBA<1>
FBBA<2>

A18
C17

55

FBBA<3>

B17
C16

FBBA<4>
FBBA<5>

B16
D16

55

FBBA<6>

55

FBBA<7>

A16
E16

FBCAL_PU_GND

FBACLK1
FBACLK1_L
FBACLK0
FBACLK0_L
FBDQS<0>
FBDQS<1>
FBDQS<2>
FBDQS<3>
FBDQS<4>
FBDQS<5>

52 53 54

1%
1/16W
MF
2 402

52 53 54
52 53 54

R5208

55

2 402

55

1%
1/16W
MF
2 402

1
R5201
10K

52 53 54

NOSTUFF
1

D18

55

55

549

E21

FBDQM<10>
FBDQM<11>

FBCAL_PD_VDDQ

R5207

D22
D21

53

55

NOSTUFF

FBD<120>
FBD<121>
FBD<122>
FBD<123>

53

54 FBACKE

C19

FBD<118>

7 50 52 54 55

FB_DLLVDD

B22
B20

53

53

FBCAL_CLK_GND

B23

53

53

FBCAL_TERM_GND

FBD<116>
FBD<117>

F21

B19

53

B24

FBD<105>
FBD<106>

53

1%
1/16W
MF
402

B26
B25
C23

53

1 NV34
R5202
49.9

A28

FBD<103>

53

PP2V5_GPU

B28

53

53

I376

FBD<99>
FBD<100>

B29
A29

53

I372

FBACLK1

FBD<97>
FBD<98>

A3

FBD<101>
FBD<102>

53

FBCLK
FBCLK

B7
B6

53

53

FBACLK0
FBACLK0

C4
C8

B5

53

FBACLK0

E6
D5

FBD<91>
FBD<92>

53

54 53 52

E9

53

53

NET_SPACING_TYPE

C9

53

53

DIFFERENTIAL_PAIR

FBD<80>
FBD<81>

D9
D8

F9

53

M27

L28

D13

53

NV36

FBADQS0
K30
FBADQS1
G27
FBADQS2
D30
FBADQS3
AG30
FBADQS4
AD26
FBADQS5
AA29
FBADQS6
W27
FBADQS7
M26

FBD<65>

53

FBACLK0 U21
FBACLK0* V21
FBACLK1 N21
FBACLK1* P21

NC_FBADQS0*
NC_FBADQS1*
NC_FBADQS2*
NC_FBADQS3*
NC_FBADQS4*
NC_FBADQS5*
NC_FBADQS6*
NC_FBADQS7*

53

50

FBARAS*
FBACAS*
FBAWE*
FBACS0*
FBACS1*

F13

53

FBACKE N30

FBABA0
FBABA1

FBD<64>

53

AK19
A22
AK22
K5
J7
AE25

FBCAL_PU_GND E4

C28

AF2

NV18B

Y23
F1
J1
M1
T1
W1
AB1
AE1
A19

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12

U4900

53

55

5%
1/16W
MF
2 402

55
55

55

FBBA<10>
FBBA<11>

55

FBBA<12>

55

53
53
53

FBBA<8>
FBBA<9>

C5

RECOMMANDED NY NVIDIA.

55

53
55

FBBBA<0>
FBBBA<1>

N13

FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7

D12

FBDQS<8>

53

A10
E7

FBDQS<9>

53

FBDQS<10>

53

A4
A27

FBDQS<11>

53

FBDQS<12>

53

D24
A21

FBDQS<13>
FBDQS<14>

53

D19

FBDQS<15>

53

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

A15
G17

FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBCA12

E15
B15

FBCBA0
FBCBA1

F16
D15
F15

WEAK PULL-DOWN
53

FBCD0 (4 BGA
OF 5)
FBCD1
OMIT
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
THERMAL GND
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

NC_FBCDQS0*
NC_FBCDQS1*
NC_FBCDQS2*
NC_FBCDQS3*
NC_FBCDQS4*
NC_FBCDQS5*
NC_FBCDQS6*
NC_FBCDQS7*
FBCRAS*
FBCCAS*
FBCWE*
FBCCS0*
FBCCS1*
FBCCKE

P13
U13
V13
M14
N14
P14
R14
T14
U14
V14
W14
M15
N15
P15
R15
T15

U15
V15
W15
M16
N16
P16
R16
T16
U16
V16
W16
M17
N17
P17
R17
T17
U17
V17
W17
M18
N18

P18
R18
T18
U18
V18
W18
M19
N19
P19
R19
T19
U19
V19
W19
P12
N12
V12
U12
M12
R12
T12

W12
M13
R13
T13
W13

E12
C11
D6
B4
B27
D25
C20
E19

NC
NC
NC
NC
NC

NC

FBBRAS_L
FBBCAS_L

B14
C15
TESTPOINT

FBDQS<6>

53

55 53 52

FBDQS<7>

53

55 53 52
55 53 52
55 53 52

FBBCLK1
FBBCLK1_L
FBBCLK0
FBBCLK0_L

K18
K17
K13
K14

55
55
55

TP_FBBCS1_L

55 FBBCKE

53

NC

55

FBBWE_L
FBBCS0_L

D17
A13

NC

C14

D14

53

NC

1
R5200
10K

FBBCLK0
FBBCLK0*
FBBCLK1
FBBCLK1*

1%
1/16W
MF

WEAK PULL-DOWN

2 402
RECOMMENDED BY NVIDIA

NC
FBBCLK 0 AND 1 SWAPPED FOR ROUTING REASONS
NC
NC
NC

NV34

R5206

NC
NC
NC

52 52

FB_DLLVDD

=PP3V3_AGP

7 48 49 50 51 56 57 58 59

10
1

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

NV34
1

C5205

NV34
1

4.7UF
2

N20P80%
10V
CERM
805

C5206

NV34
1

0.1UF
2

20%
10V
CERM
402

C5207

2
1%
1/10W
FF
805

ALTERNATE STUFFING FOR 10 OHM R


IS FILTER APN 155S0052 PER NVIDIA SPEC

0.001UF
2

10%
50V
CERM
402

55 54 52 50 7 PP2V5_GPU

1
R5204
1K
1%
1/16W
MF

VOLTAGE=1.25V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

1
R5205
1K
1%
1/16W
MF

1 C5203
0.1UF
2

2 402

NVIDIA FRAME BUFFER

20%
10V
CERM
402

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

1 C5204
0.1UF
2

2 402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

20%
10V
CERM
402

SIZE DRAWING NUMBER

APPLE COMPUTER INC.

E
SCALE
NONE

REV.

051-6482
SHT

??

OF

52

103

PLACE RS CLOSE TO MEMORY


52
52
52
52
52
52
52

52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52

C
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52

52
52
52
52
52
52
52

FBD<31>
FBD<30>
FBD<29>
FBD<28>
FBD<27>
FBD<26>
FBD<25>
FBD<24>
FBD<0>
FBD<1>
FBD<2>
FBD<3>
FBD<17>
FBD<16>
FBD<18>
FBD<19>
FBD<15>
FBD<14>
FBD<13>
FBD<12>
FBD<10>
FBD<11>
FBD<9>
FBD<8>
FBD<5>
FBD<6>
FBD<4>
FBD<7>
FBD<20>
FBD<21>
FBD<22>
FBD<23>

FBD<64>
FBD<65>
FBD<66>
FBD<67>
FBD<84>
FBD<85>
FBD<86>
FBD<87>
FBD<72>
FBD<73>
FBD<75>
FBD<74>
FBD<68>
FBD<70>
FBD<69>
FBD<71>
FBD<80>
FBD<81>
FBD<82>
FBD<83>
FBD<76>
FBD<77>
FBD<78>
FBD<79>
FBD<91>
FBD<90>
FBD<89>
FBD<88>
FBD<95>
FBD<94>
FBD<93>
FBD<92>

GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4

8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5

RP5320
RP5320
RP5320
RP5320
RP5321
RP5321
RP5321
RP5321
RP5322
RP5322
RP5322
RP5322
RP5323
RP5323
RP5323
RP5323
RP5324
RP5324
RP5324
RP5324
RP5325
RP5325
RP5325
RP5325
RP5326
RP5326
RP5326
RP5326
RP5327
RP5327
RP5327
RP5327

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

1
2
3
4
1
2
3
4
4
3
2
1
1
2
3
4
1
2
3
4
4
3
2
1
1
2
3
4
1
2
3
4

8
7
6
5
8
7
6
5
5
6
7
8
8
7
6
5
8
7
6
5
5
6
7
8
8
7
6
5
8
7
6
5

RP5310
RP5310
RP5310
RP5310
RP5309
RP5309
RP5309
RP5309
RP5319
RP5319
RP5319
RP5319
RP5308
RP5308
RP5308
RP5308
RP5307
RP5307
RP5307
RP5307
RP5317
RP5317
RP5317
RP5317
RP5318
RP5318
RP5318
RP5318
RP5303
RP5303
RP5303
RP5303

RFBD<31>
RFBD<30>
RFBD<29>
RFBD<28>
RFBD<27>
RFBD<26>
RFBD<25>
RFBD<24>
RFBD<0>
RFBD<1>
RFBD<2>
RFBD<3>
RFBD<17>
RFBD<16>
RFBD<18>
RFBD<19>
RFBD<15>
RFBD<14>
RFBD<13>
RFBD<12>
RFBD<10>
RFBD<11>
RFBD<9>
RFBD<8>
RFBD<5>
RFBD<6>
RFBD<4>
RFBD<7>
RFBD<20>
RFBD<21>
RFBD<22>
RFBD<23>

RFBD<64>
RFBD<65>
RFBD<66>
RFBD<67>
RFBD<84>
RFBD<85>
RFBD<86>
RFBD<87>
RFBD<72>
RFBD<73>
RFBD<75>
RFBD<74>
RFBD<68>
RFBD<70>
RFBD<69>
RFBD<71>
RFBD<80>
RFBD<81>
RFBD<82>
RFBD<83>
RFBD<76>
RFBD<77>
RFBD<78>
RFBD<79>
RFBD<91>
RFBD<90>
RFBD<89>
RFBD<88>
RFBD<95>
RFBD<94>
RFBD<93>
RFBD<92>

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

54

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52

55

52
52

55

52

55

FBD<32>
FBD<33>
FBD<34>
FBD<35>
FBD<36>
FBD<37>
FBD<38>
FBD<39>
FBD<40>
FBD<41>
FBD<42>
FBD<43>
FBD<44>
FBD<45>
FBD<46>
FBD<47>
FBD<48>
FBD<49>
FBD<50>
FBD<51>
FBD<52>
FBD<53>
FBD<54>
FBD<55>
FBD<56>
FBD<57>
FBD<58>
FBD<59>
FBD<60>
FBD<61>
FBD<62>
FBD<63>

FBD<96>
FBD<97>
FBD<98>
FBD<99>
FBD<100>
FBD<101>
FBD<102>
FBD<103>
FBD<104>
FBD<105>
FBD<106>
FBD<107>
FBD<108>
FBD<109>
FBD<110>
FBD<111>
FBD<112>
FBD<113>
FBD<114>
FBD<115>
FBD<116>
FBD<117>
FBD<118>
FBD<119>
FBD<120>
FBD<121>
FBD<122>
FBD<123>
FBD<124>
FBD<125>
FBD<126>
FBD<127>

GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

3
4
1
2
4
3
2
1
2
1
3
4
1
2
4
3
4
3
1
2
4
3
2
1
1
2
4
3
1
3
2
4

6
5
8
7
5
6
7
8
7
8
6
5
8
7
5
6
5
6
8
7
5
6
7
8
8
7
5
6
8
6
7
5

RP5328
RP5328
RP5328
RP5328
RP5316
RP5316
RP5316
RP5316
RP5329
RP5329
RP5329
RP5329
RP5330
RP5330
RP5330
RP5330
RP5331
RP5331
RP5331
RP5331
RP5300
RP5300
RP5300
RP5300
RP5301
RP5301
RP5301
RP5301
RP5302
RP5302
RP5302
RP5302

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

4
3
2
1
4
3
2
1
1
2
3
4
1
2
3
4
4
3
2
1
4
3
2
1
1
2
4
3
1
3
2
4

5
6
7
8
5
6
7
8
8
7
6
5
8
7
6
5
5
6
7
8
5
6
7
8
8
7
5
6
8
6
7
5

RP5315
RP5315
RP5315
RP5315
RP5314
RP5314
RP5314
RP5314
RP5312
RP5312
RP5312
RP5312
RP5313
RP5313
RP5313
RP5313
RP5311
RP5311
RP5311
RP5311
RP5306
RP5306
RP5306
RP5306
RP5304
RP5304
RP5304
RP5304
RP5305
RP5305
RP5305
RP5305

RFBD<32>
RFBD<33>
RFBD<34>
RFBD<35>
RFBD<36>
RFBD<37>
RFBD<38>
RFBD<39>
RFBD<40>
RFBD<41>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<45>
RFBD<46>
RFBD<47>
RFBD<48>
RFBD<49>
RFBD<50>
RFBD<51>
RFBD<52>
RFBD<53>
RFBD<54>
RFBD<55>
RFBD<56>
RFBD<57>
RFBD<58>
RFBD<59>
RFBD<60>
RFBD<61>
RFBD<62>
RFBD<63>

RFBD<96>
RFBD<97>
RFBD<98>
RFBD<99>
RFBD<100>
RFBD<101>
RFBD<102>
RFBD<103>
RFBD<104>
RFBD<105>
RFBD<106>
RFBD<107>
RFBD<108>
RFBD<109>
RFBD<110>
RFBD<111>
RFBD<112>
RFBD<113>
RFBD<114>
RFBD<115>
RFBD<116>
RFBD<117>
RFBD<118>
RFBD<119>
RFBD<120>
RFBD<121>
RFBD<122>
RFBD<123>
RFBD<124>
RFBD<125>
RFBD<126>
RFBD<127>

54
54
54
54

PLACE RS CLOSE TO GPU

54
54
54
54

54 52

54

1
R5316
100

54

1%
1/16W
MF
402

54
54
54
54

52

52

52

52

FBDQS<0>

FBDQS<1>

R5302
15

1%
1/16W
MF
402

FBDQS<2>

FBDQS<3>

R5303
15

52

52

52

FBDQS<4>

FBDQS<5>

R5305
15

FBDQS<6>

FBDQS<7>

R5304
15

RFBDQS<1>

R5307
15

R5306
15
1%
1/16W
MF
402

RFBDQS<2>

54
54
54
54
54

1
R5317
100

54

1%
1/16W
MF
402

54
54
54
54

RFBDQS<4>

RFBDQS<6>

55
GPU128BIT

1
R5318
100

55
55

1%
1/16W
MF
402

55
55

PLACE 100OHM TERM AT RAM

55
55

55 52

FBBCLK1_L

55 52

FBBCLK0

55
55
55
55
55
55
55
55
GPU128BIT

1
R5319
100

55
55

1%
1/16W
MF
402

55
55

PLACE 100OHM TERM AT RAM

55
55

55 52

FBBCLK0_L

55
55
55

55
55
55
55
55
55
55

PLACE THESE R CLOSE TO SGRAM


54

52

FBDQS<8>

54

52

FBDQS<9>

54

52

54

52

FBDQS<10>

FBDQS<11>

54

52

54

52

54

52

54

52

R5314
15

R5315
15

FBDQS<12>

FBDQS<13>

R5312
15

R5309
15

R5310
15

R5311
15
1%
1/16W
MF
402

RFBDQS<8>

55

RFBDQS<9>

55

RFBDQS<10>

55

RFBDQS<11>

55

RFBDQS<12>

55

RFBDQS<13>

55

FROM Q27 PAGE 26

1%
1/16W
MF
402

1%
1/16W
MF
402

FBDQS<14>

FBDQS<15>

R5313
15

1%
1/16W
MF
402

1%
1/16W
MF
402

R5308
15
1%
1/16W
MF
402

1%
1/16W
MF
402

GPU128BIT

RFBDQS<7>

FBBCLK1

55

GPU128BIT

55 52

54

GPU128BIT

RFBDQS<5>

FBACLK0_L

54

GPU128BIT

54 52

PLACE 100OHM TERM AT RAM

54

GPU128BIT

RFBDQS<3>

FBACLK0

54

GPU128BIT

1%
1/16W
MF
402

1%
1/16W
MF
402

R5300
15

54 52

54

GPU128BIT

1%
1/16W
MF
402

1%
1/16W
MF
402
52

1%
1/16W
MF
402

RFBDQS<0>

FBACLK1_L

54

GPU128BIT

54 52

PLACE 100OHM TERM AT RAM

54

PLACE THESE R CLOSE TO SGRAM


R5301
15

FBACLK1

54

RFBDQS<14>

55

RFBDQS<15>

55

FB TERMINATION
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1%
1/16W
MF
402

1%
1/16W
MF
402

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

53

103

55 54 52 50 7

55 54 52 50 7

PP2V5_GPU

PP2V5_GPU

PLACE NEAR VDD PINS

55 54 52 50 7

PP2V5_GPU

PLACE NEAR VDD PINS

NVIDIA RECOMMENDS WIDER RANGE OF CAP VALUES


1 C5424
0.1UF
2

1 C5425
0.1UF

20%
10V
CERM
402

1 C5426
0.1UF

20%
10V
CERM
402

C5415

1 C5422
0.001UF

20%
10V
CERM
402

1 C5427
0.1UF

10%
50V
CERM
402

1 C5428
0.1UF

20%
10V
CERM
402

1 C5429
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5423
0.001UF
2

1 10UF
20%
6.3V
2 CERM
805

10%
50V
CERM
402

C5414

C5401

1 10UF
20%
6.3V
2 CERM
805

C5400
1 10UF
20%
6.3V
2 CERM
805

1 10UF
20%
6.3V
2 CERM
805

D
55 54 52 50 7

55 54 52 50 7

PP2V5_GPU

PP2V5_GPU
OMIT
OMIT

U5401
SDRAM_DDR_4MX32

U5400
SDRAM_DDR_4MX32

BGA

BGA
(2 OF 2)

D7
D8
E4
E11
L4
L7
L8
L11

C
54

SGRAVREF

VDD
VSS

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

OMIT

U5400
SDRAM_DDR_4MX32
54 52
54 52
54 52
54 52
54 52

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

54 52
54 52
54 52
54 52
54 52

53
53

52
52
52
52

54 52
54 52

1 C5434

0.1UF
2

20%
10V
CERM
402

VSSQ

B2
H13
H2
B13

RFBDQS<0>
RFBDQS<3>
RFBDQS<1>
RFBDQS<2>

53
53

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

FBA<0>
FBA<1>
FBA<2>
FBA<3>
FBA<4>
FBA<5>
FBA<6>
FBA<7>
FBA<8>
FBA<9>
FBA<10>
FBA<11>

54 52

54 52

VSS_THERM

D7
D8
E4
E11
L4
L7
L8
L11

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBABA<0>
FBABA<1>

N4
M5

BA0
BA1

M11
M12
N12
N2
M2
L2
L3

53 52
54 52
54 52
54 52
54 52
54 52

C4
C11
H4
H11
L12
L13
M3
M4
N3

55 54 52 50 7

BGA
(1 OF 2)

DQS0
DQS1
DQS2
DQS3

FBDQM<0>
FBDQM<3>
FBDQM<1>
FBDQM<2>

FBACLK0
FBACLK0_L
FBACKE
FBACS0_L
FBARAS_L
FBACAS_L
FBAWE_L

53 52

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

CK
CK
CKE
CS
RAS
CAS
WE

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

RFBD<7>
RFBD<5>
RFBD<6>
RFBD<4>
RFBD<2>
RFBD<3>
RFBD<1>
RFBD<0>
RFBD<31>
RFBD<30>
RFBD<29>
RFBD<28>
RFBD<27>
RFBD<26>
RFBD<25>
RFBD<24>
RFBD<15>
RFBD<14>
RFBD<13>
RFBD<12>
RFBD<10>
RFBD<11>
RFBD<8>
RFBD<9>
RFBD<23>
RFBD<22>
RFBD<21>
RFBD<20>
RFBD<19>
RFBD<16>
RFBD<18>
RFBD<17>

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

10%
50V
CERM
402

1 C5408
0.1UF

1 C5409
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5419
0.001UF
2

10%
50V
CERM
402

1 C5410
0.1UF

1 C5411
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

53

54

10%
50V
CERM
402

1 C5412
0.1UF

1 C5413
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

SGRAVREF

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

OMIT

U5401
SDRAM_DDR_4MX32

53

1 C5435

53

0.1UF

53

2
53

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

RFBDQS<6>
RFBDQS<4>
RFBDQS<7>
RFBDQS<5>

B2
H13
H2
B13

DQS0
DQS1
DQS2
DQS3

FBDQM<6>
FBDQM<4>
FBDQM<7>
FBDQM<5>

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBABA<0>
FBABA<1>

N4
M5

BA0
BA1

FBACLK1
FBACLK1_L
FBACKE
FBACS0_L
FBARAS_L
FBACAS_L
FBAWE_L

M11
M12
N12
N2
M2
L2
L3

CK
CK
CKE
CS
RAS
CAS
WE

54 52
54 52
54 52
54 52
54 52

VSS_THERM

20%
10V
CERM
402

53
53
53
53
53

VSSQ

53

FBA<12>
TP_U5400_RFU2

FBA<0>
FBA<1>
FBA<2>
FBA<3>
FBA<4>
FBA<5>
FBA<6>
FBA<7>
FBA<8>
FBA<9>
FBA<10>
FBA<11>

54 52

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

54 52
54 52
54 52
54 52
54 52
54 52

53
53
53
53

52
52
52
52

54 52

52 54
NO_TEST

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

54 52

53 52
53 52
54 52
54 52
54 52
54 52
54 52

C4
C11
H4
H11
L12
L13
M3
M4
N3

BGA
(1 OF 2)

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

RFBD<48>
RFBD<49>
RFBD<50>
RFBD<51>
RFBD<53>
RFBD<52>
RFBD<54>
RFBD<55>
RFBD<32>
RFBD<33>
RFBD<35>
RFBD<34>
RFBD<37>
RFBD<36>
RFBD<38>
RFBD<39>
RFBD<57>
RFBD<56>
RFBD<58>
RFBD<59>
RFBD<62>
RFBD<60>
RFBD<61>
RFBD<63>
RFBD<41>
RFBD<40>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<47>
RFBD<45>
RFBD<46>

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

FBA<12> 52 54
TP_U5401_RFU2
NO_TEST

PP2V5_GPU

1 C5421
0.001UF
2

VSS

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

53

PP2V5_GPU

1 C5420
0.001UF

VDD

53

55 54 52 50 7

1 C5418
0.001UF

(2 OF 2)

1 C5433
0.001UF

10%
50V
CERM
402

10%
50V
CERM
402

1 C5402
0.1UF

1 C5403
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5430
0.001UF
2

10%
50V
CERM
402

1 C5404
0.1UF

1 C5405
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5431
0.001UF
2

10%
50V
CERM
402

1 C5406
0.1UF

1 C5407
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5432
0.001UF
2

10%
50V
CERM
402

EVENLY PLACE 0.1UF CAP & 0.01UF CAPS

DDR SDRAM A VREF


PP2V5_GPU
55 54 52 50 7

1
R5400
1K

1%
1/16W
MF
402

20%
10V
CERM
402

SGRAM0 & SGRAM1 MEMORY SUPPORT

PART NUMBER

QTY

GPU DDR SDRAM A

1 C5416
0.1UF

DESCRIPTION

REFERENCE DES

333S0251

SDRAM,4MX32,DDR,300MHZ

U5400,U5401

CRITICAL
CRITICAL

SAMSUNG

333S0252

SDRAM,4MX32,DDR,300MHZ

U5400,U5401

CRITICAL

HYNIX

1
R5401
1K

BOM OPTION

1%
1/16W
MF
402

1 C5417
0.1UF
2

54

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

20%
10V
CERM
402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6482

SCALE

NOTICE OF PROPRIETARY PROPERTY


SGRAVREF
VOLTAGE=1.25V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

OF

54

103

55 54 52 50 7

55 54 52 50 7

PP2V5_GPU

5
PP2V5_GPU

55 54 52 50 7

PLACE NEAR VDD PINS

PP2V5_GPU

PLACE NEAR VDD PINS


GPU128BIT

GPU128BIT

GPU128BIT

1 C5518
0.1UF
2

55 54 52 50 7

GPU128BIT

1 C5519
0.1UF

20%
10V
CERM
402

GPU128BIT

1 C5520
0.1UF

20%
10V
CERM
402

GPU128BIT

1 C5521
0.001UF

20%
10V
CERM
402

GPU128BIT

1 C5522
0.1UF

10%
50V
CERM
402

GPU128BIT

1 C5523
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

C5515

GPU128BIT

1 C5524
0.1UF

1 C5525
0.001UF

20%
10V
CERM
402

1 10UF
20%
6.3V
2 CERM
805

10%
50V
CERM
402

D7
D8
E4
E11
L4
L7
L8
L11

C5500
1 10UF
20%
6.3V
2 CERM
805

U5501
SDRAM_DDR_4MX32
BGA

SGRBVREF

(2 OF 2)

OMIT

VDD
VSS

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

55 52
55 52
55 52
55 52
55 52
55 52

VSS_THERM

GPU128BIT

1 C5534

0.1UF
2

20%
10V
CERM
402

VSSQ

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

55 52
55 52
55 52
55 52
55 52

RFBDQS<8>
RFBDQS<11>
RFBDQS<9>
RFBDQS<10>

53
53
53
53

52
52
52
52

DM0
DM1
DM2
DM3

FBBBA<0>
FBBBA<1>

N4
M5

BA0
BA1

M11
M12
N12
N2
M2
L2
L3

53 52
55 52
55 52
55 52
55 52
55 52

C4
C11
H4
H11
L12
L13
M3
M4
N3

GPU128BIT

GPU128BIT

1 C5508
0.1UF
2

1 C5509
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

GPU128BIT

1 C5527
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5510
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5511
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5528
0.001UF
2

10%
50V
CERM
402

NC

OMIT

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

RFBD<71>
RFBD<69>
RFBD<70>
RFBD<68>
RFBD<65>
RFBD<67>
RFBD<66>
RFBD<64>
RFBD<95>
RFBD<94>
RFBD<93>
RFBD<92>
RFBD<91>
RFBD<90>
RFBD<89>
RFBD<88>
RFBD<79>
RFBD<78>
RFBD<77>
RFBD<76>
RFBD<74>
RFBD<75>
RFBD<72>
RFBD<73>
RFBD<87>
RFBD<86>
RFBD<85>
RFBD<84>
RFBD<83>
RFBD<81>
RFBD<82>
RFBD<80>

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

20%
10V
CERM
402

OMIT

VDD

VDDQ

N13

VREF

VSS

VSS_THERM

53
55

53

SGRBVREF

GPU128BIT

1 C5535

53

0.1UF

53

53
53

20%
10V
CERM
402

53
53
53
53

VSSQ

53

55
NO_TEST

GPU128BIT

10%
50V
CERM
402

1%
1/16W
MF

2 402

55 52
55 52
55 52
55 52

53
53
53
53

52
52
52
52

55 52

53 52
53 52
55 52
55 52
55 52
55 52
55 52

RFBDQS<14>
RFBDQS<12>
RFBDQS<15>
RFBDQS<13>

B2
H13
H2
B13

DQS0
DQS1
DQS2
DQS3

FBDQM<14>
FBDQM<12>
FBDQM<15>
FBDQM<13>

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBBBA<0>
FBBBA<1>

N4
M5

BA0
BA1

FBBCLK1
FBBCLK1_L
FBBCKE
FBBCS0_L
FBBRAS_L
FBBCAS_L
FBBWE_L

M11
M12
N12
N2
M2
L2
L3

CK
CK
CKE
CS
RAS
CAS
WE

C4
C11
H4
H11
L12
L13
M3
M4
N3

(1 OF 2)

OMIT

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

NO_TEST

RFBD<113>
RFBD<114>
RFBD<112>
RFBD<115>
RFBD<117>
RFBD<116>
RFBD<118>
RFBD<119>
RFBD<97>
RFBD<96>
RFBD<99>
RFBD<98>
RFBD<100>
RFBD<101>
RFBD<102>
RFBD<103>
RFBD<121>
RFBD<120>
RFBD<122>
RFBD<123>
RFBD<126>
RFBD<124>
RFBD<125>
RFBD<127>
RFBD<104>
RFBD<105>
RFBD<106>
RFBD<107>
RFBD<108>
RFBD<110>
RFBD<109>
RFBD<111>

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

FBBA<12> 52
TP_U5501_RFU2

55
NO_TEST

10%
50V
CERM
402

GPU128BIT

1 C5502
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5503
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5531
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5504
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5505
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5532
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5506
0.1UF
2

20%
10V
CERM
402

GPU128BIT

GPU128BIT

1 C5507
0.1UF
2

1 C5533
0.001UF

20%
10V
CERM
402

10%
50V
CERM
402

EVENLY PLACE 0.1UF CAP & 0.01 UF CAPS

GPU128BIT

20%
10V
CERM
402

GPU DDR SDRAM B


SGRBVREF

1
R5501
1K
1%
1/16W
MF

2 402

CRITICAL

55 52

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

1 C5516
0.1UF

GPU128BIT

REFERENCE DES

55 52

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

PP2V5_GPU

1GPU128BIT
R5500
1K

DESCRIPTION

55 52

SDRAM_DDR_4MX32
BGA

FBBA<0>
FBBA<1>
FBBA<2>
FBBA<3>
FBBA<4>
FBBA<5>
FBBA<6>
FBBA<7>
FBBA<8>
FBBA<9>
FBBA<10>
FBBA<11>

PP2V5_GPU

1 C5530
0.001UF

55 54 52 50 7

QTY

55 52

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

GPU128BIT

SGRAM0 & SGRAM1 MEMORY SUPPORT

55 52

55 52

53

FBBA<12> 52
TP_U5500_RFU2

55 52

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

1 C5529
0.001UF
2

U5501
55 52

53

DDR SDRAM B VREF

PART NUMBER

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

55 52

55 54 52 50 7

GPU128BIT

(2 OF 2)

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

PP2V5_GPU

1 C5513
0.1UF

20%
10V
CERM
402

(1 OF 2)

CK
CK
CKE
CS
RAS
CAS
WE

GPU128BIT

1 C5512
0.1UF

SDRAM_DDR_4MX32
BGA

DQS0
DQS1
DQS2
DQS3

B3
H12
H3
B12

FBBCLK0
FBBCLK0_L
FBBCKE
FBBCS0_L
FBBRAS_L
FBBCAS_L
FBBWE_L

53 52

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

FBDQM<8>
FBDQM<11>
FBDQM<9>
FBDQM<10>

55 52

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

B2
H13
H2
B13

55 54 52 50 7

GPU128BIT

D7
D8
E4
E11
L4
L7
L8
L11

U5500
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

FBBA<0>
FBBA<1>
FBBA<2>
FBBA<3>
FBBA<4>
FBBA<5>
FBBA<6>
FBBA<7>
FBBA<8>
FBBA<9>
FBBA<10>
FBBA<11>

55 52

55 52

10%
50V
CERM
402

GPU128BIT

C5501
1 10UF
20%
6.3V
2 CERM
805

PP2V5_GPU

SDRAM_DDR_4MX32
BGA

GPU128BIT

C5514

D
55 54 52 50 7

1 C5526
0.001UF

GPU128BIT

1 10UF
20%
6.3V
2 CERM
805

PP2V5_GPU

U5500

55

GPU128BIT

1 C5517
0.1UF
2

55

VOLTAGE=1.25V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20%
10V
CERM
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

BOM OPTION

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

333S0251

SDRAM,4MX32,DDR,300MHZ

U5500,U5501

CRITICAL

GPU128BIT_SAMSUNG

333S0252

SDRAM,4MX32,DDR,300MHZ

U5500,U5501

CRITICAL

GPU128BIT_HYNIX

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

55

103

=PP3V3_AGP

PART NUMBER
NOSTUFF

2
R5616
10K
1

D
57

5%
1/16W
MF
402

1
R5638
10K

2 OMIT
R5625
10K

2
R5626
10K

2 OMIT
R5624
10K

2 OMIT
R5623
10K

1%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

1
57

VIPHCTL
57

VIPD7

57

NOSTUFF

57

2
R5617
1K
1

57

2
R5618
1K

5%
1/16W
MF
402

57 51

5%
1/16W
MF
402

57 51

OMIT

2
R5643
10K

R5644
10K
5%
1/16W
1 MF
402

2 NOSTUFF
R5629
1K

5%
1/16W
MF
402

5%
1/16W
MF
402

2 OMIT
R5628
1K

2 OMIT
R5627
1K

5%
1/16W
MF
402

5%
1/16W
MF
402

OMIT

2 NOSTUFF
R5648
1K

R5647
1K
5%
1/16W
1 MF
402

REFERENCE DES

CRITICAL

BOM OPTION

116S1104

RES,10K-OHM,1/16W,5%

R5625,R5623

270MHZ_SAM_18

116S1104

RES,10K-OHM,1/16W,5%

R5644

270MHZ_SAM_18

116S1103

RES,1K-OHM,1/16W,5%

R5628

270MHZ_SAM_18

116S1104

RES,10K-OHM,1/16W,5%

R5625,R5644

270MHZ_HYN_18

116S1103

RES,1K-OHM,1/16W,5%

R5628,R5627

270MHZ_HYN_18

111101 = 270MHZ SAMSUNG (NV34)

5%
1/16W
MF
402

[0] = [VIPD7]

DESCRIPTION

110011 = 270MHZ HYNIX (NV18B)

(6) AGP SIDEBAND

0 = PCI MODE

QTY

110111 = 270MHZ SAMSUNG (NV18B)

5%
1/16W
MF
402

NV_HSYNC
NV_VSYNC
GPU_STRAP<3>
GPU_STRAP<2>
DVOD3
DVOD2

2 OMIT
R5630
1K
(5) HOST MODE
[0] = [VIPHCTL]

(8) FRAME BUFFER MEMORY SPEED


[5..0] = [NV11_HSYNC,NV11_VSYNC,GPU_STRAP<3>,GPU_STRAP<2>,DVOD3,DVOD2]

=PP3V3_AGP

=PP3V3_AGP

116S1104

RES,10K-OHM,1/16W,5%

R5625,R5624

116S1104

RES,10K-OHM,1/16W,5%

R5623

270MHZ_SAM_34
270MHZ_SAM_34

116S1103

RES,1K-OHM,1/16W,5%

R5647

270MHZ_SAM_34

0 = ENABLE AGP SIDEBAND

1 = AGP MODE
1 = DISABLE AGP SIDEBAND

111100 = 270MHZ HYNIX (NV34)

116S1104

RES,10K-OHM,1/16W,5%

R5624,R5623

270MHZ_HYN_34

116S1103

RES,1K-OHM,1/16W,5%

R5630,R5647

270MHZ_HYN_34

=PP3V3_AGP
=PP3V3_AGP

=PP3V3_AGP
=PP3V3_AGP 7

2
R5663
10K
1%
1/16W
MF

1 402

NOSTUFF

2
R5664
10K
1%
1/16W
MF

52

57 51

2
R5633
10K

1%
1/16W
MF

1402

ROMA15
ROMA14

52

2
R5631
10K

5%
1/16W
MF

1402

48 49 50 51 52 56 57 58 59

NOSTUFF

2
R5653
10K

5%
1/16W
MF

1 402
57

DVOD8

1 402

GPU_STRAP<1>

57

GPU_STRAP<0>
NOSTUFF

NOSTUFF

NOSTUFF

2
R5665
1K

2
R5666
1K

5%
1/16W
MF
402

5%
1/16W
MF
402

2
R5632
1K

2
R5658
1K
1

5%
1/16W
MF

5%
1/16W
MF
402

5%
1/16W
MF

1 402

FAST WRITE SUPPORT


0=ENABLE
1=DISABLE

(1) ROM TYPE (OVERRIDDEN IF STRAP1 = 0)

2
R5634
1K
1 402

(9) SUB-VENDOR

(10) PCI ADDRESS BUS

[0] = [GPU_STRAP<1>]

[1..0] = [ROMA15,ROMA14]

[0] = [GPU_STRAP<0>]

0 = SYSTEM BIOS (VENDOR & SUBSYSTEM ID=0X0000)

0 = REVERSED

1 = ADAPTER CARD VGA BIOS (VENDOR & SUBSYSTEM ID=0X54-0X57)

1 = NORMAL

00 = PARALLEL
01 = SERIAL AT25F
10 = SERIAL SST45VF

11 = SERIAL FUTURE

=PP3V3_AGP
=PP3V3_AGP

=PP3V3_AGP

NOSTUFF
NOSTUFF

2
R5667
10K

1
R5635
10K

5%
1/16W
MF

1 402

1%
1/16W
MF

57

57

VIPD6
VIPD2

57
57

NOSTUFF

NOSTUFF

TMDS_XMIT_SI

NOSTUFF

2
R5612
10K

2
R5613
10K

2
R5608
10K

2
R5609
10K

2
R5602
10K

1
R5636
10K

1%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

5%
1/16W
MF
402

1%
1/16W
MF
402

2 402
57

57

2
R5601
1K
5%
1/16W
MF

1 402

57 51
57
57

2
R5600
1K

2
R5615
1K

5%
1/16W
MF
402

5%
1/16W
MF
402

NOSTUFF

1
R5637
10K
1%
1/16W
MF

2 402

2
R5605
10K

5%
1/16W
MF

1 402

2
R5611
1K
5%
1/16W
MF

1 402

2
R5610
1K

59 57 6

ANALOG_HSYNC_L
ANALOG_VSYNC_L

5%
1/16W
MF

1 402

NOSTUFF
NOSTUFF

5%
1/16W
MF

1 402

2
R5603
1K

2
R5607
1K

5%
1/16W
MF

5%
1/16W
MF

1 402

1 402

5%
1/16W
MF

1402

DVOHSYNC
VIPD3
VIPD5
VIPD4

2
R5604
1K

NOSTUFF

2
R5620
10K

1 402

TMDS_XMIT_GPU

2
R5614
1K

NOSTUFF

2
R5619
10K
5%
1/16W
MF

5%
1/16W
MF
402

59 57 6

VIPHAD1
VIPHAD0
VIPD1
VIPD0

57

NOSTUFF

=PP3V3_AGP

NOSTUFF

NOSTUFF

2
R5622
1K

2
R5621
1K

5%
1/16W
MF

2
R5606
1K

1 402

5%
1/16W
MF

1 402

5%
1/16W
MF

1 402

NVIDIA STRAPS

(7) TV MODE

(2) CRYSTAL FREQUENCY SELECT


[1..0] = [VIPD6,VIPD2]

[1..0] = [ANALOG_HSYNC*,ANALOG_VSYNC*]

(4) USER DEFINED STRAPS


[3..0] = [VIPHAD1,VIPHAD0,VIPD1,VIPD0]

00 = 13.5MHZ

00 = SECAM

(3) PCI DEVICE ID


[3..0] = [DVOHSYNC,VIPD3,VIPD5,VIPD4]

NOTICE OF PROPRIETARY PROPERTY

01 = NTSC
10 = PAL

01 = 14.38MHZ

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

0010 = 0X112 GEFORCE2 GO


11 = DISABLED

10 = 27MHZ
11 = {UNDEFINED}

THESE BITS ARE UNDEFINED BUT THEY

0011 = 0X113 QUADRO2 GO

MUST BE KEPT LOW DURING RESET

(THESE RESISTORS ARE ALL NOSTUFF)

0100 = 0X114 NV17M

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

0000 = 0X110 GEFORCE2GO MX (NV11B)

* 1001

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

= 0X111 NV18B,NV31,NV34

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

56

103

U4900
59
59

59

L5702
=PP3V3_AGP 1000-OHM-EMI

59 58 57 56 52 51 50 49 48 7

59

6
56

1 C5704
0.1UF

C5710
4.7UF

20%
6.3V
CERM
805

R5710
MF

59 58 57 56 52 51 50 49 48 7

=PP3V3_AGP

I2CA_SCL
I2CA_SDA

1C5702
0.1UF

C5711
20%
6.3V
CERM
805

56

10%
50V
CERM
402

56

1/16W

5%

M5
M4

VIPHAD0
VIPHAD1

P3
P2

AK7

PP3V3_NV_PLL

5%
50V
CERM
402

2
2

1%
1/16W
MF
402

5%
50V
CERM
402

NOSTUFF
C5708 1
27PF
5%
50V
CERM
402

R5704
75

1%
1/16W
MF
402

1
R5703
75

2
2

NOSTUFF
1

NOSTUFF
1

R5730
75

VIPHAD0
VIPHAD1

TESTPOINT

VIPVDDQ0
VIPVDDQ1
VIPVDDQ2

L6
L7
M7

VIPCAL_PD_VDDQ
VIPCAL_PU_GND

P6
P7

TESTPOINT

TESTPOINT

PLLVDD

5%
1/16W
MF

56

2 402

56
56

=PP3V3_AGP 7

56

56

1C5706
0.1UF

56

20%
10V
CERM
402

2
NOSTUFF

R5723
VIPCAL_PD_VDDQ
VIPCAL_PU_GND

1
1

49.9

49.9

402

20%
10V
CERM
402

AE3
AF3

VSYNC_L
HSYNC_L

10%
50V
CERM
402

PP3V3_NV_DACB

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

(GND)

DAC2RSET
DAC2VREF

R5729

NOSTUFF
1

75

1%
1/16W
MF
402

1%
1/16W
MF
402

C5716
0.1UF

1%
1/16W
MF
402

20%
10V
CERM
402

NV34

DVOVREF
51 DVODE
DVOCLKOUT
TP_DVOCLKOUT_L
DVOCLKIN
DVOHSYNC
DVOVSYNC

1 C5703
0.01UF

1%
1/16W
MF
402

10%
50V
X7R
603

51

51

1
R5711
10K

PLACE CLOSE TO VGA CONNECTOR

NV34
1

R5740
130

1%
1/16W
MF
2 402

NV18B
R5708
95.3

1%
1/16W
MF
402

NV34

NV18B1
R5700

5%
1/16W
MF
402

51
51
56 51

R5741
124

121
1%
1/16W
MF
402

56 51

1%
1/16W
MF
2 402

51
51

CVBS_D
D

51 50 49 48 7
59 58 57 56 52

51

=PP3V3_AGP

51

CRITICAL
56 51

Q5700
56
IRLML2502
48 7
52 51 50 49
SOT23
59 58 57

G
S

R5720
1K
5%
1/16W
MF
402

TESTPOINT
TESTPOINT

DACA_VSYNC
DACA_HSYNC

AB4
AC4

DACB_VDD
DACB_IDUMP

DACA_VDD
DACA_IDUMP

AD1
AD2
AE2

DACB_BLUE
DACB_GREEN
DACB_RED

DACA_BLUE
DACA_GREEN
DACA_RED

AD3
AB5

DACB_RSET
DACB_VREF

AJ8
AH9

NV_VSYNC
NV_HSYNC

NOSTUFF
56

56

AG9
AG10

(GND)

AJ9
AJ10
AK10

DACA_BLUE
DACA_GREEN
DACA_RED

PP3V3_NV_DACA

DACA_RSET AG8
DACA_VREF AH8

=PP3V3_AGP

1
R5707
10K
5%
1/16W
MF
402

51

NOSTUFF
R5721

51

49.9

51

DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11

1%
1/16W
MF
402

AF4
AE4
AJ2
AK2
AG1
AD5
AD6

AG2
AH1
AG3
AJ1
AH2
AK1
AJ3
AK3
AH4
AK4
AJ4
AH5
AE8
AD8
AD9

DVOVREF
DVODE TESTPOINT
DVOCLKOUT TESTPOINT
DVOCLKOUT* TESTPOINT
DVOCLKIN
DVOHSYNC
DVOVSYNC TESTPOINT

NC_DACC_BLUE
NC_DACC_GREEN
NC_DACC_RED

W7
Y7
AA6

=PP3V3_AGP 7

48 49 50 51 52 56 57 58 59

DVOD0 STRAPS
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11

XTALSSIN

1 C5720
0.1UF

C5712

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

20%
6.3V
CERM
805

NOSTUFF

1 C5721
0.001UF

20%
10V
CERM
402

10%
50V
CERM
402

5%
1/16W
MF
402

DACRSET1
DACVREF1
NOSTUFF
1

NC

NC

C5717
20%
10V
CERM
402

R5725

NOSTUFF
1

R5733
75

121

0.1UF

NC

NC_DACC_RSET AC5

NOSTUFF

4.7UF

75

1%
1/16W
MF
402

DACB_VSYNC
DACB_HSYNC

R5728

56 51

CVBS_CNT

48 49 50 51 52 56 57 58 59

56

R5724

PLACE CLOSE TO GPU

VIPHCLK
VIPHCTL

TESTPOINT

1
R5735
10K
56

1 C5701
0.001UF

1%
1/16W
MF
402

58

VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

NOSTUFF

NOSTUFF
C5709 1
27PF

J3
J2
K2
K1
L3
L2
N2
N1

TESTPOINT
TESTPOINT

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=3.3V

5%
402
1/16W

10

TP_VIPHCLK
VIPHCTL

ANALOG_BLU
ANALOG_GRN
ANALOG_RED

1
R5702
75

VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

OMIT

ROUTE THE RGB LINES


AS 37.5 OHM TRACES.

NOSTUFF
C5707 1
27PF

VIPCLK

R5727

4.7UF

59 6

AG5
AF7

L4

MON_I2C_SCL
MON_I2C_SDA

VIPPCLK

BGA

(2 OF 5)

2
SM

59 6

I2CC_SCL
I2CC_SDA

L5700
1000-OHM-EMI
1

59 6

R5709
10

MF

ANALOG_HSYNC_L

1 C5705
0.001UF

20%
10V
CERM
402

ANALOG_VSYNC_L

59 56 6

AG6
AG7

2
SM

59 56 6

NV18B

GRAPH_DDC_SCL
GRAPH_DDC_SDA

1%
1/16W
MF
402

NOSTUFF
1

R5732
75

1%
1/16W
MF
402

R5731
75

1%
1/16W
MF
402

1%
1/16W
MF
402

NC

AJ7

GPU_XTALSSIN
1

XTALIN

AJ6

R5726
10K

GPU_CLK27M_XIN

5%
1/16W
MF
402

PROPAGATION_DELAY=L:S::16 MM

XTALOUT

AH6

GPU_CLK27M_XOUT
PROPAGATION_DELAY=L:S::16 MM

DVOVDD

XTALOUTBUFF

AJ5

TP_GPU_XTALOUTBUFF

2
VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

DVOCAL_PD_VDDQ
DVOCAL_PU_GND
C5718
0.1UF

AB6
AB7

20%
10V
CERM
402
1

TP_BUF_RST
TESTPOINT

B1

STRAP0
STRAP1
NC_STRAP2
NC_STRAP3

DVOCAL_PD_VDDQ
DVOCAL_PU_GND
BUFRST*

G1
G2
F2
F3

GPU_STRAP<0>
GPU_STRAP<1>
GPU_STRAP<2>
GPU_STRAP<3>

56
56
56
56

NOSTUFF
R5722

R5706
5.1M

49.9

C5713

0.01UF
20%
16V
CERM
402

1
R5701
10K
5%
1/16W
MF
402

1 R5734
10K

5%
1/16W
MF
603

1%
1/16W
MF
402

NOTE: KEEP STUB SHORT ->

Y5700
SM-3

5%
1/16W
MF
402

27.000M
CRITICAL
1 C5719
27PF
2

5%
50V
CERM
402

1 C5700
27PF
2

5%
50V
CERM
402

DAC & CLOCKS

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

57

103

59 58 57 56 52 51 50 49 48 7

5
=PP3V3_AGP

59 58 57 56 52 51 50 49 48 7

=PP3V3_AGP

59 58 57 56 52 51 50 49 48 7

C5850

1
R5805
10K

1
R5804
10K

1%
1/16W
MF
402

1%
1/16W
MF
402

0.1UF

U4900
NV18B

59

LCD_PWM

[OUT]

47

LCD_PWM_U5850

5%
1/16W
MF
402

59

5
1

1
R5806
10K

PCI_RESET_L

LAMP_STS

[IN]

47 1

MON_DETECT

[IN]

47

R5802

R5820

NV_GPIOD0

G5

MON_DETECT_R

F4

59 6

U5850 2

G4

NV_GPIOD2

H5

NV_GPIOD3

1%
1/16W
MF

57

CVBS_CNT

59

INV_CUR_HI

R5860 1R5861
100K

5%
1/16W
MF
2 402

C5851
0.1UF

100K

5%
1/16W
MF
2 402

59

TMDS_EN

[OUT]

47 1

GPIOD2

R5809

NV_GPIOD4

H4

GPIOD4

R5830

NV_GPIOD5

J4

GPIOD5

47 1

R5808

NV_GPIOD6

J5

GPIOD6

IFPATXC
IFPATXC*

OMIT

20%
2 10V
CERM
402

10K 1

402

10K 1

402

[OUT]

10K 1

R5817

R5816
R5815

NV_GPIOD7

J6

NV_GPIOD8

K4
K6

NV_GPIOD9

U5851 2

MC74VHC1G08 3
SOT23-5

59 58 57 56 52 51 50 49 48 7

TP_GPU_THERMC

H3

TP_GPU_THERMA

H2

402

R5833

GPU_TMDS_CKP
GPU_TMDS_CKM

10K 1
10K 1

402

10K 1

GPU_SWAP_A
GPU_SWAP_B

R5812

TP_GPU_STEREO
GPU_TESTMECLK

Y5
G24

TP_FRWR_PME_L

AF10
N6
M6
L5
N5

PPVCORE_GPU

=PP3V3_AGP

59 58 57 56 52 51 50 49 48 7

AF9
AD4

R5846 NV34

2
2

GPIOD7
GPIOD8
GPIOD9
THERMDTHERMD+

TP_FRWRLNKON
TP_FRWRLPS

0 MF 5%

R5835

U4
T4

IFPATXD1
IFPATXD1*

Y2
AA1

IFPATXD2
IFPATXD2*

V3
W3

IFPATXD3
IFPATXD3*

U5
V4

TP_TMDS_TXD3P
TP_TMDS_TXD3M

IFPBTXC
IFPBTXC*

AA2
Y3

TP_EXT_TMDS_CKP
TP_EXT_TMDS_CKM

58
58

58
58

58
58

GPU_TMDS_D0P
GPU_TMDS_D0M

2
1

0 MF

SI_SDA
5%
2 R5832 SI_SCL

0 MF 5%

R5840

0
1

TMDS_XMIT_GPU

0
1

TMDS_XMIT_GPU

R5839

0
1

51

NOSTUFF

51 59

2 TMDS_CKM

51 59

402
1/16W
MF
5%

TMDS_D0P
2 TMDS_D0M

51 59
51 59

402

TMDS_D1P
2 TMDS_D1M

1/16W
MF
5%

51 59
51 59

402
1/16W
MF
5%

TMDS_D2P
2 TMDS_D2M

51 59
51 59

402

WHAT IS THE FREQUENCY OF THE Q27 PIXEL CLOCK?


BETH: 96.21MHZ

IFPBTXD6
IFPBTXD6*

Y6
W6

TP_EXT_TMDS_D2P
TP_EXT_TMDS_D2M

IFPBTXD7
IFPBTXD7*

AC3
AC2

TP_TMDS_TXD7P
TP_TMDS_TXD7M

IFPCTXC
IFPCTXC*

P5
P4

TP_DFPCLK
TP_DFPCLK_L

IFPCTXD0
IFPCTXD0*

R3
T2

TP_DFPD0
TP_DFPD1

IFPCTXD1
IFPCTXD1*

U2
T3

TP_DFPD2
TP_DFPD3

IFPCTXD2
IFPCTXD2*

U3
V2

TP_DFPD5
TP_DFPD6

IFPCVPROBE

AA3

=PP3V3_AGP

TMDS_XMIT_GPU

R5836

0 MF 5%

1/16W

IFPBTXD5
IFPBTXD5*

20%
10V
CERM
402

0 MF 5%

51

TP_EXT_TMDS_D1P
TP_EXT_TMDS_D1M

C5810

1/16W 402

AB3
AB2

NC_FRWR_PME*
NC_FRWR_VAUXC
NC_FRWR_VAUXP
NC_FRWRLNKON
NC_FRWRLPS

0 MF 5%

TMDS_CKP

TMDS_XMIT_GPU

R5834

1/16W 402

R5838

GPU_TMDS_D2P
GPU_TMDS_D2M

TP_EXT_TMDS_D0P
TP_EXT_TMDS_D0M

STEREO
TESTMEMCLK

1/16W 402

R5837

GPU_TMDS_D1P
GPU_TMDS_D1M

W4
V5

SWAPRDY_A
SWAPRDY_B

MF 5%

1/16W 402

IFPBTXD4
IFPBTXD4*

FPBCLKOUT
FPBCLKOUT*

0.1UF
2

TMDS_XMIT_GPU

NV34
R5845

C
50 49

M3
M2

TP_GPU_FPBCLKOUT
TP_GPU_FPBCLKOUT_L

=PP3V3_AGP

402

59 58 57 56 52 51 50 49 48 7

58

TMDS_XMIT_GPU

FPD_PWR_ON

58

IFPATXD0
IFPATXD0*

5
59

W2
V1

TMDS_XMIT_GPU

402
402

R5831
1/16W 402

TMDS_XMIT_GPU

402

[IN]

NOSTUFF

1/16W 402

GPIOD3

5%
1/16W
MF

2 402

GRAPH_IIC_SDA2
GRAPH_IIC_SCL2

402

=PP3V3_AGP

47 1

AF6
AE7

1
R5819
2K

5%
1/16W
MF
402

(5 OF 5)

402

2 402

GPIOD1

I2CB_SDA
I2CB_SCL

BGA

GPIOD0

402
6 8 51 74

MC74VHC1G08 3
SOT23-5

59 58 57 56 52 51 50 49 48 7

=PP3V3_AGP

1
R5818
2K

20%
10V
2 CERM
402

R5803

58

IFP0AVCC

NOSTUFF

Q5800

TP0610

59

FPD_PWR_SW_G

SM
1

G S

PP3V3_TMDSTERM
VOLTAGE=3.3V
MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
NOSTUFF

6
6

R5847

6
58

L5800

IFP0RSET

AA4
V6

IFPABVPROVE
IFPABRSET

IFPCRSET

R4

R5869
100

1%
1/16W
MF
402 2

6
6

58

GPU_TMDS_CKM

NOSTUFF

R5848
49.9

TP_IFP1VREF

NOSTUFF

R5849

6
58

IFP1RSET

49.9

GPU_TMDS_D0P

IFP0PLLVDD

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

IFP0AVCC

U10

IFPABPLLVDD

IFPCPLLVDD

P10

V10

IFPABPLLGND

IFPCPLLGND

N10

T5

IFPAIOVDD

IFPCIOVDD

R5

T6

IFPAIOGND

IFPCIOGND

R6

Y4

IFPBIOVDD

R5870
100

GPU_IFB1IOVDD

1%
1/16W
MF
402 2

GPU_IFP1PLLVDD

W5

IFPBIOGND
2

NOSTUFF
1 C5800
0.1UF
2

20%
10V
CERM
402

GPU_TMDS_D0M

NOSTUFF

R5850
49.9

R5800
10K
1%
1/16W
MF
402

1
R5801
10K

1%
1/16W
MF
402

NOSTUFF

R5821
1K

R5851

5%
1/16W
MF
402

58

49.9

GPU_TMDS_D1P

1%
1/16W
MF
402

C5811
4.7UF
20%
6.3V
CERM
805

1 C5801
0.1UF
2

20%
10V
CERM
402

1 C5805
0.001UF
2

10%
50V
CERM
402

1 C5803
4.7UF

1 C5802
0.1UF

1 C5804
0.1UF

R5871

20%
6.3V
CERM
805

20%
10V
CERM
402

20%
10V
CERM
402

1%
1/16W
MF
402 2
58

GPU_TMDS_D1M

1%
1/16W
MF 402

100

OMIT
R5807
1K

1%
1/16W
MF 402

58

1%
1/16W
MF 402

SM

1%
1/16W
MF 402

1000-OHM-EMI
1

1%
1/16W
MF 402

MAKE TP AS SHORT AS POSSIBLE

IFP0VREF

49.9

GPU_TMDS_CKP

NOSTUFF

R5852
49.9

1%
1/16W
MF 402

NOSTUFF

R5853
58

GPU_TMDS_D2P

49.9

R5872
100

1%
1/16W
MF
402 2
58

NOSTUFF

R5854
49.9

GPU_TMDS_D2M

1%
1/16W
MF 402

1%
1/16W
MF
402

L5801
FERR-EMI-100-OHM
1

SM

DVI AND STRAPS


VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

IFP0AVCC

58

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

GPU TMDS SWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TABLE_5_ITEM

114S1003

RES,1K OHM,1%,1/16W,0402

R5807

17_INCH_LCD

114S1503

RES,1.5K OHM,1%,1/16W,0402

R5807

20_INCH_LCD

SIZE

TABLE_5_ITEM

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

58

103

1
NOSTUFF

D5900

EXTERNAL VGA CONNECTOR

=PP5V_AGP 7

BAV99DW

R5926

INTERNAL TMDS CONNECTOR

49 50 59

TMDS_D2M

58 51

SOT-363

5%
MF
1/16W 402

SDF5900

STDOFF-118OD-181H-TH
57 56 6

ANALOG_HSYNC_L

5%
50V
CERM
402

NOSTUFF

L5902

R5904
301

CRITICAL

(516S0241)

53307-3072

BAV99DW

F-ST-SM
1

10

58 51

TMDS_D2P

58 51

TMDS_D1M

SYM_VER-1

TD2M

6 59

TD2P

6 59

SM

1%
1/16W
MF
2 402

J5902

D5900
SOT-363

90-OHM

1 C5907
22PF

0
2

2
NOSTUFF

R5927

5%
0
2

MF
1/16W 402

57 56 6

ANALOG_VSYNC_L

GND_CHASSIS_VGA

7 59

CRITICAL

5%
50V
CERM
402

TD0M
TD0P

59 6
59 6

(514-0201)
TD2M
TD2P

59 6
59 6

FL1702

J5903

LCFILTER

DV01793

SM-100MHZ

F-ST-TH
15

ANALOG_RED 1

57 6

TMDS_DDC_DAT

59 6

2
16

L5903
FERR-220-OHM

3 4
CHECK RGB RETURN PINS

1
2

LCFILTER

(RED_RTN)

(GRN_RTN)

10 6

11

12

DDC_VCC_5
VGA_IIC_DAT

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

1 C5905
0.01UF

1 C5902
0.01UF

1 C5904
0.01UF

10%
16V
CERM
402

57 6

1 C5903
0.01UF

10%
16V
CERM
402

5%
1/16W
MF
402

5%
1/16W
MF
402

ROUTE THE ANALOG RGB TRACES AT 37.5 OHMS.

R5908
33

58 57 56 52 51 50 49 48 7

MON_I2C_SCL

5%
50V
CERM
402

5%
50V
CERM
402

5%
1/16W
MF

L5901
FERR-220-OHM

TMDS_CKM

R5950

5%
1/8W
FF
1206

5%
1/8W
FF
1206

TSOP

R5900
33

TMDS_DDC_CLK

PP3V3_RUN

17_INCH_LCD

58

PP12V_RUN
59 50 7

R5935

R5934

2 3

CRITICAL

59 50 7

=PP12V_AGP

42375
M-ST-TH

0805

L5905

5%
1/8W
FF
2 1206

FPD_PWR_SW_S
VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C5918

C5919

100K

OMIT

0805

10K

5%
1/16W
MF
402

5%
1/16W
MF
402

1N914
SOT23
3

R5915
100K
5%
1/16W
MF
402

1
C5917 R5960
10K

10UF

100K

OMIT

59 58

518-0135

17_INCH_LCD

2
0805

L5911

17_INCH_LCD

Q5902
SM

58

LAMP_STS

2
0805

L5912
2

C5920

17_INCH_LCD

FERR-220-OHM

17_INCH_LCD

FERR-220-OHM
59 58

20%
10V
2 CERM
402

INV_CUR_HI

2
0805

17_INCH_LCD
17_INCH_LCD
1

R5912
330

5%
1/16W
MF
2 603

C5921

17_INCH_LCD
1

10UF

10UF

20%
16V
ELEC
SM

20%
16V
ELEC
SM

C5922

C5910

17_INCH_LCD
1

0.01UF
2

20%
50V
CERM
603

C5913

20%
50V
CERM
603

58

5%
1/16W
MF
402

L5913

GREEN
2.0X1.25A
2

SILKSCREEN: 3

TMDS_EN
3

L5914

DZ5900

0805

59 58

GND_20_INV

INV_20_LCD_PWM_
INV_20_CUR_HI_F

RES,100K OHM,1/16W,5%,0402

R5913

L5916

17_INCH_LCD
59 58
TABLE_5_ITEM

RES,330 OHM,1/16W,5%,0603

R5912

17_INCH_LCD

RES,1.2K OHM,1/16W,5%,0603

R5912

20_INCH_LCD

20%
50V
CERM
603

1UF

NOTE:REMOVED 2 PINS:LAMP_STATUS &


ON/OFF FOR 20" LCD INVETER.

20_INCH_LCD

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

20%
50V
CERM 2
1210

20_INCH_LCD

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

20_INCH_LCD

C5942

20_INCH_LCD

1UF

20%
50V
2 CERM
1210

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

0805

NOSTUFF

TABLE_5_ITEM

Q5900

INV_CUR_HI

C5947 1
TABLE_5_ITEM

XSTR,MOSFET,P-CH,0.02OHM

C5915
0.01UF

FERR-220-OHM

20_INCH_LCD

113S1123

20%
50V
CERM
603

518-0141

0805

BOM OPTION

113S1332

376S0225

EXT VGA / TMDS


AND INVERTER

TABLE_5_ITEM

116S1105

5%
25V
CERM
603

20_INCH_LCD

LCD_PWM

TABLE_5_ITEM

R5913

17_INCH_LCD
1

0.01UF

VOLTAGE=0V
MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

L5915

PP24V_INV

20_INCH_LCD

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

C5914

53048
6

VOLTAGE=24V
MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

FERR-220-OHM

1N5227B

RES,10K OHM,1/16W,5%,0402

20%
50V
CERM
603

17_INCH_LCD
1

220PF

RT-S-TH

2
0805

20_INCH_LCD

DESCRIPTION

C5912

J5901
20_INCH_LCD

FERR-220-OHM

=PP24V_GRAPHICS

FERR-220-OHM

17_INCH_LCD
1

0.01UF

GND_CHASSIS_17_INCH_INVERTER

QTY

C5911

CRITICAL

LED5900

R5914
10K

A
PART#

17_INCH_LCD
1

0.01UF

20_INCH_LCD

SOT23

116S1104

L5907

LCD_PWM

17_INCH_LCD

0.1UF

5%
1/16W
MF
2 402

FERR-220-OHM

2N7002

R5916

0805

MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

5%
1/16W
MF
2 402

10%
16V
2 CERM
1210

PP5V_AGP_P_SEQ

10K

LED5900_P1

R5921

1N914
SOT23

FERR-220-OHM

Q5902_DRAIN

17_INCH_LCD

Q5901
SM

FPD_PWR_ON_D
TMDS_EN_R

2N7002

FPD_PWR_ON

D5914

17_INCH_LCD

17_INCH_LCD
6 59

PP12V_INV
GND_17_INV
PP5V_AGP_RL
INV_17_LCD_PWM_F
LAMP_STS_F
INV_17_CUR_HI_F

NOSTUFF

Q5902_GATE
PPVCC_TMDS

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

10%
50V
CERM

R5913

VOLTAGE=0V
MIN_LINE_WIDTH=100MIL
VOLTAGE=5V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

20%
16V
CERM
402

R5925

0.0022UF
402

0.01UF
2

L5900
FERR-220-OHM

5%
1/8W
FF
2 1206

VOLTAGE=12V
MIN_LINE_WIDTH=100MIL
MIN_NECK_WIDTH=10MIL

17_INCH_LCD
2

L5906

D5901

5%
1/16W
MF
2 402

20_INCH_LCD

200K

J5900

17_INCH_LCD

0805

=PP12V_AGP

R5919

NOSTUFF
NOSTUFF

376S0082

6 59

FERR-220-OHM

5%
1/16W
MF
2 402

SO-8

TCKP

MF
2 1/16W 402

6 59

17_INCH_LCD

IRF7410
G

0 5%

17_INCH_LCD

5%
1/16W
MF
402

Q5900
4

FPD_PWR_SW_G

2
NOSTUFF

10%
16V
CERM
402

L5904

100K 2

6 59

6 59

R5920

0
7

TCKM

Q5903_GATE 3

1
5 6

SM

20" LCD INVERTER NEED +24V.


17" LCD INVERTER NEED +12V.

=PP5V_AGP

R5922

5%
1/8W
FF
2 1206

5%
MF
1/16W 402
SYM_VER-1

90-OHM

TMDS_CKP

58 51

SI3433DV

PPVCC_FPD

R5923

6 59

0
2

1%
1/16W
MF
2 402

FERR-220-OHM

20_INCH_LCD

TD0P

MF
2 1/16W 402

Q5903

7 59

PP12V_RUN

NOSTUFF

0 5%

R5931
1

6 59

PP3V3_DDC

17_INCH_LCD

58

58 51

4
17_INCH_LCD

2
NOSTUFF

INVERTER INTERFACE

PP3V3_ALL

TMDS_D0P

R5933

17_INCH_LCD

59 50 49 7

90 11 7

TMDS_DDC_DAT

5%
1/16W
MF
402

NOSTUFF

2
1 C5906
47PF

6 59

5%
1/16W
MF
402

C5909 1
47PF

GRAPH_DDC_SCL

57

TD0M

1 C5901
0.01UF

5%
1/16W
MF
402

SOT-363

5%
1/16W
MF
402

58 51

SM

1%
1/16W
MF
2 402

0805

R5909
33

R5902
301

R5901
301

2
R5907
2K
1 402

BAV99DW

R5906
33

1
R5905
2K

GND_CHASSIS_VGA

PP3V3_RUN

=PP3V3_AGP

NOSTUFF

5%
1/16W
MF
402

57

7 49 50 59

D5902
1

90-OHM

SYM_VER-1

NOSTUFF

7 59

5%
MF
1/16W 402

L5909

10%
16V
CERM
402

6 59

0
2

C5900
0.01UF

10%
16V
2 CERM
1210

GRAPH_DDC_SDA

MON_I2C_SDA

C5916

TD1P

NOSTUFF

6 59

7 49 50 59

57

=PP5V_AGP

SOT-363

1
R5910
2K

TMDS_D0M

GND_CHASSIS_VGA
BAV99DW

1
R5911
2K

58 51

6 59

MF
2 1/16W 402

R5932

D5902

MON_DETECT

TMDS_D1P

TD1M

R5930

10%
16V
CERM
402

VGA_IIC_CLK

=PP5V_AGP

58 51

SM

0 5%

R5929

6 59

L5910

57

3
NOSTUFF

6 59

7 59

3 4

58 6

TD1M
TD1P
TMDS_DDC_CLK

90-OHM

2 402

10%
16V
CERM
402

LCFILTER
SM-100MHZ

6 59

SDF5901

14

GND_CHASSIS_VGA

L5908

SYM_VER-1

1%
1/16W
MF

6 59

5%
MF
1/16W 402

R5903
301

TCKM
TCKP

0
2

6 59

STDOFF-118OD-181H-TH

(BLU_RTN)

18

ANALOG_BLU 1

PP3V3_DDC

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

GND_CHASSIS_TMDS

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

17

FL1700

12

R5928

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP5V_USB2 92
7 6

13

11

NOSTUFF

VOLTAGE=3.3V

0805
8

3 4

PPVCC_TMDS

10UF

SM-100MHZ

ANALOG_GRN 1

FILT_ANALOG_RED
FILT_ANALOG_GRN
FILT_ANALOG_BLU

FL1701

57 6

59 6

1 C5908
22PF
2

NOSTUFF

C5943

20_INCH_LCD

0.01UF
2

20%
50V
CERM
603

C5944

20_INCH_LCD

0.01UF
2

20%
50V
CERM
603

C5945

20_INCH_LCD

220PF
2

5%
25V
CERM
603

C5946

SIZE

0.01UF

20%
50V
CERM
603

APPLE COMPUTER INC.

DRAWING NUMBER

REV.

051-6482

SCALE

SHT

OF

TABLE_5_ITEM

RES,0 OHM,1/10W,5%,0805

L5900

17_INCH_LCD

NONE

101S1000

GND_CHASSIS_20_INCH_INVERTER

59

103

ELECTRICAL_CONSTRAINT_SET

R6000
C6013

C6012

=PP1V2_HT

64 62 60

20%
2 10V
CERM
402

64 62 60

HT_CLK
AVDD

64 62 60
64 62 60

64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60

64 60 7

64 62 60

=PP2V5_HT

64 62 60
64 62 60

R6005 R6004 R6003 R6002


1K

1K

5%
1/16W
MF
2 402

1K

5%
1/16W
MF
2 402

1K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

64 62 60
64 62 60

7 24 60

0.1UF

10%
2 6.3V
CERM
402

27

64 62 60

VDD_HT
2_5

HT_CLK66M_NB

H9 HT_CLK

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N

N1 HT_CLK_RXP0
P1 HT_CLK_RXN0

64 62 60

VDD_HT
1_2

64 62 60

U3

64 62 60

U3LITE
V1.0-300MM
PBGA
(SYM 5 OF 7)

HT
INTERFACE

L1 HT_CAD_RXP0
L2 HT_CAD_RXN0

HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

64 62 60

L9

1UF

64 62 60

N10

64 62 60
7 60 64

N2
N6

5%
1/16W
MF
603

=PP2V5_HT

PP1V5_PWRON_HT_NB_AVDD
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R9

2.2

T4
T8

J10
G6

=PP1V5_PWRON_NB_AVDD

F8

48 37 28 7

64 62 60

OMIT

64 62 60
64 62 60

HT_CLK_TXP0 R7
HT_CLK_TXN0 R8

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N

60 62 64

64 62 60

60 62 64

64 62 60
64 62 60

HT_CAD_TXP0 U8
HT_CAD_TXN0 U7

L3 HT_CAD_RXP1
L4 HT_CAD_RXN1
M4 HT_CAD_RXP2
M3 HT_CAD_RXN2

HT_CAD_TXP1 U6
HT_CAD_TXN1 U5
HT_CAD_TXP2 U4
HT_CAD_TXN2 U3

M2 HT_CAD_RXP3
M1 HT_CAD_RXN3
P2 HT_CAD_RXP4

HT_CAD_TXP3 R5
HT_CAD_TXN3 R6
HT_CAD_TXP4 P8

P3 HT_CAD_RXN4
R3 HT_CAD_RXP5
R2 HT_CAD_RXN5

HT_CAD_TXN4 P7
HT_CAD_TXP5 P6
HT_CAD_TXN5 P5

R1 HT_CAD_RXP6
T1 HT_CAD_RXN6
U1 HT_CAD_RXP7

HT_CAD_TXP6 M5
HT_CAD_TXN6 M6
HT_CAD_TXP7 M7

U2 HT_CAD_RXN7

HT_CAD_TXN7 M8

HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

64 62 60

HT_CTL_TXP0 L6
HT_CTL_TXN0 L5

V2 HT_CTL_RXP0
V1 HT_CTL_RXN0

HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N

HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60
64 62 60

64 62 60
64 62 60
64 62 60
64 62 60

F9 HT_PWROK
G9 HT_RESET*
H8 HT_LDTSTOP*

HT_PWROK
HT_RESET_L
HT_LDTSTOP_L
HT_LDTREQ_L

H7

64 62 60
64 62 60

HT_PVTREF0 L7
HT_PVTREF1 L8

HT_LDTREQ*

HT_NB_PVTREF0
HT_NB_PVTREF1

64 62 60
64 62 60

G8

HT_CLK_AVSS

NET_SPACING_TYPE

R6001

64 62 60

200

64 62 60

1%
1/16W
MF
2 402

64 62 60
64 62 60
64 62 60
64 62 60

HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB

HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB

HT_NB_TO_SB_CLK
HT_NB_TO_SB_CLK
HT_NB_TO_SB_CTL
HT_NB_TO_SB_CTL
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD2
HT_NB_TO_SB_CAD2
HT_NB_TO_SB_CAD3
HT_NB_TO_SB_CAD3
HT_NB_TO_SB_CAD4
HT_NB_TO_SB_CAD4
HT_NB_TO_SB_CAD5
HT_NB_TO_SB_CAD5
HT_NB_TO_SB_CAD6
HT_NB_TO_SB_CAD6
HT_NB_TO_SB_CAD7
HT_NB_TO_SB_CAD7

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N
HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N
HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB

HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB

HT_SB_TO_NB_CLK
HT_SB_TO_NB_CLK
HT_SB_TO_NB_CTL
HT_SB_TO_NB_CTL
HT_SB_TO_NB_CAD0
HT_SB_TO_NB_CAD0
HT_SB_TO_NB_CAD1
HT_SB_TO_NB_CAD1
HT_SB_TO_NB_CAD2
HT_SB_TO_NB_CAD2
HT_SB_TO_NB_CAD3
HT_SB_TO_NB_CAD3
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD5
HT_SB_TO_NB_CAD5
HT_SB_TO_NB_CAD6
HT_SB_TO_NB_CAD6
HT_SB_TO_NB_CAD7
HT_SB_TO_NB_CAD7

HT_PWROK
HT_RESET_L
HT_LDTSTOP_L
HT_LDTREQ_L

HT_PWROK
HT_CTL
HT_CTL
HT_CTL

HT_2V5
HT_2V5
HT_2V5
HT_2V5

HT_NB_TO_SB

64 60 7

60 24 7

C6010
0.1UF

20%
2 10V
CERM
402

C6011
0.1UF

20%
2 10V
CERM
402

I46
I47
I83
I82
I51
I50
I52

I53
I54
I55
I56
I57
I58
I59
I60
I61
I62
I63
I64
I65

I48
I49
I84
I85
I66
I67
I68
I69
I70
I71
I72
I73
I74

I75
I76
I77
I78
I79
I80
I81

I86
I87
I88
I89

HT_SB_TO_NB

HT_2V5

5 MIL SPACING FOR DIFF PAIR


10 MIL SPACING TO ANYTHING ELSE

=PP2V5_HT

DIFFERENTIAL_PAIR

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N
HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N
HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

60 62 64

64 62 60
64 62 60

4 MIL SPACING IN GROUP


8 MIL SPACING TO ANYTHING ELSE

=PP1V2_HT

C6000
0.1UF

20%
2 10V
CERM
402

C6001
0.1UF

20%
2 10V
CERM
402

C6002
0.1UF

20%
2 10V
CERM
402

C6004
0.1UF

20%
2 10V
CERM
402

C6005
0.1UF

20%
2 10V
CERM
402

C6006
0.1UF

20%
2 10V
CERM
402

C6007
0.1UF

20%
2 10V
CERM
402

C6008

LENGTH TOLERENCE CAN BE LOOSE


MATCHED GROUP CONSTRAINT IS TIGHT ENOUGH

0.1UF

20%
2 10V
CERM
402

MASTER: GILA
LAST MODIFIED: APR 12, 04

U3LITE HT
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

60

OF

C
103

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

DIFFERENTIAL_PAIR
HT_CLK66M_SB_C

15 MIL SPACING

62

Page Notes
Power aliases required by this page:
- _PP2V5_PWRON_HT
- _PP1V2_PWRON_HT

Signal aliases required by this page:


(NONE)

BOM options provided by this page:


- SB_HT_200M
Stuffs resistor to select 200MHz HT I/F.

=PP2V5_PWRON_HT

62 7

3.3

5%
1/10W
FF
805

C6200
10uF

20%
10V
2 CERM
402

C6201
1uF

20%
6.3V
2 CERM
1206

=PP1V2_PWRON_HT

10%
6.3V
2 CERM
402

C6230

0.1uF

C6210

C6231

0.1uF

7 62

C6232
0.1uF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C6211

=PP1V2_PWRON_HT

7 62

G11

B9

10%
6.3V
2 CERM
402

B12

1uF
B17
G13

20%
6.3V
2 CERM
1206

B15

10uF

B19

B6

5%
1/10W
FF
805

C7

3.3

20%
2 10V
CERM
402

PP1V2_PWRON_HT_PLLAVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

R6210

C6220
0.1uF

PP1V2_PWRON_HT_PLLDVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

R6200

=PP1V2_PWRON_HT

20%
10V
2 CERM
402

U2300

C6240
0.1uF

AVDD DVDD VDDP HT_RXVDD HT_TXVDD


HT_PLL
HT OMIT

C6241

0.1uF

C6242
0.1uF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

SHASTA
V1.0

64 60
64 60
64 60
64 60
64 60
64 60
64 60
64 60
64 60

64 60
64 60

64 60

C6255
0.1uF
27

HT_CLK66M_SB

R62551
332
1%
1/16W
MF
402 2

62 7

64 60
64 60

62

20%
10V
CERM
402

F13 HT_CTLIN_P
E13 HT_CTLIN_N

HT_CADOUT_4_P A11
HT_CADOUT_4_N B11
HT_CADOUT_5_P C12

C14 HT_CADIN_5_N
E14 HT_CADIN_6_P
F14 HT_CADIN_6_N

HT_CADOUT_5_N D12
HT_CADOUT_6_P E12
HT_CADOUT_6_N F12

B14 HT_CADIN_7_P
A14 HT_CADIN_7_N

HT_CADOUT_7_P A13
HT_CADOUT_7_N B13
HT_CTLOUT_P C13
HT_CTLOUT_N D13

E16 HT_PWROK_H
C18 HT_RESET_L
E17 HT_LDTSTOP_L

HT_PWROK
HT_RESET_L
HT_LDTSTOP_L

HT_LDTREQ_L

C8 HT_REFCLK
D8 HT_S100M66M
V6 SEL_HT00_H

HT_CLK66M_SB_C
SB_HT_S100M66M
SB_SELHT100

AC coupled
1.0V pk-pk

HT_PLL
AGND DGND
C6

HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N

B16 HT_CADIN_4_P
A16 HT_CADIN_4_N
D14 HT_CADIN_5_P

HT_CADOUT_2_N F11
HT_CADOUT_3_P D11
HT_CADOUT_3_N C11

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N

HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N

A19 HT_LDTREQ_L

HT_R100P E10
HT_R100N F10

SB_HT_R100_P
SB_HT_R100_N

HT_TXGND

60 64

C6250 1
47pF

5%
50V
CERM 2
402

60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64

60 64
60 64

60 64

R6250
1

HT_RXGND

60 64

HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

G10

64 60

HT_CADOUT_1_N A8
HT_CADOUT_2_P E11

A9

64 60

A18 HT_CADIN_1_N
F15 HT_CADIN_2_P
E15 HT_CADIN_2_N
D16 HT_CADIN_3_P
C16 HT_CADIN_3_N

HT_CADOUT_0_P D10
HT_CADOUT_0_N C10
HT_CADOUT_1_P B8

A12

64 60

D17 HT_CADIN_0_P
C17 HT_CADIN_0_N
B18 HT_CADIN_1_P

HYPERTRANSPORT

64 60

HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

G12

64 60
64 60

D15 HT_CLKIN_P
C15 HT_CLKIN_N

A17

64 60

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N

A15

64 60

A6

64 60

BGA
B10
(3 OF 8) HT_CLKOUT_P
HT_CLKOUT_N A10

82.5 2
1%
1/16W
MF
402

C6251
47pF

5%
50V
2 CERM
402

=PP1V2_PWRON_HT
NO STUFF

R62521

R62541

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

4.7K

10K

SB_HT_200M

R62531

R62511

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

4.7K

Master: Link

1K

Shasta HyperTransport

NOTICE OF PROPRIETARY PROPERTY


HT RefClk

HT I/F Speed

1 = 100MHz
0 = 66MHz

1 = 100MHz
0 = 200MHz

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

DRAWING

APPLE COMPUTER INC.

TITLE=FIZZY
ABBREV=DRAWING

DRAWING NUMBER

D
SCALE

LAST_MODIFIED=Wed Aug

SHT
NONE

4 17:58:18 2004

REV.

051-6482

OF

62

103

SAME CONNECTORS & PINOUT AS

Q37 HYPERTRANSPORT BETWEEN GOLEM AND K2

NOSTUFF

J6400
P6860

ST-SM-DF
SYM_VER1

NOSTUFF

NOSTUFF

J6401

J6402

P6860

P6860

ST-SM-DF

ST-SM-DF

SYM_VER1

SYM_VER1

NOSTUFF

R6400

A15

62 60

HT_NB_TO_SB_CLK_N

A14

CLK-

HT_NB_TO_SB_CLK_P

A13

GND

62 60

62 60

HT_NB_TO_SB_CAD_P<6>

A12

62 60

B12
D15

B11

GND

B10

CLK+

A11

GND

62 60

HT_NB_TO_SB_CAD_N<6>

A10

62 60

HT_NB_TO_SB_CAD_N<4>

A9

B9
D11

B8

GND

B7

D9

GND

62 60

HT_NB_TO_SB_CAD_P<4>

62 60

HT_NB_TO_SB_CAD_N<2>

A6

62 60

HT_NB_TO_SB_CAD_P<2>

D7

B5

GND

B4

D8

D5

A4

GND

B3
D3

B2

GND

B1

D4

62 60

HT_NB_TO_SB_CAD_N<0>

62 60

HT_NB_TO_SB_CAD_P<0>

60 62

HT_NB_TO_SB_CAD_P<5>

60 62

HT_SB_TO_NB_CAD_N<0>

A13

HT_SB_TO_NB_CAD_N<2>

A12

A3
D1

A1

GND

D15

B11

GND

B10

HT_SB_TO_NB_CAD_P<2>

HT_NB_TO_SB_CAD_P<3>

60 62

HT_NB_TO_SB_CAD_N<3>

60 62

HT_SB_TO_NB_CAD_P<4>

A11

D13

A10

GND

A9
A8

62 60

HT_SB_TO_NB_CAD_N<4>

D11

B8

GND

B7

62 60

HT_SB_TO_NB_CAD_P<6>

62 60

HT_SB_TO_NB_CAD_N<6>

A7

HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N

62 60

HT_SB_TO_NB_CLK_P

A6
D5

A4

GND

HT_SB_TO_NB_CAD_P<3>

60 62

HT_SB_TO_NB_CAD_N<3>

60 62

HT_SB_TO_NB_CAD_N<5>

60 62

D7

B5
B4

HT_SB_TO_NB_CAD_P<5>

60 62

B3

HT_SB_TO_NB_CAD_N<7>

60 62

D3

A3

TEK_HT_A10

D1

A1

GND

A14

CLK-

A13

GND

B12
B11

GND

B10

TEK_HT_B10

B9

HT_RESET_L

TEK_HT_A9

5%
1/10W
MF
603
62 60

HT_LDTSTOP_L

TEK_HT_A7

A11

D13

A10

GND
D11

B8

GND

B7

A9

A7

60 62

D0

HT_PWROK

D10

B6

GND
D7

B5

GND

B4

D8

A6

HT_LDTREQ_L

60 62

D6

A5

D5

A4

GND

A3

62 60

60 62

D9

B3
D3

B2

GND

B1

D4

HT_SB_TO_NB_CAD_P<7>

D14

A8

R6404

5%
1/10W
MF
603

TEK_HT_B12

D15

A12

D12

D2

A2

TEK_HT_A12

5%
1/10W
603

B2
B1

CLK+

R6403

D6

A5

A15

NOSTUFF

GND

GND

GND

62 60

60 62

NOSTUFF

B6

D4

62 60

HT_SB_TO_NB_CAD_N<1>

HT_SB_TO_NB_CLK_N

D10

60 62

D0

60 62

D9

D8

60 62

HT_SB_TO_NB_CAD_P<1>

D14

D12

D2

A2

B12

B9
62 60

HT_NB_TO_SB_CAD_N<1>

GND

CLK+

HT_NB_TO_SB_CAD_N<5>

HT_NB_TO_SB_CAD_P<1>

CLK-

62 60

D6

A5

62 60

A14
62 60

62 60

B6

A15

60 62

D10

A8
A7

HT_NB_TO_SB_CAD_P<7>

60 62

D14
D13

D12

HT_NB_TO_SB_CAD_N<7>

HT_SB_TO_NB_CAD_P<0>

HT_NB_TO_SB_CTL_N

60 62

HT_NB_TO_SB_CTL_P

60 62

D2

A2

D1

A1

GND

D0

=PP2V5_HT
DEVELOPMENT

7 60

R6401

10K

5%
1/16W
MF

2 402

HT_VREF_DEBUG
VOLTAGE=1.25V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

DEVELOPMENT

R6402

10K

5%
1/16W
MF

2 402

MASTER: GILA
LAST MODIFIED: APR 12, 04

HT DEBUG CONN
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

64

OF

C
103

ALL RESISTOR PACKS ARE 47 OHM 1/16W 5%

R PAKS ARE PIN SWAPPABLE ACROSS ALL SIGNALS (EXCEPT IDSELS)

74

PCI_SB_AD<0>
PCI_SB_AD<1>
PCI_SB_AD<2>
PCI_SB_AD<3>
PCI_SB_AD<4>
PCI_SB_AD<5>
PCI_SB_AD<6>
PCI_SB_AD<7>
PCI_SB_AD<8>
PCI_SB_AD<9>
PCI_SB_AD<10>
PCI_SB_AD<11>
PCI_SB_AD<12>
PCI_SB_AD<13>
PCI_SB_AD<14>
PCI_SB_AD<15>
PCI_SB_AD<16>

76 74

PCI_SB_AD<17>

74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74

RP7300
RP7303
RP7303
RP7303
RP7309
RP7300
RP7300
RP7309
RP7300
RP7301
RP7301
RP7301
RP7309
RP7309
RP7301
RP7307
RP7308

47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77

R7300
1

47

PCI_AD<17>

6 74 75 76 77

5%
1/16W
MF
402

74
74
74
74
74
74
74
74
74

PCI_SB_AD<18>
PCI_SB_AD<19>
PCI_SB_AD<20>
PCI_SB_AD<21>
PCI_SB_AD<22>
PCI_SB_AD<23>
PCI_SB_AD<24>
PCI_SB_AD<25>
PCI_SB_AD<26>

RP7307
RP7306
RP7305
RP7305
RP7302
RP7302
RP7304
RP7306
RP7305

47
47
47
47
47
47
47
47
47

PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 76 77
6 74 76 77
6 74 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77

R7301
77 74

PCI_SB_AD<27>

47

PCI_AD<27>

6 74 75 76 77

5%
1/16W
MF
402
74
74
74
74

74
74
74
74

74
74

74
74
74
74

PCI_SB_AD<28>
PCI_SB_AD<29>
PCI_SB_AD<30>
PCI_SB_AD<31>

RP7302
RP7304
RP7302
RP7304

PCI_SB_CBE_L<0>
PCI_SB_CBE_L<1>
PCI_SB_CBE_L<2>
PCI_SB_CBE_L<3>

RP7303
RP7306
RP7305
RP7304

PCI_SB_DEVSEL_L
PCI_SB_FRAME_L
PCI_SB_IRDY_L
PCI_SB_TRDY_L
PCI_SB_STOP_L
PCI_SB_PAR

RP7306
RP7307
RP7307
RP7308
RP7308
RP7308

47
47
47
47

PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

47
47
47
47

PCI_CBE_L<0>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_CBE_L<3>

47
47
47
47
47
47

PCI_DEVSEL_L
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_PAR

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77

6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77

6 74 76 77
6 74 76 77

6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77

PLACE CLOSE TO SHASTA

AD<17> IS IDSEL FOR AIRPORT


AD<27> IS IDSEL FOR USB

PCI SERIES TERMINATION

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6482

73

OF

C
103

8
ELECTRICAL_CONSTRAINT_SET

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR

PCI_AD
PCI_AD27
PCI_AD
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD
PCI_AD17
PCI_AD

PCI_AD<31..28>
PCI_AD<27>
PCI_AD<26..24>
PCI_AD<23>
PCI_AD<22>
PCI_AD<21>
PCI_AD<20>
PCI_AD<19..18>
PCI_AD<17>
PCI_AD<16..0>

PCI
PCI
PCI_CTL
PCI_CTL
PCI_CTL
PCI_CTL
PCI_CTL

PCI_CBE_L<3..0>
PCI_PAR
PCI_DEVSEL_L
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L

6 73 75 76 77
6 73 75 76 77
6 73 75 76 77
6 73 76 77
6 73 76 77
6 73 76 77
6 73 75 76 77
6 73 75 76 77
6 73 75 76 77
6 73 75 76 77

6 73 76 77
6 73 76 77
6 73 74 76 77
6 73 74 76 77
6 73 74 76 77
6 73 74 76 77
6 73 74 76 77

Page Notes
Power aliases required by this page:
- _PP3V3_PCI
- _PP3V3_SB_PCI (can be _PP3V3_PCI)
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB

=PP3V3_SB_PCI

Signal aliases required by this page:


(NONE)

BOM options provided by this page:


(NONE)

20%
2 6.3V
CERM
805

NO STUFF

C7410
10uF

0.1uF

C7402
0.1uF

C7403
0.1uF

20%
2 10V
CERM
402

C7404
0.1uF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

7 23 25 88

NO STUFF

C7405
0.1uF

20%
10V
2 CERM
402

C7406
0.1uF

20%
10V
2 CERM
402

C7407
0.1uF

20%
10V
2 CERM
402

C7408
0.1uF

C7409

C7420 1 C7421

0.1uF

20%
10V
2 CERM
402

0.1uF

20%
10V
CERM 2
402

20%
10V
2 CERM
402

VDDOPC

C7422

0.1uF

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

C7423

0.1uF

20%
10V
CERM 2
402

N20
U20

PCI1)
PCI0 or 2)
PCI0 or 2)
PCI0 or 2)
PCI0)

J18

20%
6.3V
2 CERM
805

B20

10uF

U21
V19

C7411

N21
R20

M16

(0x106B/0x004F,
(0x1166/0x0240,
(0x106B/0x0050,
(0x106B/0x0052,
(0x106B/0x0051,

C7401

20%
2 10V
CERM
402

H16
J21

KeyLargo
SATA 150
UATA 133
FireWire
Ethernet

E21

0.1uF

AA22
B22

AD23
AD28
AD29
AD30
AD31

C7400

20%
2 10V
CERM
402

=PP2V5_PWRON_SB

PCI Devices implemented on this page:


AD11 - PCI0
(0x106B/0x0053)
AD11 - PCI1
(0x106B/0x0054)
AD11 - PCI2
(0x106B/0x0055)

PCIVDDP

U2300

OMIT

SHASTA
V1.0
27

PCI_CLK66M_SB_INT

AB9 PCIBR_CLK_H

27 8

PCI_CLK33M_SB_EXT

U19 PCI1CLK_H

BGA
(4 OF 8)

PCI

=PP3V3_PCI 7

76 74 6

25 74 75 76 77

76 74 6

RP7400
4.7K
2

PCI_SLOTA_REQ_L

5%
1/16W
SM1

4.7K
1

PCI_SLOTG_REQ_L

"Slot G" - AD27


PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L

AB18

PCI1REQ_0_L

AA18

PCI1GNT_0_L

AB20
AB19

PCI1REQ_1_L
PCI1GNT_1_L

6 74 76

74

74 77

"Slot D" - AD20


PCI_SLOTD_REQ_L
PCI_SLOTD_GNT_L

4.7K

PCI_SLOTG_GNT_L

V17

PCI1REQ_2_L

V18

PCI1GNT_2_L

PCI_SLOTD_REQ_L

74 77

4.7K

PCI_SLOTD_GNT_L

PCI1AD_12_H M19
PCI1AD_13_H N19
PCI1AD_14_H P21
PCI1AD_15_H R22
PCI1AD_16_H P20
PCI1AD_17_H V21
PCI1AD_18_H P18
PCI1AD_19_H T20
PCI1AD_20_H R16

PCI1AD_23_H Y22
PCI1AD_24_H R18
PCI1AD_25_H T19

74

PCI1AD_26_H T18
PCI1AD_27_H Y21
PCI1AD_28_H W20

RP7401
4

PCI1AD_10_H M17
PCI1AD_11_H N18

PCI1AD_21_H R17
PCI1AD_22_H W21

5%
1/16W
SM1

RP7401

PCI1AD_4_H M18
PCI1AD_5_H L20
PCI1AD_6_H M21
PCI1AD_7_H N16
PCI1AD_8_H M20
PCI1AD_9_H P22

RP7400
3

5%
1/16W
SM1

PCI_SLOTA_GNT_L

74

5%
1/16W
SM1

4.7K

77 74

5%
1/16W
SM1

RP7400

77 74

RP7400

B
4.7K
4

6 74 76

"Slot A" - AD17


PCI_SLOTA_REQ_L
PCI_SLOTA_GNT_L

PCI1AD_0_H L18
PCI1AD_1_H K19
PCI1AD_2_H L22
PCI1AD_3_H M22

74

PCI1AD_29_H T16
PCI1AD_30_H AA21
PCI1AD_31_H T17

5%
1/16W
SM1

PCI1C_BE_0_L

L19

PCI1C_BE_1_L

P16
V22

PCI1C_BE_2_L
PCI1C_BE_3_L

76 75 6

76 75 6
76 75 6

AB8
AA9

ROM_CS_L
ROM_OE_L
ROM_WE_L

Y10

ROMCS_L
ROMOE_L
ROMRW_L

V20

PCI1DEVSEL_L

T22

PCI1FRAME_L
PCI1IRDY_L

T21
R21

PCI1TRDY_L

P19

PCI1STOP_L
PCI1PAR_H

P17
N17

PCI1RST_L

U18

PCI_SB_AD<0>
PCI_SB_AD<1>
PCI_SB_AD<2>
PCI_SB_AD<3>
PCI_SB_AD<4>
PCI_SB_AD<5>
PCI_SB_AD<6>
PCI_SB_AD<7>
PCI_SB_AD<8>
PCI_SB_AD<9>
PCI_SB_AD<10>
PCI_SB_AD<11>
PCI_SB_AD<12>
PCI_SB_AD<13>
PCI_SB_AD<14>
PCI_SB_AD<15>
PCI_SB_AD<16>
PCI_SB_AD<17>
PCI_SB_AD<18>
PCI_SB_AD<19>
PCI_SB_AD<20>
PCI_SB_AD<21>
PCI_SB_AD<22>
PCI_SB_AD<23>
PCI_SB_AD<24>
PCI_SB_AD<25>
PCI_SB_AD<26>
PCI_SB_AD<27>
PCI_SB_AD<28>
PCI_SB_AD<29>
PCI_SB_AD<30>
PCI_SB_AD<31>
PCI_SB_CBE_L<0>
PCI_SB_CBE_L<1>
PCI_SB_CBE_L<2>
PCI_SB_CBE_L<3>
PCI_SB_DEVSEL_L
PCI_SB_FRAME_L
PCI_SB_IRDY_L
PCI_SB_TRDY_L
PCI_SB_STOP_L
PCI_SB_PAR

73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73 76
77 76 75 74 25 7

=PP3V3_PCI

73

RP7402

73
73
77 76 74 73 6

PCI_DEVSEL_L

4.7K

73

5%
1/16W
SM1

RP7402

73
73
77 76 74 73 6

PCI_FRAME_L

4.7K

73

5%
1/16W
SM1

73
73
77 76 74 73 6

RP7402
2

PCI_IRDY_L

4.7K

73 77

5%
1/16W
SM1

RP7402

73
73
77 76 74 73 6

PCI_TRDY_L

4.7K

73

5%
1/16W
SM1

73

73

77 76 74 73 6

RP7401
7

PCI_STOP_L

4.7K

73
73

5%
1/16W
SM1

73

=PP3V3_PWRON_SB

7 23 25

73

Master: Link

73
73
73
73
73

R7455
4.7K

C7450 1R7450
0.1uF

20%
10V
2 CERM
402

5%
1/16W
MF
2 402

4.7K

Shasta PCI Interface

5%
1/16W
MF
2 402

5
1

SB_PCI_RESET_L

87 77 25 8

NOTICE OF PROPRIETARY PROPERTY

U7450 4
2

SYS_WARM_RESET_L

Shasta drives PCI RESET, but its output


may not be valid during power-up, so
it is ANDed with a reset from the SMU.

PCI_RESET_L 6

8 51 58

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

3MC74VHC1G08
SOT23-5

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

DRAWING

APPLE COMPUTER INC.

TITLE=LINK
ABBREV=DRAWING

DRAWING NUMBER

SCALE

LAST_MODIFIED=Wed Aug

SHT
NONE

4 17:58:24 2004

REV.

051-6482
OF

74
1

103

Page Notes
Power aliases required by this page:
- _PP3V3_PCI
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

NOTE: This page does not specify a BootROM


part number. Must use a TABLE_x_ITEM
symbol to declare U7500 part number.

77 76 75 74 25 7

=PP3V3_PCI

C7500 1 C7501
2.2uF

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
805

C7502 1
0.1uF

20%
10V
CERM 2
402

11

30

VPP

31

VCC

U7500

77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6

77 76 75 74 25 7

77 76 74 73 6

=PP3V3_PCI

77 76 74 73 6
77 76 74 73 6

R75001

R7501

10K

5%
1/16W
MF
402 2
76 74 6

ROM_CS_L

77 76 74 73 6

R7502
1

1K

10K

77 76 74 73 6

5%
1/16W
MF
2 402

77 76 74 73 6
77 76 74 73 6

76 6

5%
Allows ROM override module
1/16W
MF
to intercept ROM chip select

76 74 6
76 74 6

402

6
8

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>

21

ROM_ONBOARD_CS_L
ROM_OE_L
ROM_WE_L
ROM_WP_L
=PCI_ROM_RESET_L

22

20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
38

24
9
12
10

FEPR-1MX8
90.0ns
TSOP
A0
DQ0
A1 OMIT DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20

25
26
27
28
32
33
34
35

PCI_AD<24> 6
PCI_AD<25> 6
PCI_AD<26> 6
PCI_AD<27> 6
PCI_AD<28> 6
PCI_AD<29> 6
PCI_AD<30> 6
PCI_AD<31> 6

73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77

CE
OE
WE
WP
PWD

B
GND
23

39

Master: Link

BootROM

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING

APPLE COMPUTER INC.

TITLE=FIZZY
ABBREV=DRAWING

DRAWING NUMBER

D
SCALE

LAST_MODIFIED=Wed Aug

SHT
NONE

4 17:58:24 2004

REV.

051-6482

OF

75

103

8
ELECTRICAL_CONSTRAINT_SET
PCI_CLK_AIRPORT

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR
_PCI_CLK33M_AIRPORT

CLOCKS

8 76

Page Notes
Power aliases required by this page:
- _PP3V3_PCI
Signal aliases required by this page:
- _PCI_CLK33M_AIRPORT (33MHz PCI clock)

BOM options provided by this page:


(NONE)
PCI Devices implemented on this page:
AD17 (Slot "A") - AirPort (0x????/0x????)
NOTE: This AirPort implementation does
not support PME#.
77 75 74 25 7

=PP3V3_PCI
NO STUFF
1

NO STUFF

C7600
10UF

20%
2 6.3V
CERM
1206

C7601
10UF

20%
2 6.3V
CERM
1206

C7602
0.1UF

20%
2 10V
CERM
402

C7603
0.1UF

20%
2 10V
CERM
402

CRITICAL

J7600
RCPT-CARD-EDGE
F-ST-TH1

SIDE-A
8
6
74 6

77 75 74 73 6

77 75 74 73 6

77 75 74 73 6
77 75 74 73 6

77 74 73 6

77 74 73 6
77 74 73 6
77 75 74 73 6

77 75 74 73 6

77 74 73 6
77 74 73 6

77 74 73 6
77 75 74 73 6

PCI_AIRPORT_RESET_L
TP_AIRPORT_RF_DISABLE
PCI_SLOTA_REQ_L
PCI_AD<31>
PCI_AD<29>
PCI_AD<27>
PCI_AD<25>
PCI_CBE_L<3>
PCI_AD<23>
PCI_AD<21>
PCI_AD<19>
PCI_AD<17>
PCI_CBE_L<2>
PCI_IRDY_L
AIRPORT_CLKRUN_L_PD
PCI_CBE_L<1>
PCI_AD<14>

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51
77 75 74 73 6
77 75 74 73 6
75 74 6
77 75 74 73 6
77 75 74 73 6

77 75 74 73 6

75 6
77 75 74 73 6

77 75 74 73 6
75 74 6

PCI_AD<12>
PCI_AD<10>
ROM_WE_L
PCI_AD<8>
PCI_AD<7>
PCI_AD<5>
ROM_ONBOARD_CS_L
PCI_AD<3>
PCI_AD<1>
ROM_CS_L
NC
NC
NC

R7612
94 25 6

I2S1_MCLK
SCC_RTS_L

5%
1/16W
MF
402

94 25 6

I2S1_DEV_TO_SB_DTI
SCC_RXDA

NC
NC
NC

PP5V_PWRON_AIRPORT_MARTY
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

5%
1/16W
MF
402

94 25 6

=PP5V_PWRON_AIRPORT

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75
77

76 NC
78 NC

79

80

81

82 NC
84 NC

87

NC

91
93
95

PCI_AD<28>
PCI_AD<26>
PCI_AD<24>
PCI_SLOTA_IDSEL
PCI_AD<22>
PCI_AD<20>
PCI_PAR
PCI_AD<18>
PCI_AD<16>

6 74
6
6 25
6 73 74 75 77

6 73 74 75 77
6 73 74 75 77
6 73 74 75 77

R7600
1

6 73 74 77

22

PCI_SB_AD<17>

73 74

5%
1/16W
MF
402

6 73 74 75 77
6 73 74 77
6 73 74 75 77
6 73 74 75 77

PCI_FRAME_L
PCI_TRDY_L
PCI_STOP_L
PCI_DEVSEL_L
PCI_AD<15>
PCI_AD<13>
PCI_AD<11>

6 73 74 77
6 73 74 77
6 73 74 77
6 73 74 77

6 73 74 75 77
6 73 74 75 77
6 73 74 75 77

PCI_AD<9>
PCI_CBE_L<0>
ROM_OE_L
PCI_AD<6>
PCI_AD<4>
PCI_AD<2>
PCI_AD<0>

6 73 74 75 77
6 73 74 77
6 74 75
6 73 74 75 77

6 73 74 75 77
6 73 74 75 77
6 73 74 75 77

RESERVED FOR USB_DP AND USB_DN

86 NC
88 NC
90 NC
92 NC

RESERVED FOR RADIO_IO

94 NC
96 NC

97

98 NC

99

100 NC

R76011
10K
5%
1/16W
MF
402 2

R7613
0

58

PCI_SLOTA_GNT_L
TP_AIRPORT_PME_L
PCI_SLOTA_INT_L
PCI_AD<30>

8 76

5%
1/16W
MF
402

56

57

_PCI_CLK33M_AIRPORT

516-0069

R7611
I2S1_SB_TO_DEV_DTO
SCC_TXDA

55

89

I2S1_SB_TO_DEV_DTO_MARTY

R7610

52
54

85

NC

KEY

53

83

I2S1_MCLK_MARTY
I2S1_DEV_TO_SB_DTI_MARTY

SIDE-B

AirPort Extreme

5%
1/16W
MF
402

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

76

103

ELECTRICAL_CONSTRAINT_SET
PCI_CLK_USB2

NET_SPACING_TYPE

DIFFERENTIAL_PAIR
=PCI_CLK33M_USB2

CLOCKS

8 77

Page Notes
Power aliases required by this page:
- _PPVIO_PCI (to 3.3V or 5V)
Signal aliases required by this page:
- _PCI_CLK33M_USB2 (33MHz PCI clock)

BOM options provided by this page:


(NONE)
7

=PPVIO_PCI_USB2

PCI Devices implemented on this page:


AD27 (Slot "G") - USB2 (0x1033/0x0035)

C7703 1

NOTE: This USB2 implementation supports


D3cold.

0.1uF

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>

M5

(PCI_AD<27>)
6 PCI_AD<28>
6 PCI_AD<29>
6 PCI_AD<30>
6 PCI_AD<31>

C4

76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6

76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 74 73 6
76 74 73 6
76 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6

PCI_AD<27>
76 75 74 73
76 75 74 73

74 73

PCI_SB_AD<27>

76 75 74 73
76 75 74 73

76 74 73 6

R77141
22

5%
1/16W
MF
402 2

76 74 73 6
76 74 73 6
76 74 73 6

76 74 73 6

76 75 74 25 7

76 74 73 6

=PP3V3_PCI

76 74 73 6
76 74 73 6

R77161 R77131
RP7703
25

PCI_SLOTG_INT_L

47

47

5%
1/16W
SM1
8

=PCI_USB2_RESET_L

74

47

77 8

47

5%
1/16W
SM1

RP7702
4

74

RP7702

SYS_WARM_RESET_L

SYS_PME_L

76 74 73 6

N5
P4
N4
M3
N3
M1
L2
L1
K2
L3
K1
K3
J2
J1
F2
E3
E1
D3
D1
D2
C2
C1
B4
A4
B5

A5
C5
B6
A6

M2

PCI_CBE_L<0>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_CBE_L<3>

J3
F1
C3

PCI_PAR
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_SLOTG_IDSEL
PCI_DEVSEL_L
PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
NEC_PERR_L_PU
NEC_SERR_L_PU
NEC_INTA_L
NEC_INTB_L
NEC_INTC_L
=PCI_CLK33M_USB2

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

NEC_VBBRST_L
NEC_CRUN_L_PD
NEC_PME_L
NEC_VCCRST_L
TP_NEC_SMI_L

47

C8

NEC_uPD720101_USB2
FBGA

CBE0
CBE1
CBE2
CBE3

J4

PAR
FRAME
IRDY
G1
TRDY
G3
STOP
B3 IDSEL
G2
DEVSEL
C6
REQ
D6
GNT
H2
PERR
H1
SERR OD
C7
INTA OD
B7
INTB OD
A7
INTC OD
A8
PCLK
F3
F4

B8
N6
D9
C9
L6

VBBRST (CHIP RESET)


CRUN
PME OD
VCCRST (PCI RESET)
SMI OD

RP7702

M4

CRITICAL

U7700

5%
1/16W
SM1

25 13

5%
1/16W
MF
402 2

5%
1/16W
SM1

RP7703

87 74 25 8

5%
1/16W
MF
402 2

76 74 73 6

RP7703
2

47

10K

5%
1/16W
SM1

10K

P5

VDD_PCI

H3

20%
10V
CERM 2
402

L7

NEC_LEGC_PD

LEGC

B
IPD NTEST1 M8

TP_NEC_NTEST1

IPD

SMC M7

TP_NEC_SMC

IPD
IPD

TEB N7
AMC P7

TP_NEC_TEB
TP_NEC_AMC

IPD

TEST L8

NANDTEST
SRCLK
SRDTA
IPD SRMOD

M10
M9
N9
P9

TP_NEC_TEST

TP_NEC_NANDTEST
TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD

6
6

6
6
6
6

7
8

5%
1/16W
SM1

R77151
5%
1/16W
MF
402 2

RP7702 & RP7703 required to


facilitate NAND-tree testing

Master: Link

RP7703

4.7K

47
5%
1/16W
SM1

USB 2.0 PCI Interface

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING

APPLE COMPUTER INC.

TITLE=FIZZY
ABBREV=DRAWING

DRAWING NUMBER

D
SCALE

LAST_MODIFIED=Wed Aug

SHT
NONE

4 17:58:25 2004

REV.

051-6482

OF

77

103

8
ELECTRICAL_CONSTRAINT_SET

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR

SATA_RXD1
SATA_RXD1

SATA
SATA

SATA_RXD1_C
SATA_RXD1_C

SATA_RXD_P1_C
SATA_RXD_N1_C

SATA_TXD1
SATA_TXD1

SATA
SATA

SATA_TXD1
SATA_TXD1

SATA_TXD_P1
SATA_TXD_N1

SATA_RXD2
SATA_RXD2

SATA
SATA

SATA_RXD2_C
SATA_RXD2_C

SATA_RXD_P2_C
SATA_RXD_N2_C

SATA_TXD2
SATA_TXD2

SATA
SATA

SATA_TXD2
SATA_TXD2

SATA_TXD_P2
SATA_TXD_N2

80 83

80 83

RP8000

80 83

80 83

80

UATA_DD_R<0>

80 83

80

UATA_DD_R<1>

33

UATA_DD<0>

6 80 83

UATA_DD<1>

6 80 83

UATA_DD<2>

6 80 83

UATA_DD<3>

6 80 83

UATA_DD<4>

6 80 83

UATA_DD<5>

6 80 83

UATA_DD<6>

6 80 83

UATA_DD<7>

6 80 83

UATA_DD<8>

6 80 83

UATA_DD<9>

6 80 83

UATA_DD<10>

6 80 83

UATA_DD<11>

6 80 83

UATA_DD<12>

6 80 83

UATA_DD<13>

6 80 83

UATA_DD<14>

6 80 83

UATA_DD<15>

6 80 83

UATA_DA<0>

6 80 83

UATA_DA<1>

6 80 83

UATA_DA<2>

6 80 83

UATA_RESET_L

6 80 83

UATA_CS0_L

6 80 83

UATA_CS1_L

6 80 83

UATA_HSTROBE

6 80 83

UATA_STOP

6 80 83

UATA_DMACK_L

6 80 83

80 83

5%
1/16W
SM1

6 80 83
80

6 80 83

UATA_DD_R<2>

6 80 83

80

6 80 83

UATA_DD_R<3>

33

6 80 83
80

6 80 83

RP8001
1

UATA_DD_R<4>

6 80 83

80 83

80

UATA_DD_R<5>

33

80 83

Page Notes

80

Power aliases required by this page:


- _PP1V2_PWRON_DISK

RP8003
3

UATA_DD_R<6>

UATA_DD_R<7>

C8000
0.1uF

20%
2 10V
CERM
402

Net Spacing Type: SATA

C8001
0.1uF

20%
2 10V
CERM
402

C8002
0.1uF

20%
2 10V
CERM
402

C8003

0.1uF

C8004

20%
2 10V
CERM
402

UATA_DD_R<9>

AB14

80

UATA_DD_R<11>

80

UATA_DD_R<12>

OMIT

SHASTA
80

UD_IDEDD_0_H J6
UD_IDEDD_1_H H7
UD_IDEDD_2_H H6
UD_IDEDD_3_H E2
UD_IDEDD_4_H C1

UATA

UD_IDEDD_5_H C2
UD_IDEDD_6_H E3
UD_IDEDD_7_H G6
UD_IDEDD_8_H G5
UD_IDEDD_9_H D4
UD_IDEDD_10_H G7
UD_IDEDD_11_H F6
UD_IDEDD_12_H C3
UD_IDEDD_13_H F5
UD_IDEDD_14_H E5
UD_IDEDD_15_H D5

DSTROBE aka:
IORDY/HDMARDY*
HSTROBE aka:
DIOR*

UD_IDEDA0_H E6
UD_IDEDA1_H C4

STOP aka:
DIOW*

UD_IDEDA2_H D6

UATA_DSTROBE

F9 UD_IDECHRDY_H

UD_IDECS1FX_L
UD_IDECS3FX_L

B3
B4

83 80

UATA_DMARQ

D7 UD_IDEDMARQ_H

UD_IDEDMACK_L

E8

UATA_INTRQ

C5 UD_IDEINTRQ_H

UD_IDERD_L

83 80

E4
D3

83 80

UD_IDEWR_L
UD_IDERST_L

E7

UATA_DD_R<0>
UATA_DD_R<1>
UATA_DD_R<2>
UATA_DD_R<3>
UATA_DD_R<4>
UATA_DD_R<5>
UATA_DD_R<6>
UATA_DD_R<7>
UATA_DD_R<8>
UATA_DD_R<9>
UATA_DD_R<10>
UATA_DD_R<11>
UATA_DD_R<12>
UATA_DD_R<13>
UATA_DD_R<14>
UATA_DD_R<15>
UATA_DA_R<0>
UATA_DA_R<1>
UATA_DA_R<2>
UATA_CS0_L_R
UATA_CS1_L_R
UATA_DMACK_L_R
UATA_HSTROBE_R
UATA_STOP_R
UATA_RESET_L_R

80
80

80

AB15 RXDP2
AA15 RXDN2

AC coupling required for any SATA pair used.


Recommend 0.1uF cap placed close to Shasta.
(Caps provided by device page)

SATA 1

TXDP1 AA16 SATA_TXD_P1


TXDN1 AB16 SATA_TXD_N1
TXDP2 Y15
TXDN2 Y14

SATA_TXD_P2
SATA_TXD_N2

33

80

80

RP8004
1

UATA_DD_R<15>

33

80
80

80

RP8004
2

80

80

UATA_DA_R<1>

33

80
80

80

RP8004
4

UATA_DA_R<2>

80

80

UATA_RESET_L_R

33

33

5%
1/16W
SM1

RP8004

80

5%
1/16W
SM1

80

33

5%
1/16W
SM1

RP8001

80

5%
1/16W
SM1

UATA_DA_R<0>

80

33

5%
1/16W
SM1

80

RP8003

80

33

5%
1/16W
SM1

UATA_DD_R<14>

80

80

5%
1/16W
SM1

80

80

80

R8000
1

UATA_CS0_L_R

80

80
80

UATA_CS1_L_R

80

80 83
80

R8003

5%
1/16W
MF
402

UATA_STOP_R

80 83

80

22

5%
1/16W
MF
402

80 83

SATA_GND

R8002

UATA_HSTROBE_R

80 83

5%
1/16W
MF
402

80
80

33

33

5%
1/16W
MF
402

R8001

W16

83 80

SATA_RXD_P2_C
SATA_RXD_N2_C

SATA 0

AA17
T13

83 80

Y17 RXDP1
Y16 RXDN1

AA14

83 80

SATA_RXD_P1_C
SATA_RXD_N1_C

RP8001

5%
1/16W
SM1

80
83 80

UATA_DD_R<13>

80

33

5%
1/16W
SM1

RP8002

V1.0
BGA
(5 OF 8)

33

5%
1/16W
SM1

SATA_VDD

RP8000
1

UATA_DD_R<10>

80

33

5%
1/16W
SM1

RP8002

U2300

NOTE: Target differential impedance for


SATA data pairs is 100 ohms.

33

5%
1/16W
SM1

20%
2 10V
CERM
402

Line To Line:
15 mils
Length Tolerance:
50 mils
Primary Max Sep:
10 mils outer
Primary Max Sep:
9 mils inner
Secondary Max Sep: 100 mils
Secondary Length: 500 mils

RP8002

RP8003
80

5%
1/16W
SM1

UATA_DD_R<8>

0.1uF

W15
Y18

80

5%
1/16W
MF
402 2

AB17
T14

BOM options provided by this page:


(NONE)

10K

SATA_VDD x 5

=PP1V2_PWRON_DISK_SB

33

5%
1/16W
SM1

R80051
7

33

5%
1/16W
SM1

80 83

33

5%
1/16W
SM1

RP8001

6 80 83

5%
1/16W
SM1

6 80 83

33

5%
1/16W
SM1

RP8003

6 80 83

RP8000

RP8002

Signal aliases required by this page:


(NONE)

33

5%
1/16W
SM1

RP8000

80 83

UATA_DD<15..8>
UATA_DD<7>
UATA_DD<6..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_HSTROBE
UATA_STOP
UATA_DMACK_L
UATA_RESET_L
UATA_DSTROBE
UATA_DMARQ
UATA_INTRQ

UATA_DD
UATA_DD7
UATA_DD
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST_R
UATA_HOST_R
UATA_DEV_R_C
UATA_DEV_R
UATA_DEV_R

UATA Termination

80 83

80

UATA_DMACK_L_R

22

R8004
1

22

5%
1/16W
MF
402

Master: Link

Shasta Disk

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING

APPLE COMPUTER INC.

TITLE=FIZZY
ABBREV=DRAWING

DRAWING NUMBER

SCALE

LAST_MODIFIED=Wed Aug

SHT
NONE

4 17:58:27 2004

REV.

051-6482
OF

80
1

103

ELECTRICAL_CONSTRAINT_SET
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6

83 80
83 80
83 80

UATA_DD<15..8>
UATA_DD<7>
UATA_DD<6..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_HSTROBE
UATA_STOP
UATA_DMACK_L
UATA_RESET_L
UATA_DSTROBE
UATA_DMARQ
UATA_INTRQ

NET_PHYSICAL_TYPE

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

UATA_DD
UATA_DD7
UATA_DD
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST_R
UATA_HOST_R
UATA_DEV_R_C
UATA_DEV_R
UATA_DEV_R

SATA CONNECTORS
PATA CONNECTOR
C8304
SATA_TXD_P1_C

J8300

0.1UF
1
2

SATA_TXD_P1

80

20%
10V
CERM
402

SATA_TXD_N1

80

C8305

LD18077-S04
M-ST-TH

SATA_TXD_N1_C

0.1UF
1
2

SATA_RXD_N1

0.1UF
1
2

C8308

5
6

=PP5V_PATA
=PP3V3_PATA
ATA-6 spec does not call out R8180 or R8182
NO STUFF

C8307

20%
10V
CERM
402

83 7

0.1UF
1
2

SATA_RXD_P1

20%
10V
CERM
402

R8313
SATA_RXD_N1_C

10K

10K

80

5%
1/16W

5%
1/16W
MF
402 2

SATA_RXD_P1_C

CRITICAL MF

J8301
1

F-ST-SM
51

R8314

20%
10V
CERM
402

518-0157

4.7K
5%
1/16W
MF
2 402

NC

Per ATA Spec

83 80 6
83 80 6
83 80 6
83 80 6

DEVELOPMENT

C8302
SATA_TXD_P2_C
DEVELOPMENT

NOSTUFF

J8302

C8303
0.1UF
1
2

LD18077-S04
M-ST-TH

SATA_TXD_N2_C

0.1UF
1
2

SATA_TXD_P2

SATA_RXD_N2

83 80 6
6

SATA_RXD_N2_C

DEVELOPMENT

C8306

5
6

0.1UF
1
2

0.1UF
1
2

SATA_RXD_P2

20%
10V
CERM
402

R8315

80
83 80

SATA_RXD_P2_C

UATA_DSTROBE

82

83 80 6

5%
1/16W
MF
402

80

83 80 6
83 80 6

R8316

20%
10V
CERM
402

518-0157

83 80

UATA_INTRQ

NO STUFF

82

10pF

UATA_STOP
UATA_DSTROBE_R
UATA_INTRQ_R
UATA_DA<1>
UATA_DA<0>
UATA_CS0_L
UATA_DASP_L

5%
1/16W
MF
402

C8301 1

5%
50V
CERM 2
402

UATA_RESET_L
UATA_DD<7>
UATA_DD<6>
UATA_DD<5>
UATA_DD<4>
UATA_DD<3>
UATA_DD<2>
UATA_DD<1>
UATA_DD<0>

80

C8300

20%
10V
CERM
402

83 80 6
83 80 6

80

83 80 6

SATA_TXD_N2
DEVELOPMENT

1
2

Sourced by drive
Terminate near connector

83 80 6

83 80 6

20%
10V
CERM
402

UATA_CSEL_PD

S05B-XA

UATA_DMARQ

82

10
12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

NC 49

50

NC
NC

5%
1/16W
MF
2 402

Obsolete

UATA_DD<8>
UATA_DD<9>
UATA_DD<10>
UATA_DD<11>
UATA_DD<12>
UATA_DD<13>
UATA_DD<14>
UATA_DD<15>

6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83

UATA_HSTROBE

6 80 83

UATA_DMACK_L
UATA_IOCS16_PU

6 80 83

NC
UATA_DA<2>
UATA_CS1_L

6 80 83
6 80 83

NC

UATA_DMARQ_R
516S0235

ATA-6 spec does not call out C8177


6 7
83 7

=PP12V_DISK

R83191

=PP5V_PATA

DEVELOPMENT
1

=PP3V3_DISK

R8321

R8318 1R8317

5.6K

6 7

M-RT-TH
1

1K

11

5%
1/16W
MF
402

=PP5V_DISK

R8312

R8320
83 80

CRITICAL

52

HD POWER

J8303

402 2

804RVS-050505R

80

R83111

NO STUFF

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

499

1%
1/16W
MF
402 2

3
4

6.2K

5%
1/16W
MF
2 402
PER ATA7 SPEC

Per ATA Spec


Per ATA Spec

DEVELOPMENT

LED8301

UATA_DASP_L_DS
518-0144

GREEN
2.0X1.25A

"UATA ACTIVE"

DISK CONNECTORS

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

83

103

8
ELECTRICAL_CONSTRAINT_SET

7
NET_PHYSICAL_TYPE

NET_SPACING_TYPE
10
10
15
15
15

MIL
MIL
MIL SPACING
MIL SPACING
MIL SPACING

DIFFERENTIAL_PAIR
ENET_CLK25M_TX
ENET_CLK125M_RX
ENET_CLK125M_GBE_REF
ENET_CLK125M_GTX
ENET_CLK125M_GTX_R

ENET_RX_CLK
ENET_RX_CLK
ENET_GBE_REF
ENET_TX_CLK

ENET
ENET
ENET
ENET
ENET

ENET_RX
ENET_RX_CTL
ENET_RX_CTL

ENET
ENET
ENET

ENET_RXD<7..0>
ENET_RX_DV
ENET_RX_ER

ENET_TX
ENET_TX_CTL
ENET_TX_CTL

ENET
ENET
ENET

ENET_TXD<7..0>
ENET_TX_EN
ENET_TX_ER

ENET_RX_CTL
ENET_RX_CTL
ENET_MDC
ENET_MDIO

ENET
ENET
ENET
ENET

ENET_CRS
ENET_COL
ENET_MDC
ENET_MDIO

84 87
84 87
84 87
84 87
84

84 87
84 87
84 87

84 87

84 87
84 87

84 87
84 87
84 87
84 87

Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

RP8400
2

U2300
SHASTA

ETHERNET

87 84

ENET_CLK25M_TX
ENET_CLK125M_RX

ETH_TXD_0_H G4
ETH_TXD_1_H E1
ETH_TXD_2_H H4

K1 ETH_RXD_0_H
L3 ETH_RXD_1_H
K2 ETH_RXD_2_H

J2 ETH_RXD_6_H
G1 ETH_RXD_7_H

ETH_TXD_6_H J4
ETH_TXD_7_H K6

ENET_TXD_R<0>
ENET_TXD_R<1>
ENET_TXD_R<2>
ENET_TXD_R<3>
ENET_TXD_R<4>
ENET_TXD_R<5>
ENET_TXD_R<6>
ENET_TXD_R<7>

87 84

ENET_RX_DV
ENET_RX_ER

K4 ETH_RX_DV_H
G2 ETH_RX_ER_H

ETH_TX_EN_H H3
ETH_TX_ER_H F1

ENET_TX_EN_R
ENET_TX_ER_R

87 84

ENET_CLK125M_GBE_REF

M5 ETH_REFCLK_H

87 84

ENET_CRS

L6 ETH_CRS_H

ETH_MDC_H M4

87 84

ENET_COL

L5 ETH_COL_H

ETH_MDIO_H M6

87 84
87 84
87 84
87 84
87 84
87 84
87 84

J1 ETH_RXD_3_H
L4 ETH_RXD_4_H
K3 ETH_RXD_5_H

ETH_TXD_3_H J5
ETH_TXD_4_H G3
ETH_TXD_5_H F2

0K

ETH_GTX_CLK_H K5

84

3
84 87

ENET_MDIO

84 87

0K

ENET_TXD<3>

84 87

ENET_TXD<4>

84 87

ENET_TXD<5>

84 87

0K

ENET_TXD<6>

84 87

ENET_TXD<7>

84 87

ENET_TX_EN

84 87

ENET_TX_ER

84 87

ENET_CLK125M_GTX

84 87

R8400
1

5%
1/16W
MF
402

0K

5%
1/16W
SM1

84 87

5%
1/16W
SM1

5%
1/16W
MF
402

R8401

ENET_TXD<2>

RP8401

RP8401

ENET_MDC

5%
1/16W
SM1

ENET_CLK125M_GTX_R

84 87

5%
1/16W
SM1

RP8401

1
87 84

ENET_TXD<1>

RP8401
2

0K

0K

5%
1/16W
SM1

84 87

5%
1/16W
SM1

RP8400

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RXD<4>
ENET_RXD<5>
ENET_RXD<6>
ENET_RXD<7>

87 84

ENET_TXD<0>

RP8400
1

BGA
(6 OF 8)
H5 ETH_TX_CLK_H
J3 ETH_RX_CLK_H

5%
1/16W
SM1

V1.0
87 84

0K

0K

5%
1/16W
SM1

RP8400

OMIT

R8402
1

5%
1/16W
MF
402

Master: Link

Shasta Ethernet

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING

APPLE COMPUTER INC.

TITLE=FIZZY
ABBREV=DRAWING

DRAWING NUMBER

SCALE

LAST_MODIFIED=Tue Aug

SHT
NONE

3 15:55:45 2004

REV.

051-6482
OF

84
1

103

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

ETHERNET ROUTING PRIORITY:

ENET_MDI_TX
ENET_MDI_TX

ENET
ENET

ENET_MDI_TD
ENET_MDI_TD

ENET_TDP
ENET_TDN

ENET_MDI_RX
ENET_MDI_RX

ENET
ENET

ENET_MDI_RD
ENET_MDI_RD

ENET_RDP
ENET_RDN

1. DECOUPLING CAPS
87

2. TX TERMINATION - LOCATE NEAR PHY


87

3. RX TERMINATION - LOCATE NEAR PHY


87

ROUTE TD OVER 2.5V PLANE (BOTTOM LAYER) ONLY

87

ROUTE RD OVER GROUND PLANE (TOP LAYER) ONLY

ENET_XTAL

ENET_CLK25M_XIN
ENET_CLK25M_XOUT

15 MIL SPACING
15 MIL SPACING

87
87

ALL DIFFERENTIAL SIGNALS SHOULD BE CLOSE,


VOLTAGE=2.5V

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP2V5_ENET

PARALLEL, MATCHED LENGTHS, WITH MINIMUM

VIA COUNT, AND SHORT IF POSSIBLE

87 7

ENET_DVDD

C8704

C8702

0.01UF
20%
16V
CERM
402

0.1UF
20%
10V
CERM
402

C8705

0.01UF
20%
16V
CERM
402

C8712

CLEAR OUT ALL PLANES BETWEEN MIDDLE

10UF
20%
6.3V
CERM
805

OF TRANSFORMER AND CONNECTOR

C8709
0.01UF
20%
16V
CERM
402

22

NC

46

0.1UF
20%
10V
CERM
402

OVDD/NC

BIASVDD

REFCLK

OVDD2

OVDD1

AVDD2

AVDD1

DVDD2

DVDD1

NOTE: PLACE R3128, R3100, RP 3101 CLOSE TO PHY

REGAVDD

REGDVDD

1
(PLACE R3126, R3127
R3117, R3118
CLOSE TO PHY)
2

C8710

R8701 1

0.1UF
20%
10V
CERM
402

49.9
1%
1/16W
MF
402

R8706

84

33

1/16W

1/16W

5%

5%

RP8701

ETHPHYRESET_L
NET_SPACING_TYPE=10 MIL

33

1/16W

84

5%

42

ENET_MDC

41

PP3V3_PWRON_ENET

87 7

C8750

0.1uF

5
77 74 25 8

SYS_WARM_RESET_L

87 7

PP3V3_PWRON_ENET

U8750 4
2

R87191

20%
2 10V
CERM
402

NC

R8711
1

2
5%
1/16W
MF
402

3MC74VHC1G08
SOT23-5

1K

87 7

Q8700

2N7002

13

NC

14

1.5K
1%
1/16W
MF
603 2

90

NOSTUFF
1

C8723

1UF
20%
10V
CERM
603

SM
25

NC

PP3V3_PWRON_ENET

12

R87081
ENETFW_RESET_L

11

NC

PHY ADDRESS 00000

5%
1/16W
MF
402 2

ENETFW_RESET

NC

ETHPHYRESET_L_R

10

S
2

84

ENET_MDIO

87
CRITICAL

C8701
27PF
5%
50V
CERM
603

LNKLED/JTAG_TDI*
SPDLED/JTAG_TMS*
XMTLED*
RCVLED/JTAG_TDO*

87

12

35

ENET_TDI
ENET_TMS
XMIT_LED
TP_ENET_TDO

36
34
33

C8706

0.1UF
20%
10V
CERM
402

C8707

0.1UF
20%
10V
CERM
402

C8714

0.1UF
20%
10V
CERM
402

0.1UF
20%
10V
CERM
402

RX-SIDE
RJ45
CHIP SIDE

0.1UF
20%
10V
CERM
402

75
OHM

C8721
0.1UF
20%
10V
CERM
402

SHIELD

TWO OF THESE CAPS SHOULD BE NEAR


J8700 PINS 2&5

87
87

75
OHM

PP3V3_PWRON_ENET

PP3V3_PWRON_ENET

PP3V3_PWRON_ENET

87

DEVELOPMENT

DEVELOPMENT

R8704
10K
5%
1/16W
MF
402

R8718
4.7K
5%
1/16W
MF
603

R8717
330
5%
1/16W
MF
603

DS3P1
1

R8704 PULLDOWN ENABLES


AUTO-MDI/MDIX

87

ENET_TMS

87

XMIT_LED

87

ENET_TDI

RP8702
10K

R8716
330
5%
1/16W
MF
603

DS1P1

DEVELOPMENT

DEVELOPMENT

LED8702

LED8701

GREEN
2.0X1.25A

GREEN
2.0X1.25A

10/100

R8715
330
5%
1/16W
MF
603

R8714

4.7K
5%
1/16W
MF
603

DS2P1
1

DEVELOPMENT

LED8700
GREEN
2.0X1.25A

XMIT

LINK

5%
87

87

ENET_5221_FDX
ENET_5221_TESTEN
ENET_5221_LOW_PWR
OGND3_JTAG_EN

C8713
10UF
20%
6.3V
CERM
1206

NOTE: LINK SUPPORT FOR GIGABIT ETHERNET PULLED DOWN OR ALIASED TO TEST POINTS HERE.
I228
I232
ENET_RXD_PD
TP_ENET_TXD<4>
84 ENET_CLK125M_GBE_REF
84 ENET_TXD<4>
6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
I229
I233
ENET_RXD<5>
TP_ENET_TXD<5>
84 ENET_TXD<5>
6
MAKE_BASE=TRUE
I230
I234
ENET_RXD<6>
TP_ENET_TXD<6>
84 ENET_TXD<6>
6
R87981
MAKE_BASE=TRUE
10K
I231
I235
ENET_RXD<7>
TP_ENET_TXD<7>
1%
84 ENET_TXD<7>
6
1/16W
MAKE_BASE=TRUE
MF
I236
TP_ENET_CLK125M_GTX
402
84 ENET_CLK125M_GTX
2
MAKE_BASE=TRUE
R87991
ENET_RXD<4>

10K
1%
1/16W
MF
402

ETHERNET PHY
LAST_MODIFIED=Wed Aug

4 17:58:31 2004

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
2

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6482

SCALE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SIZE

75
OHM

1000PF, 2000V

KEEP ALL CAPS CLOSE TO TRANSCEIVER ON THIS PAGE

75
OHM

OGND3_JTAG_EN

87

0.1UF
20%
10V
CERM
402

J8

SM1

J7

1/16W

84

4.7UF
20%
10V
CERM
1206

1CT:1CT

11

87

84

TX-SIDE

RJ45
CABLE SIDE

ENET_ENERGYDET 25

87

A
C8717

J5
J6

DEVELOPMENT

27PF
5%
50V
CERM
603

84

J4

C8700

PP3V3_PWRON_ENET

ENET_RDN

ANEN
15 ENET_5221_TESTEN 87
18
MII_EN
16 ENET_5221_LOW_PWR 87

1.27K
1%
1/16W
MF
402

84

C8718

ENET_CLK25M_XOUT

J2
J3

5%
1/16W
MF
402

R8705 1

87

1%
1/16W
MF
402
2

10K

J1

38

ENERGY_DET 17
RDAC 23

Y8700

C8719

49.9

1%
1/16W
MF
402

8X4.5MM-SM

R8713

R8702

ENET_CLK25M_XIN

25.0000M
1
2

C8720

5%
1/16W
MF
402

87

ENET_TDN
ENET_RDP

(PLACE Y8700 CRYSTAL CLOSE TO PHY)

SHASTA SIGNAL IS ACTIVE HIGH

87

61

39 ENET_5221_FDX
37
TP_ENET_TCK

ENET_RDAC_PD

62

ENET_PHY_COL
1

R8703

GND_CHASSIS_RJ45

BIASGND

84

33

RP8701

ENET_PHY_CRS

51

RP8701

ENET_RX_ER
ENET_CRS
ENET_COL

49

24

SM1

ENET_PHY_RX_DV
ENET_PHY_RX_ER

XTALGND

84

43

1/16W

5%
1/16W
MF
402
84

44

47

AGND2

ENET_PHY_RXD<0>
ENET_PHY_RXD<1>
ENET_PHY_RXD<2>
ENET_PHY_RXD<3>

RXC
RXD0
RXD1
RXD2
RXD3
RXDV
RXER
CRS
COL
RESET*
MDC
MDIO
XTALI
XTALO
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4

32

48

AGND1

NET_SPACING_TYPE=10 MIL

FDX
F100/JTAG_TCK
ANEN/JTAG_TRST
TESTEN
OVDD/NC
LOW_PWR

29

10K

50

CLKENET_PHY_RX

DGND2

SECONDARY
1CT:1CT

1
2

PP3V3_PWRON_ENET

NC

R8712

2
402
5%

DGND1

SYM_VER-3

ENET_TDP

49.9

63

33

ENET_RX_DV

CRITICAL

54

84

TXEN
TXER

OGND3/
JTAG_EN

84

(SYM_VER2)

64

84

52

TQFP

OGND2

1
MF
1/16W

5%

84

56

ENET_TX_EN
ENET_TX_ER

33

33

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
R8709

60

10

R8707

RP8700
84

59

U8700
BCM5231

87

NET_SPACING_TYPE=10 MIL

58

84

CLK_ENET_LINK_RX
MAKE_BASE=TRUE

F-ST-TH
9

87

57

ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>

TD+ 31
TD- 30
RD+ 26
RD- 25
NC 21
NC 19

84

84

I238

J8700
RJ45
JFM24V10

84

84

ENET_CLK125M_RX

CRITICAL

49.9
1%
1/16W
MF
402

87

NET_SPACING_TYPE=10 MIL

TXC
TXD0
TXD1
TXD2
TXD3

NET_SPACING_TYPE=10 MIL
5%
1/16W
MF
402

84

53

CLKENET_PHY_TX

45

MAKE_BASE=TRUE

R8700

(514-0200)

0.1UF
20%
10V
CERM
402

PRIMARY

33

CLK_ENET_LINK_TX

OGND1

I237
ENET_CLK25M_TX

40

84

C8722

C8715

28

0.01UF
20%
16V
CERM
402

27

C8708

55

0.1UF
20%
10V
CERM
402

C8716

10UF
20%
6.3V
CERM
805

20

C8711

0.1UF
20%
10V
CERM
402

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP3V3_PWRON_ENET

C8703

OF

87

103
DRAWING

ELECTRICAL_CONSTRAINT_SET
FW
FW
FW_LPS
FW_LREQ
FW_PINT
FW_LCLK
FW_PCLK

NET_PHYSICAL_TYPE
FW
FW
FW
FW
FW
FW
FW

NET_SPACING_TYPE

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

DIFFERENTIAL_PAIR
FW_DATA<7..0>
FW_CTL<1..0>
FW_LPS
FW_LREQ
FW_PINT
FW_CLK98M_LCLK
FW_CLK98M_PCLK
FW_CLK98M_LCLK_R

88 90
88 90
88 90
88 90
88 90
88 90
88 90
88

Page Notes

Power aliases required by this page:


- _PP2V5_PWRON_SB
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

=PP2V5_PWRON_SB

C8800
0.1uF

20%
2 10V
CERM
402

C8801
0.1uF

20%
2 10V
CERM
402

C8802
0.1uF

20%
2 10V
CERM
402

N5
J7

A4

74 25 23 7

FWVDDP

U2300

OMIT

SHASTA
V1.0
BGA
(7 OF 8)

FIREWIRE

PHY_DATA_0_H N4
PHY_DATA_1_H P5

FW_DATA<0>
FW_DATA<1>
FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<6>
FW_DATA<7>

PHY_DATA_2_H N1
PHY_DATA_3_H M7
PHY_DATA_4_H N6
PHY_DATA_5_H L1
PHY_DATA_6_H M3
PHY_DATA_7_H L2
PHY_CTL_0_H N2
PHY_CTL_1_H N3

FW_CTL<0>
FW_CTL<1>

PHY_LPS_H P6
PHY_LREQ_H P1
90 88

FW_CLK98M_PCLK

P2 PHY_SCLK_H

PHY_LCLK_H R1

90 88

FW_PINT

P3 PHY_PINT_L

PHY_LINKON_L N7

FW_LPS
FW_LREQ
88

88 90
88 90
88 90
88 90
88 90
88 90
88 90
88 90

88 90
88 90

88 90
88 90

FW_LINKON

R8800
1

FW_CLK98M_LCLK_R
90

22

FW_CLK98M_LCLK

88 90

5%
1/16W
MF
402

Master: Link

Shasta FireWire

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING

APPLE COMPUTER INC.

TITLE=FIZZY
ABBREV=DRAWING

DRAWING NUMBER

SCALE

LAST_MODIFIED=Wed Aug

SHT
NONE

4 17:58:31 2004

REV.

051-6482
OF

88
1

103

PP24V_RUN

VERTICAL

R9056
0

VOLTAGE=24V
MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL

5%
1W
FF
2512

5%
1/8W
FF
1206 2

BAV99DW
SOT-363
2

D
90

D9002

FW_TPA1N

NOSTUFF

FW_TPB1P

D9002

DZ9050

BAV99DW

1N5248B

SOT-363

90

FW_TPB1N

NOSTUFF
3

2K

18K

5%
1/8W
FF
2 1206

5%
1/16W
MF
2 402

Q9051_COLLECTOR

BAV99DW
SOT-363
5

SM

FW_VGND

FL9001

90 6

FW_TPO1N

90 6

FW_TPI1P

90 6

FW_TPI1N

FW_VP_PORT1

TPO
TPO#
TPI

VP

VGND

SM
2

VOLTAGE=24V

MIN_LINE_WIDTH=35MIL

PORT POWER
RAMP

PHY

SLEEP

OFF

ON

OFF

OFF

ON

SLEEP

ON

ON

OFF

OFF

ON

SLEEP

ON

ON

C9018 1

CHOICE A
90

NEW PS

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=3.3V

OFF

ON

100PF

165-OHM
SM

0.01UF
10%
50V
CERM
805

GND_CHASSIS_FIREWIRE

PORT 2

GND_CHASSIS_FIREWIRE

514-0202

SYM_VER-1

ON

C9010

FL9002

CHOICE B

0.01UF
10%
16V
CERM
402

C9024

5%
50V
CERM
402

CRITICAL

J9001
FWS22

2
VOLTAGE=3.3V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

PP3V3_FW

F-ST-TH
90 6

FW_TPO2P

90 6

FW_TPO2N

90 6

FW_TPI2P

90 6

FW_TPI2N

6 FW_VP_PORT2

TPO

FL9003

90

165-OHM
SM

TPO#

SYM_VER-1

1
NO STUFF
1

R9098
4.7K
5%
1/16W
MF
402

C9004

U9000

1000pF
5%
25V
CERM
603

FW_CLK25M_XIN

43

NOSTUFF

10K
5%
1/16W
MF
402

22

FW_LREQ

88

88
88
88
88
88
88

470

5%
1/16W
MF
402

24
59

FW_CLK25M_XOUT
25 FW_LOWPWR

60
19
28
29
61

FW_PHY_ISO_L

FW_LPS

23
16

RP9000

FW_LREQ_R

1
57

NOTE: 49M, NOT 98M CLK FOR 1394-A


88 FW_CLK98M_PCLK
NAMING KEPT FROM NEOBORG
88 FW_CTL<0>
88 FW_CTL<1>

88

FW_CLK25M_XOUT_R 1

CPS

R9061

FW_PHY_RST_L

90 88

88

51

24.576M
SM
2

5%
50V
CERM
603

50

0
5%
1/16W
MF
402 2

R9099

R9060

Y9000

27PF

NO STUFF

CRITICAL

C9028
1

AVDD0
AVDD1
AVDD2
AVDD3
AVDD4

31
2

5%
50V
CERM
603

R9022 1

FLAS

30

27PF
1

22
22
22

FW_DATA<0>
FW_DATA<1>
FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<6>
FW_DATA<7>

R9001
RP9000
RP9000

22

22

22
22

22

22
22

22

FW_CLK98M_PCLK_R
FW_CTL_R<0>
FW_CTL_R<1>

RP9000
RP9001
RP9001
RP9001
RP9001
RP9002
RP9002
RP9002

63
3
4

FW_DATA_R<0>
FW_DATA_R<1>
FW_DATA_R<2>
FW_DATA_R<3>
FW_DATA_R<4>
FW_DATA_R<5>
FW_DATA_R<6>
FW_DATA_R<7>

5
6
8
9
10
11
12
13

NC

15

OMIT

DVDD0
DVDD1
DVDD2
DVDD3
DVDD4

62
2

54

NOT USED WITH 1394-A PHY


1

R9000

88

2K
5%
1/16W
MF
402
88

FW_CLK98M_LCLK

C9034

R9025 1

TP_FW_CLK98M_LCLK
MAKE_BASE=TRUE

510K
5%
1/16W
MF
402

0.1UF
20%
10V
CERM
402

R9024 1
1K
5%
1/16W
MF
402

25

NOSTUFF1

R9023
10K
5%
1/16W
MF
402

56
64

0.47UF
20%
10V
CERM
603

48

NC

36

90

35

90

34

90

33

90

41

90

40

90

39

90

38

90

47

R9015
56.2
1%
1/16W
MF
402

AGND0
AGND1
AGND2
AGND3

R9014
56.2
1%
1/16W
MF
402

R9026

LREQ PULL-DOWN
ENSURES SIGNAL
LOW WHEN LUCENT
PHY POWERS UP

10K

5%
1/16W
MF
2 402

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=8MIL

TPI#

0.47UF
20%
10V
CERM
603

R9010
56.2
1%
1/16W
MF
402

VGND
7

8 WATTS MAX
24 VOLTS

R9009
56.2
1%
1/16W
MF
402

C9000

NC

45

NC

44

NC

10

GND_CHASSIS_FIREWIRE

0.01UF
10%
16V
CERM
402

C9011
100PF
1

2
5%
50V
CERM
402

FW_R0
FW_R1

55

C9005

GND_CHASSIS_FIREWIRE

NC

46

0.01UF
10%
50V
CERM
805

VP

SM

ELECTRICAL_CONSTRAINT_SET
1

22
21
20
2

R9019
2.49K
1%
1/16W
MF
402

58
2

FW_LINKON 88

18

R9018
56.2
1%
1/16W
MF
402

R9016
56.2
1%
1/16W
MF
402

32
49
52
2

53

R9013
56.2
1%
1/16W
MF
402

R9011
56.2
1%
1/16W
MF
402

FW_TPB1

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1
FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1

FW
FW
FW
FW
FW
FW
FW
FW

FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1
FW_TPO1
FW_TPO1
FW_TPI1
FW_TPI1

FW_TPA1P
FW_TPA1N
FW_TPB1P
FW_TPB1N
FW_TPO1P
FW_TPO1N
FW_TPI1P
FW_TPI1N

FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2
FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2

FW
FW
FW
FW
FW
FW
FW
FW

FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2
FW_TPO2
FW_TPO2
FW_TPI2
FW_TPI2

FW_TPA2P
FW_TPA2N
FW_TPB2P
FW_TPB2N
FW_TPO2P
FW_TPO2N
FW_TPI2P
FW_TPI2N

90
90
90
90
6 90
6 90
6 90
6 90

R9020
1

4.7K
5%
1/16W
MF
402

C9021
220PF
5%
25V
CERM
402

R9017
4.99K
1%
1/16W
MF
402

C9019

220PF
5%
25V
CERM
402
2

R9012
4.99K
1%
1/16W
MF
402

FW_PINT
1

C9016

FW_TPA1P
FW_TPA1N
FW_TPB1P
FW_TPB1N
FW_TPA2P
FW_TPA2N
FW_TPB2P
FW_TPB2N

FW_TPB2

DGND0
DGND1
DGND2
DGND3
DGND4

14

C9015

42

1
88 90

1.5AMP-33V
1

27

CNA

FW_LPS

F9000

MIN_NECK_WIDTH=8MIL

D0
D1
D2
D3
D4
D5
D6
D7

C/LKON

26

37

PLLVSS

TPI

17

CPS
TPBIAS0
XI
TPBIAS1
XO
TPBIAS2
PD
TPA0+
SE
TPA0SM
TPB0+
RESET
TPB0ISO
TPA1+
LPS
TPA1LREQ
TPB1+
PLLVDD
TPB1SYSCLK
TPA2+
CTL0
TPA2CTL1
TPB2+
TPB2R0
R1
PC2
PC1
PC0

MIN_NECK_WIDTH=8MIL

VOLTAGE=1.8V
MIN_LINE_WIDTH=10MIL

FW803

C9027

VOLTAGE=1.8V
MIN_LINE_WIDTH=10MIL

90 7

PP1V8_FW_BIAS1
PP1V8_FW_BIAS2

90 7

ENETFW_RESET_L

10

MIN_NECK_WIDTH=10MIL

SOT-363

87

TPI#

F9002

BAV99DW

FW_TPB2N

1
4

PP3V3_FW

FW_TPO1P

165-OHM
SM

390K
5%
1/16W
MF
402

90 6

0.5AMP

D9004
4

90

5%
1/8W
FF
2 1206

5%
1/16W
MF
2 402

2N3904

R9021

100K

Q9051

Q9051_BASE

5%
1/16W
MF
402

F-ST-TH

SYM_VER-1

R9054

NOSTUFF

1206

R9007
2

SM

NOSTUFF
3

R9052
4.7K 2
1

D9004

FW_TPB2P

R9057
0

2N3904
1

NOSTUFF

SOT-363
2

90

Q9052

Q9052_BASE

BAV99DW

FW_TPA2N

SOT-23

NOSTUFF

D9003
4

90

PP3V3_PWRON

FW_TPA2P

NTR4101P
G

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=24V

10%
1W
FF
2512

FWS22

165-OHM
SM

SYM_VER-1

Q9053

Q9053_BASE

BAV99DW

CRITICAL

J9000

FL9000

5%
1/8W
FF
1206

NOSTUFF

5%
1/16W
MF
2 402

R9053

90

1K

R9051

SOT-363

R9055

NOSTUFF

SOT23

D9003

FW_CPS_R

0.1UF
20%
50V
CERM
805

11 59

2.7

NOSTUFF
PP24V_RUN

90

PP3V3_ALL 7

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=24V

C9009

IRF5505
SM

BAV99DW
SOT-363

FW_CPS

SM

Q9050_GATE

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=24V

NOSTUFF

Q9050

3.3K

D9001
3

FW_TPA1P

PP24V_FW

FERR-160-OHM

90 7

R90501

90

NOSTUFF

SOT-363

L9001

R9002

MURS320T3

BAV99DW

PORT 1
514-0202

CRITICAL

D9000

D9001

CONNECTORS

FW_VP

MIN_LINE_WIDTH=30MIL
MIN_NECK_WIDTH=25MIL

90

90 7

PP3V3_FW

PW_LOWPWR SHOULD BE
PULLED DOWN ON SB

FW_XTAL

90
90
90
90
6 90
6 90
6 90
6 90

X_TAL_IN
X_TAL_OUT

15 MIL SPACING
15 MIL SPACING

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

U9000

CRITICAL

BOM OPTION
TABLE_5_ITEM

338S0088

PP3V3_FW

FIREWIRE PHY 802A

90

FIREWIRE PHY

NOTICE OF PROPRIETARY PROPERTY

DVDD BYPASS

AVDD BYPASS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

C9006
10UF
20%
6.3V
CERM
1206

C9035
0.1UF
20%
10V
CERM
402

C9033
0.1UF
20%
10V
CERM
402

C9032
0.1UF
20%
10V
CERM
402

C9031

0.001UF
20%
50V
CERM
402

C9030
0.001UF
20%
50V
CERM
402

C9029
0.001UF
20%
50V
CERM
402

C9007
10UF
20%
6.3V
CERM
1206

C9008
10UF
20%
6.3V
CERM
1206

C9026
0.1UF
20%
10V
CERM
402

C9025
0.1UF
20%
10V
CERM
402

C9023
0.1UF
20%
10V
CERM
402

C9022
0.001UF
20%
50V
CERM
402

C9002
0.001UF
20%
50V
CERM
402

C9001

II NOT TO REPRODUCE OR COPY IT

0.001UF
20%
50V
CERM
402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

90

103

8
ELECTRICAL_CONSTRAINT_SET

7
NET_PHYSICAL_TYPE

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

USB2_0
USB2_0

USB2
USB2

USB2
USB2

USB2_0
USB2_0

USB2_P<0>
USB2_N<0>

USB2_1
USB2_1

USB2
USB2

USB2
USB2

USB2_1
USB2_1

USB2_P<1>
USB2_N<1>

USB2_2
USB2_2

USB2
USB2

USB2
USB2

USB2_2
USB2_2

USB2_P<2>
USB2_N<2>

USB2_3
USB2_3

USB2
USB2

USB2
USB2

USB2_3
USB2_3

USB2_P<3>
USB2_N<3>

USB2_4
USB2_4

USB2
USB2

USB2
USB2

USB2_4
USB2_4

USB2_P<4>
USB2_N<4>

91 92
91 92

91 92
91 92

91 92
91 92

91 94
91 94

91 92
91 92

NEC_CLK30M_XT1
NEC_CLK30M_XT2
NEC_CLK30M_XT2_R

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

USB2_NEC_XTAL

L9135

91
91
91 7

=PP3V3_PWRON_USB

91

PP3V3_PWRON_NEC_AVDD
VOLTAGE=3.3V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil

FERR-EMI-100-OHM
1

2
SM

Net Spacing Type: USB2


mils
mils
mils
mils
mils

C9126

C9127 1

C9128 1

0.1uF

0.1uF

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

0.1uF

20%
10V
CERM 2
402

N10

20%
10V
CERM 2
402

D7

H4

G12

J13

0.1uF

R9100

VDD

20%
10V
CERM 2
402

C9129 1 C9130

20%
10V
CERM 2
402

0.1uF

20%
10V
CERM 2
402

L13

0.1uF

N8

C9124 1 C9125

E2

20%
10V
CERM 2
402

0.1uF

A3

C9123 1

20%
10V
CERM 2
402

0.1uF

A12

C9122 1

20%
10V
CERM 2
402

A13

0.1uF

P12

C9121

C9137

20%
10V
CERM 2
402

N12

0.1uF

20%
6.3V
CERM
805

AVDD

20%
6.3V 2
CERM
805

P3

10uF

P2

C9120

BOM options provided by this page:


(NONE)

C9136

10uF

5%
1/16W
MF
603

Signal aliases required by this page:


(NONE)

Line To Line:
19.5
Length Tolerance:
50
Primary Max Sep:
7.5
Secondary Max Sep: 100
Secondary Length: 500

C9135

D13

Power aliases required by this page:


- _PP3V3_PWRON_USB

4.7

F13

H13

Page Notes

R9135

RSDM1 M14
DM1 M13
DP1 L14
RSDP1 K13

0.1uF

20%
10V
CERM 2
402

CRITICAL

1%
1/16W
MF
402

USB_NEC_N<0>
(USB2_N<0>)
(USB2_P<0>)
USB_NEC_P<0>

U7700

NOTE: Target differential impedance for


USB2 data pairs is 90 ohms.

36

USB2_N<0>
USB2_P<0>

91 92
91 92

R9101
36

1%
1/16W
MF
402

NEC_uPD720101_USB2
FBGA

R9102
36

1
91 7

RP9110

V1.0
NC0 P7
NC1 P8
NC2 R3
NC3 R4
NC4 R5
NC5 R6
NC6 R7
NC7 R8
NC8 T1
NC9 T2
NC10 T3
NC11 T4
NC12 T5
NC13 T6
NC14 T7
NC15 T8
NC16 U1
NC17 U2
NC18 U3
NC19 U4
NC20 U5
NC21 U6
NC22 V1
NC23 V2
NC24 V3
NC25 V4
NC26 W1
NC27 W3
NC28 Y1
NC29 Y3

TP_SB_NC_P7
TP_SB_NC_P8
TP_SB_NC_R3
TP_SB_NC_R4
TP_SB_NC_R5
TP_SB_NC_R6
TP_SB_NC_R7
TP_SB_NC_R8
TP_SB_NC_T1
TP_SB_NC_T2
TP_SB_NC_T3
TP_SB_NC_T4
TP_SB_NC_T5
TP_SB_NC_T6
TP_SB_NC_T7
TP_SB_NC_T8
TP_SB_NC_U1
TP_SB_NC_U2
TP_SB_NC_U3
TP_SB_NC_U4
TP_SB_NC_U5
TP_SB_NC_U6
TP_SB_NC_V1
TP_SB_NC_V2
TP_SB_NC_V3
TP_SB_NC_V4
TP_SB_NC_W1
TP_SB_NC_W3
TP_SB_NC_Y1
TP_SB_NC_Y3

K14

USB_NEC_N<1>

K12

(USB2_N<1>)
(USB2_P<1>)
USB_NEC_P<1>

J14
J12

10K

5%
1/16W
MF
402 1

BGA
(8 OF 8)

RSDM2
DM2
DP2
RSDP2

10K

SHASTA

7 6

R91102

U2300

OMIT

5%
1/16W
SM1

2 3

1%
1/16W
MF
402

92

92

92

94
92

B11 OCI2

92

92

92

92

36

A10 OCI4
B9 OCI5

RSDM3 H11
DM3 G11

C12 PPON1

USB2_PWREN<0>
USB2_PWREN<1>
USB2_PWREN<2>
USB2_PWREN<3>
USB2_PWREN<4>

DP3 G13
RSDP3 G14

A11 PPON2
C11 PPON3

USB_NEC_N<2>
(USB2_N<2>)
(USB2_P<2>)
USB_NEC_P<2>

C10 PPON4

USB2_N<2>
USB2_P<2>

36

R9106

RSDM4
DM4
DP4
RSDP4

=PP3V3_PWRON_USB

6
6

R91401

(USB2_N<3>)
(USB2_P<3>)
USB_NEC_P<3>

E12
E14

R9141
1.5K

5%
1/16W
MF
402 2

USB_NEC_N<3>

F14

1.5K

F12

36

P6 NC1
M6 NC2

36

RSDM5 E13
DM5 D14

91

NEC_CLK30M_XT1
NEC_CLK30M_XT2_R

DP5 C13
RSDP5 C14

L9 XT1/SCLK
P8 XT2

100

NEC_CLK30M_XT2

22pF

5%
50V
CERM 2
402

5%
2 50V
CERM
402

5%
1/16W
MF
603

N11

M12

R9139

P13

D8

F11

G4

22pF

J11

D12

H12

L12

M11

AVSS
B13

N2

N13

B2

VSS
A2

B14

H14

C9146

N14

N1

8X4.5MM-SM
1

B1

C9145

91

2
P10

RREF P11

AVSS(R)

Y9145

USB2_N<4>
USB2_P<4>

91 92
91 92

36

Master: Fizzy

1%
1/16W
MF
402

5%
1/16W
MF
1 402

30.0000M

R9109
1

R9145

91 94

1%
1/16W
MF
402

USB_NEC_N<4>
(USB2_N<4>)
(USB2_P<4>)
USB_NEC_P<4>

CRITICAL

91 94

R9108

91

USB2_N<3>
USB2_P<3>

1%
1/16W
MF
402

NEC_NC1_PU
NEC_NC2_PU

R9107

5%
1/16W
MF
2 402

36

1%
1/16W
MF
402

91 92

1%
1/16W
MF
402

91 7

91 92

R9105
1

A9 PPON5

1%
1/16W
MF
402

91 92

R9104

B10 OCI3

6
92

91 92

1%
1/16W
MF
402

B12 OCI1

(USB2_OC<0>)
(USB2_OC<1>)
(USB2_OC<2>)
(USB2_OC<3>)
(USB2_OC<4>)

36

USB2_OC<0>
USB2_OC<1>
USB2_OC<2>
USB2_OC<3>
USB2_OC<4>

USB2_N<1>
USB2_P<1>

R9103

=PP3V3_PWRON_USB

USB Host Interfaces

NEC_RREF_PD

R91381

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

1%
1/16W
MF
402 2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

Tie to GND at ball N11


II NOT TO REPRODUCE OR COPY IT

GND_NEC_AVSS_R
VOLTAGE=0V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

Y9145 LOAD CAPACITANCE IS 16pF

DRAWING

APPLE COMPUTER INC.

TITLE=FIZZY
ABBREV=DRAWING

DRAWING NUMBER

SHT
NONE

4 17:58:34 2004

REV.

051-6482

SCALE

LAST_MODIFIED=Wed Aug

NOTICE OF PROPRIETARY PROPERTY

9.09K

OF

91
1

103

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

PROVIDED
BY
USB
CONTROLLER

USB2
USB2

USB2_PORT1_F
USB2_PORT1_F

USB2_PORT1_P_F
USB2_PORT1_N_F

USB2
USB2

USB2_PORT2_F
USB2_PORT2_F

USB2_PORT2_P_F
USB2_PORT2_N_F

USB2
USB2

USB2_PORT3_F
USB2_PORT3_F

USB2_PORT3_P_F
USB2_PORT3_N_F

I526
I527

DIFFERENTIAL_PAIR
6 92
6 92

6 92
6 92

6 92
6 92

External USB Ports

Page Notes

L9210

FERR-250-OHM

Power aliases required by this page:


- _PP5V_PWRON_USB
- _PP5V_PWRON_UDASH
- _PP3V3_PWRON_UDASH
- _PP3V3_PWRON_BT

59

PP5V_USB2

USB2_PWREN<1>

ALIAS

91

USB2_PWREN<2>

ALIAS

91

USB2_PWREN<3>

ALIAS

91

USB2_PWREN<4>

ALIAS

PP5V_USB2_PORT1_F
VOLTAGE=5V
MIN_LINE_WIDTH=25MIL

C9211MIN_NECK_WIDTH=10MIL
10uF

10%
2 16V
X5R
1210

SM

C9213 1

0.01uF

0.01uF

20%
16V
CERM 2
402

CRITICAL

J9210

20%
16V
CERM 2
402

USB-UAS25
F-ST-TH
5

PORT 1

C9212 1

L9212
165-OHM

SM
SYM_VER-1

91

USB2_N<0>

ALIAS

USB2_PORT1_N
MAKE_BASE=TRUE

TP_USB2_PWREN<0>
MAKE_BASE=TRUE
TP_USB2_PWREN<1>
MAKE_BASE=TRUE
TP_USB2_PWREN<2>
MAKE_BASE=TRUE
TP_USB2_PWREN<3>
MAKE_BASE=TRUE
TP_USB2_PWREN<4>
MAKE_BASE=TRUE

4
92 6

91

USB2_P<0>

ALIAS

USB2_PORT1_P
MAKE_BASE=TRUE
1

92 6

USB2_PORT1_N_F
USB2_PORT1_P_F

R9210

R9211

15K

NO STUFF

C9214 1

15K

5%
1/16W
MF
402 2

neoBorg Implementation

91

20%
2 6.3V
POLY
SMD

GND_USB2_PORT1
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=20MIL

5%
1/16W
MF
2 402

NOTE: This design does not provide power


control on USB ports 2-4. Rename
USB controller outputs to indicate
single-pin connections.
ALIAS

NOSTUFF

C9210
150uF

L9211

NOTE: USB pairs are NOT constrained on


this page. It is assumed that the
USB Host Controller page will
provide the appropriate constraints
to apply to entire USB D+/D- XNets.

USB2_PWREN<0>

NOSTUFF
1

FERR-250-OHM

BOM options provided by this page:


(NONE)

91

SM

Signal aliases required by this page:


(NONE)
NOTE: This page is expected to contain the
necessary aliases to map the
USB pairs to their appropriate
destinations and/or to properly
terminate unused signals.

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

33pF

VDD
DD+
GND
NO STUFF

C9215

2
3
4

33pF

5%
50V
CERM 2
402

5%
50V
2 CERM
402

514-0199

GND_CHASSIS_USB

MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

L9220

FERR-250-OHM

SM

NOSTUFF
1

C9221MIN_NECK_WIDTH=10MIL
10uF

10%
2 16V
X5R
1210

20%
2 6.3V
POLY
SMD

FERR-250-OHM

PP5V_USB2_PORT2_F
VOLTAGE=5V
MIN_LINE_WIDTH=25MIL

NOSTUFF

C9220
150uF

L9221

7 92

SM

C9222 1

C9223 1

0.01uF

0.01uF

20%
16V
CERM 2
402

L9222
165-OHM

CRITICAL

J9220

20%
16V
CERM 2
402

USB-UAS25
F-ST-TH
5

PORT 2

GND_USB2_PORT2
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=20MIL

SM
SYM_VER-1

91

USB2_N<1>

ALIAS

USB2_PORT2_N
MAKE_BASE=TRUE

4
92 6

91

USB2_P<1>

ALIAS

USB2_PORT2_P
MAKE_BASE=TRUE

R92201

92 6

R9221

15K

USB2_PORT2_N_F
USB2_PORT2_P_F
NO STUFF

C9224 1

15K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

33pF

5%
50V
CERM 2
402

VDD
DD+
GND
NO STUFF

C9225

2
3
4

33pF

10uF

91

NOSTUFF

SM-1

R9200

FERR-250-OHM

160
5%
1/16W
MF
2 603
91

USB2_OC<0>

91

USB2_OC<1>

ALIAS

91

USB2_OC<2>

ALIAS

ALIAS

C9230
150uF

L9231

USB2_N<4>
USB2_P<4>

PP5V_USB2_PORT3_F
VOLTAGE=5V
NOSTUFF MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
1
6

SM

20%
2 6.3V
POLY
SMD

20%
6.3V
CERM 2
805

7 92

91

ALIAS

C9240

FERR-250-OHM

ALIAS
ALIAS

6
6

R9240

10uF

10%
16V
2 X5R
1210

C9241

J9240
53353

M-ST-SM

0.1uF

20%
10V
CERM 2
402

NC
NC
NC
8 NC
10 NC

USB_BT_N
MAKE_BASE=TRUE
USB_BT_P
MAKE_BASE=TRUE
1

C9231

CRITICAL

USB2_OC<4>

514-0199

7
9
1

R9241

15K

15K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

516S0097

SDF9201
STDOFF-197OD-283H-TH
1

SM

GND_USB2_PORT3
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=20MIL

USB_OC
MAKE_BASE=TRUE
1

R9201
300

C9232

0.01uF

C9233

CRITICAL

0.01uF

20%
16V
CERM 2
402

J9230

20%
16V
CERM 2
402

USB-UAS25
F-ST-TH
5

L9232
165-OHM

5%
1/16W
MF
2 603

SM
SYM_VER-1

91

USB2_P<2>

ALIAS

USB2_PORT3_P
MAKE_BASE=TRUE

92 6
92 6

91

USB2_N<2>

ALIAS

USB2_PORT3_N
MAKE_BASE=TRUE
1

R9230

R9231

15K

15K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

USB2_PORT3_P_F
USB2_PORT3_N_F

NO STUFF

C9234 1
33pF

5%
50V
CERM 2
402

VDD
DD+
GND
NO STUFF

C9235

33pF

5%
50V
2 CERM
402

2
3
4

PORT 3

_PP5V_PWRON_USB

_PP3V3_PWRON_BT

L9230

F9200
2AMP-6V

SDF9200

STDOFF-197OD-283H-TH

91

5%
50V
2 CERM
402

GND_CHASSIS_USB

Q37 BlueTooth Connector

USB Device Interfaces

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

514-0199

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

GND_CHASSIS_USB

II NOT TO REPRODUCE OR COPY IT

7 92

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

92

103

Page Notes
Power aliases required by this page:
- _PP3V3_PWRON_MODEM
Spec Load: 0.5 A active, 3 mA auxiliary
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

D
SOFT MODEM IS PLAN OF RECORD
MICRODASH MODEM CONNECTOR LEFT ON FOR DEVELOPMENT PURPOSES ONLY

MicroDash Modem Connector

Q52 Modem Connector

NOSTUFF

SDF9400

SDF9402

STDOFF-4MM-9MMH-TH

STDOFF-4MM-9MMH-TH

CRITICAL

J9401

91

C104A-H9.0

USB2_OC<3>

ALIAS

_PP3V3_PWRON_UDASH

35 F-ST-SM

NC
NC 31

DEVELOPMENT

32 NC

C9400 1
4.7uF

94 7

_PP3V3_PWRON_MODEM

NC

C9450
10UF

20%
6.3V
2 CERM
805

C9451
0.1UF

20%
10V
2 CERM
402

NC
NC 7
NC 9
NC 11
NC 13

94 76 25 6
94 25 6

94 76 25 6

17

22

23

24

25

26

27

28

29

30

NC 33
NC 36

I2S1_BITCLK

20%
10V
CERM 2
402

R94002
10K

5%
1/16W
MF
402 1

NOSTUFF

DEVELOPMENT

R9401
10K

5%
1/16W
MF
2 402

6 25 94
6 25 76 94

6 25 94

34 NC

516S0116

R9402

DEVELOPMENT

10K

5%
1/16W
MF
2 402

J9400
5047

F-ST-SM

1
(+3.3V)
3
(GND)
5
25 6 UDASH_SDOWN
(SDOWN)
Default to Modem On
7
(GND)
9
94 76 25 6 I2S1_DEV_TO_SB_DTI
(RXD)
11
94 25 6 I2S1_SYNC
(GPIO*)
13
(GND)
15
94 25 6 MODEM_RING2SYS_L
(RING*)
MODEM_RING2SYS_L SHOULD BE PULLED UP ON SB
(HOOK)
NC 17
19
(GND)
21
18 6 I2C_UDASH_SCL
(SCL)
23
(GND)
25
(A0)
(SNDIN) NC 27
(SNDOUT) NC 29

5%
1/16W
MF
2 402

I2S1_SYNC
I2S1_DEV_TO_SB_DTI

0.1uF

R9451

MODEM_FC_RGDT

16 NC
18 NC
20

20%
10V
CERM 2
1206

7 94

C9401 1

10K

14

19

I2S1_MCLK

6 25 94

NC 21
I2S1_SB_TO_DEV_DTO
I2S1_RESET_L

_PP3V3_PWRON_MODEM
MODEM_RING2SYS_L

10 NC
12 NC

15

NC
NC

DEVELOPMENT DEVELOPMENT

(+3.3V)
(RST*)
(RTS*)
(DTR*)
(GND)
(TXD*)
(TRXC)
(GND)
(D-)
(D+)
(GND)
(SDA)
(A1)
(+5V)
(+5V)

4
6
8
10
12
14
16
18
20
22
24
26
28
30

UDASH_RESET_L
I2S1_MCLK
I2S1_RESET_L

6 25
6 25 76 94
6 25 94

I2S1_SB_TO_DEV_DTO
I2S1_BITCLK
6
6

6 25 76 94

6 25 94

USB_UDASH_N
MAKE_BASE=TRUE
USB_UDASH_P
MAKE_BASE=TRUE
I2C_UDASH_SDA
UDASH_I2C_A1_PU

USB2_N<3>
USB2_P<3>

ALIAS
ALIAS

91
91

6 18

R94041

_PP5V_PWRON_UDASH

R9403

15K

15K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

516S0121
DEVELOPMENT DEVELOPMENT
1

C9402
0.1uF

20%
2 10V
CERM
402

SDF9401
STDOFF-4MM-9MMH-TH
GND_CHASSIS_MODEM

C9403
10uF

20%
2 6.3V
CERM
1206

RJ11 CONNECTOR
STUFFED AT FATP
SYMBOL USED FOR PLACEMENT

OMIT

J9402
RJ11-HGT27.5
ST-TH

1
2

514-0205

From Intel Mobile Audio/Modem


Daughter Card Specification
Rev 1.0, February 22, 1999
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

MONO_OUT/PC_BEEP
GND
AUXA_RIGHT
AUXA_LEFT
CD_GND
CD_RIGHT
CD_LEFT
GND
3.3Vaux
GND
3.3Vmain
AC97_SDATA_OUT
AC97_RESET#
GND
AC97_MSTRCLK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

AUDIO_PWRON
MONO_PHONE
RESERVED
GND
5Vmain
RESERVED
RESERVED
PRIMARY_DN
5Vd
GND
AC97_SYNC
AC97_SDATA_INB
AC97_SDATA_INA
GND
AC97_BITCLK

Modem Interface

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

94

103

AUDIO CODEC
APPLE P/N 353S0655
MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
VOLTAGE=3.3V

L9500

1000-OHM-200MA
103 102 101 100 7

PP3V3_AUDIO

PPV_3V3_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

96 102

0603

PLACE AT U9500

C9500

19
18

I2S0_RESET_L

PDWN*

11
10

NET_SPACING_TYPE=AUDIO
AUDI2S0OUT
AUDSPDIFOUT

12

NET_SPACING_TYPE=AUDIO

21

NC 20
103 18
103 18

25

103 102

AUD_CODEC_MCLK

17

NET_SPACING_TYPE=AUDIO

R9500
I2S0_DEV_TO_SB_DTI

NET_SPACING_TYPE=AUDIO

NOSTUFF

C9513
4.7PF

+/-0.25PF
50V
C0G 2
402
103 101

AUD_SPDIF_OUT

SCKI
ATEST

DGND

5%
1/16W
MF
402

1
1

NC

R9501
47K

5%
1/16W
MF
2 402

15

25

33

R9502

NET_SPACING_TYPE=AUDIO

33

MBIAS
MINM
MINP
AGND
8

I2S0_SB_TO_DEV_DTO

13
14

10%
2 10V
CERM
805

GND_AUDIO_CODEC

95 96 98 102

AUD_CODEC_IN_L
AUD_CODEC_IN_R

6
25
24

AUD_CODEC_OUT_L
AUD_CODEC_OUT_R

26
4
5

AUD_PCM_VCOM

96
96

98 100
98 100

100

AUD_PCM_REF1
AUD_PCM_REF2

AUD_CODEC_LI_SHDN_L
AUD_PSEUDO_VREF

32
27
28

96
96

AUD_PCM_MBIAS 102
AUD_MICIN_N 102
AUD_MICIN_P 102

29
1

C9504
0.1UF

10%
2 16V
X7R
603

C9506
10UF

C9508

10UF

C9510
10UF

20%
2 16V
ELEC
SM

20%
2 16V
ELEC
SM

20%
2 16V
ELEC
SM

C9507 1

C9509 1

C9511 1

10%
16V
X7R 2
603

10%
16V
X7R 2
603

10%
16V
X7R 2
603

10%
16V
X7R 2
603

0.1UF

0.1UF

C9512
10UF

20%
2 16V
ELEC
SM

C9505 1

5%
1/16W
MF
402
102 98 96 95

C9503
1UF

10%
2 10V
CERM
805

0.1UF

1UF

31

I2C_AUDIO_SCL
I2C_AUDIO_SDA

PCM3052
VQFN
BCK
VINL
LRCK
VINR
DOUT
VOUTL
DOUTS
VOUTR
DIN
VCOM
I2CEN
VREF1
ADR
VREF2
SCL
VREFS
SDA
REFO

I2S0_BITCLK_DELAYED
I2S0_SYNC

C9502

VCC

VDD

C
103 25

23

CRITICAL

22
30

103 25

U9500

1%
1/16W
MF
2 402

10%
2 10V
CERM
805

16

1K

C9501
1UF

20%
6.3V
CERM 2
805

R9503

102

1
1

10UF

0.1UF

GND_AUDIO_CODEC

AUDIO: CODEC

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

95

103

LINE IN PSEUDO-DIFFERENTIAL AMP


AV= 0.49

D
NOSTUFF

C9603
47PF
102 96 95

PP4V5_AUDIO_ANALOG

5%
50V
CERM
402

C9600

R9604

10UF

101

AUD_LI_L

AUD_LI_L1

47K

5%
1/16W
MF
402 2

R9603

0.47UF

100K

AUD_LI_GND

AUD_LI_GNDL1

20.5K2

R9600
165

U9600

V+

MAX4253
UMAX
1

AUD_CODEC_IN_L

95

V-

APPLE P/N 353S0642

AUD_LI_VREFL

1%
1/16W
MF
402

20%
16V
ELEC
SM

1%
1/16W
MF
2 402
96 95

SOT-363
2

R9605

10UF

BAV99DW

1%
1/16W
MF
402

10
2

C9601
101 96

D9600
1

20%
10V
CERM 2
603

1%
1/16W
MF
2 402

10K

CRITICAL

C9602

R9602

AUD_LI_L2

1%
1/16W
MF
402

20%
16V
ELEC
SM

R9607

20.5K2

R9606

AUD_PSEUDO_VREF

10K

1%
1/16W
MF
402
102 98 96 95

GND_AUDIO_CODEC
NOSTUFF

R9601
95

AUD_CODEC_LI_SHDN_L

AUD_CODEC_LI_SHDN_L1

5%
1/16W
MF
402

NOSTUFF

C9606
47PF

102 96 95

PP4V5_AUDIO_ANALOG

5%
50V
CERM
402

C9604

R9609

10UF
101

AUD_LI_R

AUD_LI_R1

20.5K2

R9612
1

AUD_LI_R2

1%
1/16W
MF
402

20%
16V
ELEC
SM

CRITICAL

D9600
BAV99DW

R9608

100K

1%
1/16W
MF
2 402

MAX4253
UMAX

AUD_CODEC_IN_R

B
95

V-

APPLE P/N 353S0642

R9610

10UF
AUD_LI_GND

U9600

V+

101 96

9
3

C9605

10
8

SOT-363
5

10K

1%
1/16W
MF
402

AUD_LI_GNDR1

20.5K2

AUD_LI_VREFR

1%
1/16W
MF
402

20%
16V
ELEC
SM

R9611
96 95

AUD_PSEUDO_VREF

10K

1%
1/16W
MF
402
102 98 96 95

GND_AUDIO_CODEC

AUDIO: LINE INPUT AMP

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

96

103

LINE OUT LOW-PASS FILTER


FC = 37 KHZ, HO = -1.4

R9801
1

14K

1%
1/16W
MF
402

C9800

R9800

10UF

100 95

AUD_CODEC_OUT_L

AUDCODECOUTL

10K

270PF

3.92K2

1%
1/16W
MF
402

20%
16V
ELEC
SM-1

C9801

R9802
AUDCODECOUTL1

1%
1/16W
MF
402

AUD_LOAMP_OUT_L

98

5%
50V
CERM
603

AUD_LOAMP_IN_L_M

98

AUD_LOAMP_IN_L_P

98

CRITICAL
1

C9802
1.5NF

5%
25V
2 CERM
0603
101

R9803

AUD_LO_GND_PRB

14K

1%
1/16W
MF
402

R9804
10K

1%
1/16W
MF
2 402

LINE OUT
GROUND NOISE
CANCELLATION

R9805
10K

102 98 96 95

1%
1/16W
MF
2 402

R9806

GND_AUDIO_CODEC

14K

C9804
1.5NF

C9803

R9807

10UF
AUD_CODEC_OUT_R

AUDCODECOUTR

10K

1%
1/16W
MF
402

20%
16V
ELEC
SM-1

98

AUD_LOAMP_OUT_R

98

270PF

3.92K2

AUDCODECOUTR1

AUD_LOAMP_IN_R_M

C9805

R9808

98

5%
25V
2 CERM
0603

100 95

AUD_LOAMP_IN_R_P

1%
1/16W
MF
402

CRITICAL

1%
1/16W
MF
402

5%
50V
CERM
603

R9809
1

14K

1%
1/16W
MF
402

LINE OUT AMP


APPLE P/N 353S0687
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=5V
PP5V_AUDIO_LOAMP

R9810
102

PP5V_AUDIO_ANALOG

4.7

5%
1/10W
MF
603

C9806
10UF

B
C9807

20%
2 16V
ELEC
SM

GND_AUD_LOAMP_CHGPMP

98 102

10UF

20%
6.3V
CERM 2
805

4.7K

102 98 96 95

5%
1/16W
MF
402

C9812 1

5%
1/16W
MF
402 2

1K

100PF

AUDIO_LO_MUTE_L_F

C9813

13

PVDD

VDDR

VDDL
C1P 2
C1N 4

SHDN*
VSS

ROUT 10

11

AUDIO_LO_MUTE_L

R98151

16

R9816

TO SHASTA GPIO
25

RINRIN+

PVSS

8
7

AUD_LOAMP_IN_R_M
AUD_LOAMP_IN_R_P

MAX9722
QFN

100PF

5%
50V
CERM 2
402

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

R9812
1

C9808
1UF

14

AUD_LO_R

101

C9809

AUD_LOAMP_OUT_R

98

10%
10V
2 CERM
805

AUD_MAX9722_C1N

R9817

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

R9818
1K

1%
1/16W
MF
2 402

R9813
1

10

AUD_LO_GND 101

AUDIO: LINE OUT AMP

1%
1/10W
FF
805

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_MAX9722_PVSS

10%
10V
CERM 2
805

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20%
1 16V
ELEC
SM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

R9814
1

GND_AUD_LOAMP

10

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2
SIZE

1%
1/10W
FF
805

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6482

D
SCALE

NOTICE OF PROPRIETARY PROPERTY

C9811
10UF

1UF
GND_AUD_LOAMP_CHGPMP

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

1UF

10%
10V
2 CERM
805

1%
1/16W
MF
2 402

101

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

1%
1/10W
FF
805

AUD_MAX9722_C1P
1

AUD_LO_L

1%
1/10W
FF
805

1K

C9810

102

14

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

5%
50V
CERM 2
402

GND_AUDIO_CODEC

102 98

NC 17

98

R9811
1

LOUT 12

SGND

98

AUD_LOAMP_OUT_L

U9800

LINLIN+

98

14
15

AUD_LOAMP_IN_L_M
AUD_LOAMP_IN_L_P

PGND

98

98

GND_AUD_LOAMP_CHGPMP

102 98

CRITICAL

OF

98

103

FA000

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

1.5A-24V

PP12V_AUDIO_SPKRAMP

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

SM
2

PP12V_AUDIO_SPKRAMP_F

XWA000
OMIT
SM

DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

FERR-250-OHM

PP12V_AUDIO_SPKRAMP_F2

SPEAKER AMP

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

LA000

APPLE P/N 353S0680

PP12V_AUD_SPKRAMP_PLANE

SM-1

LA005

AUDSAMPINLN

CA005

VDD

10%
16V
X7R
805

AUD_PCM_VCOM

LA007

0.47UF

AUDSAMPINRP

0603

CA016

100PF

1000-OHM-200MA
1

AUD_CODEC_OUT_R

AUDSAMPINRN

25

TIE TO SHASTA GPIO

RA013

AUDIO_SPKR_MUTE_L

47K

5%
1/16W
MF
402

RA0121
4.7K

5%
1/16W
MF
402 2

CA020 1

CA021 1

100PF

100PF

5%
50V
CERM 2
402

C1- 5
OUTR+ 27
OUTR+ 28

SHDN*

THM
AGND PAD

AUD_SPKR_OUTL_N

101

ACM4532
SYM_VER-1

0.1UF

10%
50V
2 X7R
603

NOSTUFF

LA003

180-OHM-1.5A
1

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

AUD_SPKR_OUTR_P

101

0603

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

LA004

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOUTRN

180-OHM-1.5A
1

AUD_SPKR_OUTR_N

101

0603

LA012
800-OHM

ACM4532
SYM_VER-1

CA009
0.47UF

CA014

10%
2 16V
X7R
805

5%
2 25V
CERM
603

CA011
1000PF

5%
2 25V
CERM
603

CA012

1000PF

5%
2 25V
CERM
603

CA013
1000PF

5%
2 25V
CERM
603

APPLE P/N 155S0194

10%
16V
2 X7R
805

0.47UF

CA010
1000PF

5%
50V
CERM 2
402

LA011
800-OHM

CA008

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCSS

101

0603

NOSTUFF

SS 12

PGND

AUD_SPKR_OUTL_P

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

LA002

SOT-363

180-OHM-1.5A

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOURTP

OUTR- 25
OUTR- 26

8 NC

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

LA001

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOUTLN

QFN

100 102

180-OHM-1.5A

2N7002DW

SOT-363

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL

10UF

10%
16V
2 CERM
1210

NOSTUFF

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCPN

14 REG

AUD_MAX9714_VREG

CA023

0603

C1+ 6

MAX9714

QA000

2N7002DW

NC

10%
16V
2 CERM
1210

NOSTUFF

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCPP

QA000

AUDIO_SPKR_MUTE_L_F

AUD_SAMP_SHDN_L 11

2
10%
16V
X7R
805

2 AUDIO_SPKR_MUTE_L_INV

1%
1/16W
MF
402

19 FS1
20 FS2

0.47UF

2
0603

10K

AUD_SAMP_FS1
100 AUD_SAMP_FS2

CA007

RA015
100 PP3V3_AUDIO_SPKR

17 G1
18 G2

100

5%
50V
2 CERM
402

LA008

AUD_SAMP_G1
100 AUD_SAMP_G2
100

10%
16V
X7R
805

U9700

15 INR-

AUD_SAMP_INR_N

OUTL- 29
OUTL- 30

16 INR+

AUD_SAMP_INR_P

CA006

1000-OHM-200MA

CA003
10UF

20%
16V
2 CERM
603

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOUTLP

OUTL+ 31
OUTL+ 32

10 INL+

AUD_SAMP_INL_P

0.1UF

GND_AUDIO_SPKRAMP_PLANE

24

0603

CA019

CHOLD 7

9 INL-

AUD_SAMP_INL_N

23

0.47UF

AUDSAMPINLP

22

1%
1/16W
MF
2 402

21

10K

RA014
4

CA015

5%
2 50V
CERM
402

LA006

1000-OHM-200MA

2
10%
16V
X7R
805

100PF

100

20%
16V
2 CERM
1206

33

AUD_CODEC_OUT_L

CA002
1UF

20%
16V
CERM 2
603

0.47UF

98 95

0.1UF

PP3V3_AUDIO_SPKR

CA004

0603

95

CA018 1

10%
16V
CERM 2
1210

20%
16V 2
ELEC
SM-2

GND_AUDIO_SPKRAMP_PLANE

1000-OHM-200MA
98 95

10UF

220UF

20%
16V 2
ELEC
SM-2
102 100

CA001

CA000 1

220UF

AUD_MAX9714_CHOLD

CA017

SM

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL

XWA003
OMIT

13

B
102 7

GND_AUDIO_SPKRAMP

XWA001
OMIT
SM
1

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL

XCA000
50R28
DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL

XWA002
OMIT
SM
1

GAIN SETTINGS: +19DB


MODULATION SETTING: LOW EMI
102 100

GND_AUDIO_SPKRAMP_PLANE

GAIN AND SWITCHING FREQUENCY STUFF OPTIONS

LA009

1000-OHM-EMI
103 102 101 95 7

PP3V3_AUDIO

MIN_LINE_WIDTH=4MIL
MIN_NECK_WIDTH=4MIL
PP3V3_AUDIO_SPKR_EMI

SM

LA010

1000-OHM-EMI
1

MIN_LINE_WIDTH=4MIL
MIN_NECK_WIDTH=4MIL

PP3V3_AUDIO_SPKR

100

SM
8 7

6 5

CA022 1

RPA000

100PF

47K

5%
50V
CERM 2
402

5%
1/16W
SM1
1 2

3 4

AUDIO: SPEAKER AMP

AUD_SAMP_G1
100 AUD_SAMP_G2
100 AUD_SAMP_FS1
100 AUD_SAMP_FS2

100

NOTICE OF PROPRIETARY PROPERTY

NOSTUFF
1

RA008
0

5%
1/16W
MF
2 402

102 100

RA009
0

5%
1/16W
MF
2 402

NOSTUFF
1

RA010
0

5%
1/16W
MF
2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

NOSTUFF

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

RA011

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5%
1/16W
MF
2 402

SIZE

APPLE COMPUTER INC.

GND_AUDIO_SPKRAMP_PLANE

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

100

103

LINE IN JACK

SPEAKER CABLE CONNECTOR

APPLE P/N 514-0203

APPLE P/N 518-0138

LA100

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L_JACK

AJR23
F-ST-TH
5

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L_EMI

FERR-EMI-100-OHM
1

LA104

SM

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L 96

FERR-EMI-100-OHM
SM

100

LA101

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_JACK

1
3

LA105

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_EMI

FERR-EMI-100-OHM

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL

AUD_LI_R_EMI

AUD_LI_GND_JACK

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL

CA100
100PF

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_GND_EMI

5%
2 50V
CERM
402

CA101
100PF

5%
2 50V
CERM
402

CA102
100PF

CA103

RA113

5%
1/16W
MF
2 402

LA132

1000-OHM-200MA

DZA100

5%
2 50V
CERM
402

AUDIO_GPIO_12

SPEAKER TYPE DETECT


TO SHASTA GPIO

NOSTUFF

100PF

5%
2 50V
CERM
402

14V-15A

CA119

5%
2 25V
CERM
603

CA125
1000PF

5%
2 25V
CERM
603

101 7

LA108

AUDIO_IN_DET0_L = LOW: PLUG INSERTED


AUDIO_IN_DET0_L = HIGH: PLUG NOT INSERTED
102

PP3V3_AUDIO

GND_AUDIO_MIC

RA101
47K

RA100

5%
1/16W
MF
2 402

100K

5%
1/16W
MF
2 402

102

AUDIO_LI_DET_L

GND_AUDIO_MIC_EMI

SM

LA109

LA112

AUD_MIC_IN_P

101

AUD_LI_DET_H

47K

AUDLINDETH

5%
1/16W
MF
402

SM

102

AUD_MIC_IN_N

AUD_MIC_IN_N_EMI

CA120

CA121

1000PF

10%
2 25V
X7R
402

NOSTUFF

CA106
1000PF

5%
25V
2 CERM
603

CA107
1000PF

5%
25V
2 CERM
603

APPLE P/N 518-0034

LINE OUT PLUG DETECTS

MIC CABLE CONNECTOR

AUDIO_LO_DET_L = LOW: PLUG INSERTED


AUDIO_LO_DET_L = HIGH: PLUG NOT INSERTED

10%
2 25V
X7R
402

AUDIO_LO_OPTICAL_PLUG_L = LOW: OPTICAL DIGITAL AUDIO PLUG INSERTED


AUDIO_LO_OPTICAL_PLUG_L = HIGH: ANALOG AUDIO PLUG INSERTED

CA122
1000PF

10%
2 25V
X7R
402

103 102 101 100 95 7

PP3V3_AUDIO

GND_CHASSIS_AUDIO_INTERNAL

RA104

LA122

AUD_SPDIF_OUT_EMI

RA103

5%
1/16W
MF
2 402

100K

SM

47K

FERR-EMI-100-OHM

5%
1/16W
MF
2 402

AUD_SPDIF_OUT_JACK

SM

LA123

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP5V_AUDIO_SPDIF_EMI

101

AUD_LO_DET1

SM

SM

LA124

AUD_LO_R

AUD_LO_DET1_EMI

SM

LA117

LA125

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_R_EMI

CA117
0.1UF

SM

CA118
1UF

10%
2 10V
CERM
805

20%
2 10V
CERM
402

SM

SM

LA126

FERR-EMI-100-OHM

F-ST-TH
9
10

98

AUD_LO_L

FERR-EMI-100-OHM
1

MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL
MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL

SM

AUD_LO_GND_JACK
AUD_LO_DET1_JACK
AUD_LO_R_JACK
AUD_LO_L_JACK

AUD_LO_DET2_JACK

SM

LA119

LA127

FERR-EMI-100-OHM
AUD_LO_DET2

AUD_LO_DET2_EMI

8
SM

98

AUD_LO_GND

LA128

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_GND_EMI

FERR-EMI-100-OHM
2

0.1UF

B
1

RA107

RA106

5%
1/16W
MF
2 402

100K

5%
1/16W
MF
2 402

VIN
VDD

AUDIO_LO_OPTICAL_PLUG_L

GND

RA108
101

AUD_LO_DET2
NOSTUFF

12

RA109

47K

AUD_LO_DET2_1

5%
1/16W
MF
402

2N7002DW
SOT-363

S
1

CA110

20%
2 10V
CERM
402

5%
1/16W
MF
2 402

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_SPDIF_GND

25

QA101

0.1UF

100K

SM

TO SHASTA GPIO

47K

FERR-EMI-100-OHM

SM

CA109

PP3V3_AUDIO

11

LA120

SOT-363

SM

103 102 101 100 95 7

4
2

FERR-EMI-100-OHM

2N7002DW

20%
2 10V
CERM
402

7
101

5%
1/16W
MF
402

JA103

MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL
MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_L_EMI

AUD_LO_DET1_1

6 25

QA101

JFJ8210

LA118

47K

APPLE P/N 514-0204

FERR-EMI-100-OHM
1

RA105
101 AUD_LO_DET1

LINE OUT JACK


1

FERR-EMI-100-OHM

FERR-EMI-100-OHM
98

LA116

FERR-EMI-100-OHM

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP5V_AUDIO_SPDIF_JACK

FERR-EMI-100-OHM

LED

LA115

FERR-EMI-100-OHM

TO SHASTA GPIO
AUDIO_LO_DET_L

PP5V_AUDIO

1000PF

SM

1000PF

FERR-EMI-100-OHM
AUD_SPDIF_OUT

LA113

LA114

CA127

5%
25V
2 CERM
603

HF28
2

SM

101 7

NOSTUFF

CA105

GND_AUDIO_MIC_CONN
AUD_MIC_IN_P_CONN
AUD_MIC_IN_N_CONN

FERR-EMI-100-OHM

0.1UF

5%
25V
2 CERM
603

5%
25V
2 CERM
603

CA108

1000PF

M-ST-TH

SM

20%
10V
2 CERM
402

103 95

AUD_MIC_IN_P_EMI

FERR-EMI-100-OHM

2N7002

LA110

QA100

RA102

CA126

JA102

FERR-EMI-100-OHM

SM

3
D

SM

25

100

2
0603

FERR-EMI-100-OHM

FERR-EMI-100-OHM

TO SHASTA GPIO

AUD_SPKR_OUTL_P_CONN

1000PF

5%
25V
2 CERM
603

GND_CHASSIS_AUDIO_INTERNAL

1
1

AUD_SPKR_OUTL_P

LA134

NOSTUFF

CA104

100

LA111

FERR-EMI-100-OHM
1

NOSTUFF
1

1000PF

GND_CHASSIS_AUDIO_EXTERNAL

LINE IN PLUG DETECT

2
0603

1000PF

0405
2

103 102 101 100 95 7

AUD_SPKR_OUTL_N_CONN

AUD_SPKR_OUTR_N

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL
180-OHM-1.5A

25

102 101 7

SM

GND_CHASSIS_AUDIO_EXTERNAL

101

SM

PP3V3_AUDIO

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_GND 96

FERR-EMI-100-OHM

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL

0603
103 102 101 100 95 7

2
0603

M-ST-TH

47K

LA107

FERR-EMI-100-OHM

102 101 7

AUD_SPKR_OUTL_N

SM

LA103

100

AUD_SPKR_OUTR_N_CONN

10-89-7082

LA131

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_R 96

FERR-EMI-100-OHM

SM

LA133

JA101

AUD_SPKR_OUTR_P_CONN

180-OHM-1.5A

LA106

FERR-EMI-100-OHM

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL
180-OHM-1.5A

0603

SM

LA102

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_R_JACK

AUD_SPKR_OUTR_P

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_H 101

FERR-EMI-100-OHM

SM

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL

LA130

180-OHM-1.5A

AUDIO_GPIO_12_CONN

JA100

RA1121
FERR-EMI-100-OHM
1

AUD_LO_GND_PRB_EMI

SM

PLACE NEAR
J9801

XCA100
50R28

SM

CA111

100PF

100PF

CA124
100PF

5%
2 50V
CERM
402

100PF

5%
50V
2 CERM
402

5%
2 50V
CERM
402

CA113

100PF

5%
50V
2 CERM
402
1

CA112
100PF

CA114
100PF

5%
2 50V
CERM
402

AUD_LI_GND_EMI

5%
50V
2 CERM
402
1

5%
50V
2 CERM
402

PLACE NEAR
J700

AUDIO: Q45 CONNECTORS

XCA101
50R28

DZA101
1

CA116

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

101

101 7

GND_CHASSIS_AUDIO_INTERNAL

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

MMBZ15DLT1

II NOT TO REPRODUCE OR COPY IT

15V

0.01UF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SOT23

10%
16V
2 CERM
402

SIZE

APPLE COMPUTER INC.

GND_CHASSIS_AUDIO_EXTERNAL

DRAWING NUMBER

SHT
NONE

REV.

051-6482

D
SCALE

NOTICE OF PROPRIETARY PROPERTY

CA115

CA123

102 101 7

AUD_LO_GND_PRB

5%
1/16W
MF
402 2

FERR-EMI-100-OHM

98

LA129

LA121

OF

101

C
103

RA226

RA227

5%
1/16W
MF
402

5V POWER SUPPLY FOR THE HEADPHONES/LINE OUT AMP

NET_SPACING_TYPE=AUDIO
I2S0_BITCLK_8NS_DELAY
ELECTRICAL_CONSTRAINT_SET=8NS

UNUSED GPIO TERMINATIONS

5%
1/16W
MF
402

NOSTUFF

RA225
103 25

APPLE P/N 353S0539

DIFFERENTIAL_PAIR=AUD_CODEC_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

LA200

PP12V_AUDIO_CODEC

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

VRA200

RA200

FERR-250-OHM
7

CRITICAL

AUD_12V_CODEC

SM-1

10

I2S0_BITCLK

103 102 101 100 95 7

I2S0_BITCLK_DELAYED

5%
1/16W
MF
402

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=5V

RA228

5%
1W
FF
2512

PP5V_AUDIO_ANALOG

IN

CA200

1UF

CA201
220UF

20%
16V
2 CERM
1206

20%
2 16V
ELEC
SM-2

CA209
220UF

25

AUDIO_HP_DET_L

CA203

RA216

100UF

20%
2 16V
ELEC
SM

100

GND_AUDIO_SPKRAMP_PLANE

GND_AUDIO_CODEC

634

1%
1/16W
MF
402 2

25

AUDIO_SPKR_DET_L

GND_AUDIO_SPKRAMP

25

I2S2_DEV_TO_SB_DTI

47K

5%
1/16W
MF
402

5%
1/10W
FF
805

4.5V POWER SUPPLY FOR CODEC AND LINE IN AMP

47K

RA209

NOSTUFF

RA217
100 7

5%
1/16W
MF
402

PLACE NEAR ENTRY TO SPEAKER


AMP GROUND PLANE

47K

RA208

95 96 98 102

5%
1/10W
FF
805

GND_AUDIO_CODEC

RA210
103 25

AUDIO_GPIO_11

APPLE P/N 353S0733

5%
1/16W
MF
402

NOSTUFF

RA202

20%
16V 2
ELEC
SM

47K

RA207

100UF

AUDIO_LI_OPTICAL_PLUG_L

5%
1/16W
MF
402

PLACE ACROSS GROUND SPLIT


AT RIGHT SIDE OF CA007

AUD_V5_REF
FC=7HZ

CA202 1

25

98 102

RA2011
1%
1/16W
MF
402 2

20%
2 16V
ELEC
SM-2

RA206

5%
1/16W
MF
2 402

SOT223-4

VOUT 4
OUT 2
ADJ/GND

95

LM1117
3

AUD_12V_CODEC2

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP3V3_AUDIO

NOSTUFF

205

102 98 96 95

NET_SPACING_TYPE=AUDIO

47K

5%
1/16W
MF
402

CRITICAL

VRA201
MAX8510-4.5V
SC70-5
102 98

PP5V_AUDIO_ANALOG

RA2031

103 102 101 100 95 7

BP 4

100K 2

102 98 96 95

CA204
10UF

AUD_4V5_FB
1

CA205
0.1UF

20%
6.3V
2 CERM
805

NOT USED: C9906

10%
16V
2 X7R
603

CA207

10%
2 10V
CERM
805

RA212

5%
1/10W
MF
603

1UF

GND_AUDIO_CODEC

47K

5%
1/16W
MF
402

RA205

CA206

AUD_4V5_SHDN*

I2S2_BITCLK

95 96

10%
16V
2 CERM
402

GND

RA211
25

PP4V5_AUDIO_ANALOG

0.01UF

1%
1/16W
MF
402

102 98 96 95

SHDN*

1%
1/16W
MF
402 2

RA204
PP3V3_AUDIO

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

OUT 5

IN

100K

NOSTUFF

PLACE ACROSS GROUND SPLIT


AT CODEC U9500

25

I2S2_SYNC

47K

5%
1/16W
MF
402

CA208
10UF

RA213

20%
2 16V
ELEC
SM-1

PLACE AT J5903

25

AUDIO_HP_MUTE_L

RA229

GND_AUDIO_CODEC
101 7

GND_CHASSIS_AUDIO_EXTERNAL

47K

5%
1/16W
MF
402

RA214

5%
1/10W
FF
805

25

AUDIO_EXT_MCLK_SEL

47K

5%
1/16W
MF
402

RA215
25

I2S2_RESET_L

47K

5%
1/16W
MF
402

MICROPHONE IMPEDANCE MATCHING CIRCUIT


AUDIO GROUND RETURNS
DIFFERENTIAL_PAIR=AUD_CODEC_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=12MIL
7

AUD_PCM_MBIAS

95

NOSTUFF
25

XWA200
OMIT
SM

GND_AUDIO

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V
GND_AUDIO_CODEC

10UF

XWA202
OMIT

GND_AUDIO_MIC
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

101

GND_AUD_LOAMP

CA212

98

165

1%
1/16W
MF
402

SM

XWA203
OMIT
SM

XCA201
50R28

DIFFERENTIAL_PAIR=AUDIO_MIC
NET_SPACING_TYPE=AUDIO

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V
101

GND_AUD_LOAMP_CHGPMP

NOSTUFF
1

RA221

165

1%
1/16W
MF
402

AUD_CODEC_MCLK

100K
1%
1/16W
MF
402 2

DIFFERENTIAL_PAIR=AUDIO_MIC_1
NET_SPACING_TYPE=AUDIO

DIFFERENTIAL_PAIR=AUDIO_MIC_2
NET_SPACING_TYPE=AUDIO
AUD_MICIN_P 95

0.1UF
1

RA224

NOTICE OF PROPRIETARY PROPERTY

DIFFERENTIAL_PAIR=AUDIO_MIC_2
NET_SPACING_TYPE=AUDIO
AUD_MICIN_N 95

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

10%
16V
X7R
603

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

1K

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1%
1/16W
MF
2 402

SIZE

GND_AUDIO_MIC

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6482

SCALE

95 103

AUDIO: Q45 POWER SUPPLIES

CA214

AUD_MIC_M1

1%
1/16W
MF
2 402

25

95 96 98 102

10%
16V
X7R
603

RA2221

1K

102 101

0.1UF

AUD_MIC_P1

RA220
1

AUD_MIC_IN_N

98

I2S2_MCLK

CA211

GND_AUDIO_CODEC

CA213

DIFFERENTIAL_PAIR=AUDIO_MIC_1
NET_SPACING_TYPE=AUDIO

1000PF

10%
25V 2
X7R
402

I116

25

1%
1/16W
MF
2 402

RA219

AUD_MIC_IN_P

MAKE_BASE=TRUE
I2S0_MCLK

I2S2_SB_TO_DEV_DTO

20%
2 16V
ELEC
SM-1

1K

1%
1/16W
MF
2 402

DIFFERENTIAL_PAIR=AUDIO_MIC
NET_SPACING_TYPE=AUDIO

I89

RA223

1K

101 102

MAKE_BASE=TRUE
TP_I2S2_MCLK

RA218

MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=6MIL
VOLTAGE=4.5V

I88

10UF

20%
6.3V
2 CERM
805

95 96 98 102

NOSTUFF

XWA201
OMIT
SM

CA210

MAKE_BASE=TRUE
TP_I2S2_SB_TO_DEV_DTO

OF

102

103

S/PDIF TRANSMITTER
I2C ADDRESS = 0010 000X
APPLE P/N 353S0597

NOSTUFF

LA300

1000-OHM-200MA
102 101 100 95 7

PP3V3_AUDIO

NOSTUFF

MIN_LINE_WIDTH=15MIL
MIN_NECK_WIDTH=10MIL
PP3V3_AUDIO_CS8406

0603

CA300 1

NOSTUFF

10UF

20%
6.3V
CERM 2
805

NOSTUFF

CA301

1UF

CA302

1UF

10%
10V
2 CERM
805

10%
10V
2 CERM
805

NOSTUFF

UA300
6
VD
102 95

95 25
102 25

AUD_CODEC_MCLK

21 OMCK

I2S0_SYNC
I2S0_BITCLK

12
13

23
VL

ILRCLK
ISCLK

USER
TEST18

18

TEST20
USER

20

CS8406
95 25

14

I2S0_SB_TO_DEV_DTO

SDIN

TSSOP

26
TXP
25
TXN

95 18
95 18

28

I2C_AUDIO_SCL
I2C_AUDIO_SDA

2
27
3

102 25

ORIG
SCL/CCLK
COPY/C
SDA/CDOUT

TEST2
AD0/CS
TEST27
AD1/CDIN
EMPH*
AD2

AUDIO_GPIO_11

24

RST*
H_S*

SFMT0
RXP

SFMT1
DGND

C EN
TEST16

16

VALIDITY
TEST17

17

AUDIO*
INT

10

TCBLD
TEST11

11
15

AUD_CS8406_INT

NET_SPACING_TYPE=AUDIO
AUD_SPDIF_OUT 95

101

MAKE_BASE=TRUE
TP_AUD_CS8406_INT

AUD_CS8406_TCBL
NOSTUFF
1

22

33

5%
1/16W
MF
402

I87

TEST7

NC

19

APMS
TEST10

TEST8

RA301

AUD_CS8406_USERBIT

TCBL

DGND

NOSTUFF
NET_SPACING_TYPE=AUDIO
AUD_CS8406_TXP

RA300
47K

5%
1/16W
MF
2 402

NOSTUFF
1

RA302
47K

5%
1/16W
MF
2 402

AUDIO: S/PDIF XMITTER

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6482

OF

103

103

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