Xilinx Spartan3 Device Reliability

Device Reliability Report
First Quarter 2012
UG116 (v9.0) May 8, 2012
Copyright 20042012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Notice of Disclaimer The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be failsafe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.
Reliability Report
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UG116 (v9.0) May 8, 2012
Revision History
The following table shows the revision history for this document.
Date 02/09/04 05/10/04 05/24/04 05/24/04 08/18/04 01/04/05 03/01/05 05/20/05 08/19/05 11/17/05 02/24/06 05/05/06 06/20/06 08/11/06 08/29/06 10/06/06 12/01/06 02/12/07 02/20/07 03/28/07 06/04/07 08/24/07 09/18/07 10/31/07 02/06/08 07/07/08 08/15/08 11/14/08 02/11/09 Version 1.0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.0.1 3.1 3.1.1 3.1.2 3.2 3.3 3.3.1 3.3.2 4.0 4.1 4.1.1 4.2 4.3 5.0 5.1 5.2 5.3 Initial release in new template. First quarter 2004 revision. Changed fit rate on page 7 for 0.5 m from 89 to 8. Changes to Tables 1-1, 2-1, 2-15, 3-44, 3-46, 3-48, 3-50, and 3-52; also a heading on page 75. Added second quarter data. Added third quarter data. Changes in most tables to show the fourth-quarter test values. Removed packaging information from Chapter 1 and added a reference to the packaging website. Data corrections in tables 2-61 and 3-32. Changes in most tables to show the second-quarter test values. Updates most tables to include the third-quarter test data. Most tables updated to reflect the fourth-quarter test data. Changes in most tables to show the first-quarter test data. Corrected two transposed figures in Table 1-10. Changes in most tables to show the second-quarter test data. Changed typos in tables 2-91, 3-44, and 3-55. Corrected values in tables 1-12, 2-87, 2-90, and 2-91. Changes in most tables to show the third-quarter test data. Changes in most tables to show the fourth-quarter test data. Correct typos in three tables. Correct typos in four tables. Changes in most tables to show the first-quarter test data. Changes in most tables to show the second-quarter test data. Corrected omission in this history table. Changes in most tables to show the third-quarter test data. Changes in most tables to show the fourth-quarter test data. Changes in most tables to show the first-quarter test data. Changes in most tables to show the second-quarter test data. Changes in most tables to show the third-quarter test data. Updated legal disclaimer. Changes in most tables to show the fourth-quarter test data. Added single event upset and soft error rate data. See Table 1-17, page 23. Revision
UG116 (v9.0) May 8, 2012
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Reliability Report
Date 05/07/09 06/15/09 08/03/09 10/27/09 03/15/10 05/04/10 08/10/10 11/01/10 02/01/11 05/09/11 06/17/11 08/02/11 11/07/11
Version 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 6.0 6.0.1 7.0 8.0
Revision Changes in most tables to show the first-quarter, 2009 test data. Added second paragraph to SEU and Soft Error Rate Measurements, page 23. Added SF363 (Lot 2) data to Table 3-77, page 111. Replaced Figure 3-1, page 112, Figure 3-2, page 112, and Figure 3-3, page 113. Revised FFG1704 data in Table 3-79, page 117 Changes in most tables to show the second-quarter, 2009 test data. Added alpha particle FIT/Mb data for Spartan-6 and Virtex-6 FPGAs to Table 1-17, page 23. Most tables updated to include third-quarter, 2009 test data. Changes in most tables to show the fourth-quarter, 2009 test data. Changes in most tables to show the first-quarter, 2010 test data. Changes in most tables to show the second-quarter, 2010 test data. Changes in most tables to show the third-quarter, 2010 test data. Changes in most tables to show the fourth-quarter, 2010 test data. Changes in most tables to show the first-quarter, 2011 test data. Revised last sentence in SEU and Soft Error Rate Measurements for clarity. Changes in most tables to show the second-quarter, 2011 test data. Changes in most tables to show the third-quarter, 2011 test data. Chapter 1, The Reliability Program: Updated Acceptance Criteria and added note 3 to Table 1-3. Chapter 2, Results by Product Family: Added XCV600E to Table 2-12. Added XC2VP7 to and deleted XC2VP80 from Table 2-15. Deleted XC3S2000 from Table 2-18. Deleted XC4VLX15 from Table 2-24. Added XC6VLX130T to Table 2-28. Added XC4VLX80 to Table 2-45. Added XC2V6000 to Table 2-81. Deleted XC4VFX100 and XC4VLX85T from Table 2-89. Added XC5VLX330T device to Table 2-90. Added XC6VLX195T device to Table 2-91. Added XC6SLX25T to Table 2-104. Added XCV100 to Table 2-128. Added XC6SLX16 to Table 2-141. Added XC4VLX80 to Table 2-142. Deleted XC17S150XL from Table 2-152. Deleted XCF128X from Table 2-154. Deleted XC17S30XL from Table 2-158. Deleted XCF01S, XCF04S, XCF08P, and XCF128X from Table 2-161. Deleted XC17S30XL from Table 2-170. Deleted XC17V16 from Table 2-171. Deleted XC17S30XL from Table 2-176. Deleted XC17V16 from Table 2-177. Deleted XCF01S, XCF04S, XCF08P, and XCF128X from Table 2-179. Deleted XC95216 from Table 2-181. Added XCR3256XL and deleted XCR384XL and XCR3512XL from Table 2-199. Added XCR3256XL and deleted XCR384XL and XCR3512XL from Table 2-208. Added XCR3256XL and deleted XCR3128XL XCR3512XL from Table 2-220. Chapter 3, Results by Package Type: Added HASTU to Table 3-11. Deleted HTS from Table 3-12. Deleted HASTU from Table 3-15. Deleted Temperature cycling 40 to +125C row from Table 3-26. Added HASTU to Table 3-29. Added HTS to Table 3-43. Added HAST to Table 3-47. Added Temperature cycling -55 to +125C row and HTS to Table 3-49. Added HTS to Table 3-66. Added Temperature humidity 85C, 85% RH with bias row to Table 3-75.
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UG116 (v9.0) May 8, 2012
Date 01/27/12
Version 8.1
Revision Updated Notice of Disclaimer. Changes in most tables to show the fourth-quarter, 2011 test data. Chapter 1, The Reliability Program: Added XCE6VxXxxx to Table 1-7. Added XC5VSX240T to Table 1-12. Chapter 2, Results by Product Family: Added XCE6VxXxxx to Table 2-1. Deleted XC2S150 from Table 2-8. Added XCV100 to Table 2-9. Added XC6SLX45 and XC6SLX100 to and deleted XC6SLX16 from Table 2-23. Added XC4VLX160 and XC4VFX12 and modified Note 1 in Table 2-24. Added Note 1 to Table 2-25 and Table 2-26. Inserted new table: Table 2-29. Added XC5VLX85T to table Table 2-46. Added XC6VLX365T to Table 2-47. Added XCS20XL to and deleted XCS10XL from Table 2-74. Added XC3S200AN to Table 2-87. Added XC6SLX4 to Table 2-88. Added XC2S100E to and deleted XC2S400E from Table 2-97. Added XCS20XL and XCSxxxX to Table 2-109. Added XC6SLX4 and XC6SLX9 to Table 2-121. Deleted XCR3064XL from Table 2-184. Added XC2C64 to Table 2-200. Added XCR3128XL to Table 2-220. Added XC2C64 to Table 2-221. Chapter 3, Results by Package Type: Added HTS to Table 3-3 and Table 3-47. Added HAST to Table 3-56.
05/08/12
9.0
Changes in many tables to show the first-quarter, 2012 test data. Added Xilinx 7 series FPGAs.
UG116 (v9.0) May 8, 2012
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Reliability Report
Reliability Report
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UG116 (v9.0) May 8, 2012
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 1: The Reliability Program

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
The Reliability Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Product Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Wafer Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Non-Hermetic and Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Package/Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reliability Monitor Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Wafer Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package/Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Process Technology Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD and Latch-up Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Rate Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Rate Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SEU and Soft Error Rate Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 16 21 22 23
Chapter 2: Results by Product Family

FPGA Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High-Temperature Operating Life (HTOL) Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Humidity with Bias Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Humidity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Cycling Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autoclave Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Accelerated Stress Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unbiased High Accelerated Stress Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Temperature Storage Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 26 35 35 36 40 40 40 43 43 44 52 52 52 53 53 53 55 55 56 59 59 60
Reliability Report UG116 (v9.0) May 8, 2012
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Flash PROM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

HTOL Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Humidity with Bias Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Humidity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Cycling Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autoclave Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Accelerated Stress Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unbiased High Accelerated Stress Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program/Erase Endurance Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Qualification Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Retention Bake Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HTOL Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Humidity with Bias Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Humidity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Cycling Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autoclave Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unbiased High Accelerated Stress Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program/Erase Endurance Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Qualification Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Retention Bake Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 65 65 66 66 66 67 67 67 68 68 68 69 69 69 70 70 70 71 71 71 72 72 72 72 73 74 74 74 76 76 76 77 77 77 78 78 78 79 79 80 80 80 80 81 81 82 82 83
CPLD Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Chapter 3: Results by Package Type

Reliability Data for Non-Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VO20 and VO48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC44, PC84, and PC20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQ100, PQ160, PQ208, PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQ100, TQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VQ44, VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HQ208, HQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BG352, BG432, BG560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FS48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG324, FG456, FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG680 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG1156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FT256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF668 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF484, FF784 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1136, FF1148, FF1152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1923 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1513, FF1517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1704 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1759, FF1760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF363 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability Data for PGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability Data for CB Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability Data for DD8 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability Data for Chip Scale CC44 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability Data for CF1144 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability Data for CG717 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 85 85 86 86 86 87 87 88 88 88 89 89 89 89 90 90 90 90 91 91 91 91 92 92 92 93 93 93 94 94 94 94 96 97 98 99 99
Reliability Data for Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Reliability Data for Pb-Free Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PDG8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 BGG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 BGG352, BGG432, BGG560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CPG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CPG196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CSG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 CSG280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 CSG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 CSG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 FGG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 FGG320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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FGG400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FGG324, FGG456, and FGG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FGG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FGG680 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FGG900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FGG1156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQG160, PQG208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HQG240, HQG208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCG44, PCG84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOG20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VQG44, VQG64, VQG100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VOG20, VOG48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQG100, TQG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG668 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG484, FFG784 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG1136, FFG1148, FFG1152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG1759, FFG1760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG1156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG1923 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG1513, FFG1517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG1704 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFG1738 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFG363 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102 102 103 103 103 104 104 104 105 105 105 105 106 106 106 107 107 107 107 108 108 108 108 109 109 109
Board-Level Reliability Tests, SnPb Eutectic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

FG676, FG680, FG900, FG1156, BF957, FF672, FF896, FF1152, FF1704, SF363, and CF1144 . . . . . . 110 Mother Board Design and Assembly Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Weibull Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Board-Level Reliability Tests, Pb-Free . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

FGG676, FFG1152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Mother Board Design and Assembly Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Weibull Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Chapter 1
The Reliability Program

Overview
Xilinx publishes this report to provide customers with insight regarding the reliability of Xilinx products. Reliability is defined as product performance to specification over time in response to varied (specified) environmental stress conditions. The goal of the reliability program is to achieve continuous improvement in the robustness of each product being evaluated. As part of this program, finished product reliability is measured periodically to ensure that the product performance meets or exceeds reliability specifications. Reliability programs are executed in response to internal programs.
The Reliability Program

The reliability qualifications of new devices, wafer processes, and packages are designed to ensure that Xilinx products satisfy internal requirements before transfer into production. The reliability qualification and monitoring requirements are outlined in Table 1-1 through Table 1-16. The reliability stress tests are conducted according to the conditions specified in JEDEC Solid State Technology Association s reliability test methods for packaged devices, JESD22, except Group B and D tests in which it follows DSCC test methods, MIL-STD-883.
Product Qualification
Wafer Process
The reliability tests used for wafer process qualification are summarized in Table 1-1. Table 1-1: Wafer Process Qualification Tests
Reliability Test Conditions Duration Lot Quantity Sample Size Acceptance per Lot Criteria
High-temperature operating life (HTOL) THB(3) or High-accelerated stress test (HAST)(3)
TJ > 125C, VDD Max 85C, 85% RH, VDD 130C, 85% RH, VDD
110C, 85% RH, VDD
1,000 hours 1,000 hours 96 hours

264 hours
77
200 FIT(1) 50 FIT(2)
25
0 failures
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Table 1-1:
Wafer Process Qualification Tests (Contd)

Reliability Test Conditions Duration Lot Quantity Sample Size Acceptance per Lot Criteria
Temperature humidity (TH)(3) or Unbiased high accelerated stress test (HASTU)(3)
85C, 85% RH 130C, 85% RH 110C, 85% RH 65C to +150C
1,000 hours 96 hours 264 hours 500 cycles 1,000 cycles 1,000 cycles 1,000 hours 10,000 cycles 3 1 25 32 0 failures 0 failures 3 25 0 failures 3 25 0 failures
Temperature cycling (TC)(3,4,5,6)
55C to+125C 40C to +125C
Data Retention Bake(7) or High Temperature Storage (HTS) Program Erase(8)
TA = 150C TA = 25C
Notes: 1. Phase I production is released as the qualification data demonstrates, meeting the required 200 FIT failure rate and other test
requirements. 2. Phase II production is released as the qualification data demonstrates, meeting the required 50 FIT failure rate and other test requirements. 3. Package preconditioning is performed prior to THB, HAST, temperature cycling, TH, and HASTU tests. 4. For plastic QFP packages: 65C to +150C and 500 cycles or 55C to +125C and 1,000 cycles. 5. For plastic BGA packages: 55C to +125C and 1,000 cycles. 6. For flip chip packages: 55C to +125C and 1,000 cycles or 40C to +125C and 1,000 cycles. 7. For CPLD and EPROM products. 8. This is not a mandatory test and only for CPLD and EPROM products.
Non-Hermetic and Hermetic Packages

Moisture sensitivity and reflow temperature information can be found in UG112, Device Package User Guide.
Package/Assembly
The non-hermetic package/assembly qualification is outlined in Table 1-2. However, for hermetic package qualification, a full group B and D test per MIL-STD-833, Test Methods, is required. Table 1-2: Non-Hermetic Package/Assembly Qualification
Reliability Test Conditions 85C, 85% RH, VDD 130C, 85% RH, VDD 110C, 85% RH, VDD Duration 1,000 hours 96 hours 264 hours 3 25 0 failures Lot Quantity Sample Acceptance Size Criteria per Lot
THB(1) or HAST(1)
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Reliability Monitor Program
Table 1-2:
Non-Hermetic Package/Assembly Qualification (Contd)

Reliability Test Conditions 65C to +150C Duration 500 cycles, 1,000 cycles 1,000 cycles 96 hours 1,000 hours 96 hours or 264 hours 1,000 hours 3 25 0 failures 3 25 0 failures 3 25 0 failures Lot Quantity Sample Acceptance Size Criteria per Lot
Temperature cycling(1,2,3,4)
55C to +125C 40C to +125C
Autoclave(1) or Temperature humidity unbiased(1) or HASTU(1) High-Temperature Storage (HTS)

Notes:
1. 2. 3. 4.
121C, 100% RH 85C, 85% R.H 130C, 85% RH or 110C, 85% RH TA=150C
Package preconditioning is performed prior to THB, HAST, temperature cycling, autoclave, TH, and HASTU tests. For plastic BGA packages: 55C to +125C and 1,000 cycles. For flip chip packages: 55C to +125C and 1,000 cycles or 40C to +125C and 1,000 cycles. For plastic QFP packages: 65C to +150C and 500 cycles or 55C to +125C and 1,000 cycles.
Device
The qualification process for new devices is shown in Table 1-3. Table 1-3:
Reliability Test ESD ESD Latch-up Notes:
1. HBM = Human Body Model 2. CDM = Charge Device Model 3. GT transceiver CDM level is specified per JEP157
Device Qualification
Conditions HBM(1) CDM(2) Current injection Lot Quantity 1 1 1 Sample Size per Lot 3 3 3 Acceptance Criteria 1,000V 250V(3) 200 mA
Reliability Monitor Program

Wafer Process
The wafer process reliability monitor program is based on the maturity of the wafer process, the number of device hours, and the FIT rate. All processes are divided into one of two classes to determine how often the process is monitored annually. Class 1 processes are monitored every quarter; Class 2 processes are monitored every other quarter. FIT Rate calculations for both classes are based on approximately one million device hours (at TJ = 125C) per fab if the data is available. Processes that are four years old or less are
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monitored every quarter regardless of the FIT rate. Mature processes older than four years are monitored based on the FIT Rate. Table 1-4 summarizes the classification criteria and monitoring frequency for both classes. Table 1-4: Monitoring Process Classes
Class 1 Process Age < 4 years Classification Criteria or FIT > 26 (for FPGAs) FIT > 55 (for Flash PROM) 4 times per year Class 2 Process Age > 4 years and FIT < 26 (for FPGAs) FIT < 55 (for Flash PROMs) 2 times per year
Monitor Frequency
The reliability tests used to monitor the wafer process are shown in Table 1-5. Table 1-5: Tests Used to Monitor Wafer Processes
Reliability Test HTOL Data Retention Bake(1) Note:
1. For CPLD and PROM products.
Condition Tj > 125C, VDD Max TA = 150C
Duration 1,000 hours 1,000 hours
Lot Quantity 1 1
Sample Size per Process per Family per Quarter 45 45
Package/Assembly
The package reliability monitor program takes into consideration the following factors: Package construction (wire-bond lead frame, wire-bond BGA, or flip chip) Factory location (assembly site, or wafer fabrication site) Substrate vendor Die size Technology maturity Past history
Based on these factors and availability, representative packages are drawn from inventory for the stress tests defined in Table 1-6. These tests are typically conducted on a quarterly basis, but the number of tests can be reduced or eliminated based on the maturity of the package technology, understanding of failure mechanisms, and their dependency on the stress test. Table 1-6: Tests Used by the Reliability Package Monitor Program
Reliability Test THB(1) or HAST(1) Stress Conditions 85C, 85% RH, VDD 130C, 85% RH, VDD 110C, 85% RH, VDD Stress Duration 1,000 hrs 96 hrs 264 hrs 45 Sample Size Frequency WBLF(2) Every Even Quarter WBBGA(3) Every Odd Quarter Flip Chip(4) Every Quarter
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Process Technology Family
Table 1-6:
Tests Used by the Reliability Package Monitor Program (Contd)

Reliability Test Stress Conditions Stress Duration Sample Size Frequency
Temperature cycling(1, 5)
Autoclave(1, 6) or
55C to +125C or 40C to +125C 121C, 100% RH 85C, 85% RH 130C, 85% RH or 110C, 85% RH TA=150C
1,000 cycles
45
WBLF Every Quarter WBBGA Every Quarter Flip Chip Every Quarter
96 hrs 1,000 hrs 96 hrs or 264 hrs 1,000 hrs 45 WBLF Every Quarter WBBGA Every Quarter 45 WBLF Every Odd Quarter WBBGA Every Even Quarter
Temperature humidity unbiased(1, 6) or HASTU(1, 6) HTS(7)

Notes:
1. 2. 3. 4. 5.
Package preconditioning is performed prior to THB, HAST, temperature cycling, autoclave, TH, and HASTU tests. For matured WBLF packages (PLCCs, SOICs, and DIPs packages), reliability monitoring is performed once a year. For matured WBBGA packages (S-BGA Cavity-down BGA), reliability monitoring is performed once a year. For flip chip packages, THB testing is performed every quarter and replaces the need for temperature humidity testing. For plastic QFP and BGA packages: 55C to +125C and 1,000 cycles; for flip chip packages: 55C to +125C and 1,000 cycles or 40C/+125C and 1,000 cycles. 6. Refer to the device-specific qualification report for complete autoclave, temperature humidity, and HASTU reliability test data. 7. HTS stress is not applicable with flip chip package because the technology has no wire-bond IMC interface degradation.
Process Technology Family

Table 1-7: Wafer Process Technology Family
Process Technology
0.028 m 0.040 m Device
7 series FPGAs XC6VxXxxx, XCE6VxXxxx XC6Sxxx

XC5VxXxxx, XCE5VxXxxx XC3Sxxx, XC3SxxxA, XC3SxxxAN, XC3SxxxE,XC3SDxxxA, XC4VxXxxx, XCE4VxXxxx XC2VPxxx, XCE2VPxxx XC2Vxxx, XCE2Vxxx XC18Vxxx, XCFxxxS/P XCVxxxE (shrink), XC2SxxxE XCVxxxE, XC2Cxxx XC2Sxxx, XCVxxx (shrink) XCVxxx XC4xxxXLA, XCSxxxXL, XC95xxxXV
0.045 m
0.065 m 0.09 m 0.13 m 0.15 m 0.15 m 0.18 m/0.15 m 0.18 m 0.22 m/0.18 m 0.22 m 0.25 m
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Table 1-7:
Wafer Process Technology Family (Contd)

Process Technology
0.35 m/0.25 m 0.35 m 0.35 m 0.5 m 0.6 m 0.6 m Device XC95xxxXL XC4xxxXL, XCSxxx, XCRxxxXL XC17Vxxx, XC17SxxxA XC4xxxE, XC95xxx XC4xxx/L/E XC17(S)xxx/(X)L/E
ESD and Latch-up Summary

ESD results are obtained according to specifications ANSI/ESDA/JEDEC JS-001-2010 and JEDEC JESD22-C101. Latch-up results are obtained by using specification EIA/JESD78. ESD tests are performed at 25C. In general, the latch-up data for newer products such as 7 series FPGAs, Virtex-4, Virtex-5, Virtex-6, Spartan-3, and Spartan-6 devices are collected at 125C unless specified otherwise. ESD and latch-up data are summarized by family in these tables: Table 1-8: Table 1-8: PROMs, CPLDs, and older FPGAs Table 1-9: Virtex-II Pro devices Table 1-10 and Table 1-11: Virtex-4 devices Table 1-12: Virtex-5 devices Table 1-13: Spartan-6 devices Table 1-14: Virtex-6 devices Table 1-15: 7 series FPGAs
Product ESD and Latch-up Data

Device Latch-up +200 mA +210 mA +200 mA +200 mA +250 mA +220 mA +300 mA +250 mA +250 mA +250 mA +260 mA +200 mA Human Body Model +2,000V +2,000V +2,000V +2,000V +1,750V to +8,000V +4,000V to +7,000V +1,000V to +8,000V +3,000V to +8,000V +3,000V to +7,000V +2,000V to +8,000V +2,000V to +7,000V +1,000V to +2,000V Charge Device Model +2,000V(1) +1,000V(2) +500V +500V(3) +1,000V(4) +2,000V(5) +2,000V(6) +2,000V(7) +2,000V(8) +1,000V(9) +500V (Core)/+1,000V (corner)(10) +500V(11)
XC17xxxD/L XC17xxxE, XC17Sxxx XC17Vxxx XC18Vxxx XC31xxx/A XC3xxx/A XC4xxx/A XC4xxxE XC4xxxEX XC4xxxXL XC4xxxXLA XCVxxx
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Table 1-8:
Product ESD and Latch-up Data (Contd)

Device XCVxxxE Latch-up +210 mA +210 mA +310 mA +250 mA +210 mA +250 mA +200 mA +200 mA +200 mA +200 mA +200 mA +200 mA +200 mA +200 mA +200 mA +200 mA +200 mA +200 mA +200 mA Human Body Model +1,000V to +2,500V(12) Charge Device Model +300V(13) +500V(14) +1,000V(15) +500V(16) +500V(17) +2,000V(18) +1,000V(19) +1,000V(20) +500V(21) +500V(22) +500V +500V +500V +500V +500V +500V +500V +500V +500V
XCVxxxE/XC2SxxxE XCSxxx XCSxxxXL XC2Sxxx XC5xxx XC95xxx XC95xxxXL XC95xxxXV XCRxxxL XC2Vxxx XC2Cxxx XC3Sxxx XC3SxxxE XC3SxxxA XC3SxxxAN XC3SDxxxA XC18Vxxx(ST) XCFxxxS/P
Notes:
+2,000V to +3,000V +6,000V +3,000V +2,000V +3,000V to +7,000V +2,000V to +3,000V +2,000V to +3,000V +2,000V to +3,000V +2,000V to +3,000V +750V to 2,000V(23) +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V
1. Measured on XC1765D. 2. Measured on XC17256E. 3. Measured on XC18V04. 4. Measured on XC3190/A. 5. Measured on XC3090. 6. Measured on XC4005. 7. Measured on XC4005E. 8. Measured on XC4010E. 9. Measured on XC4028XL. 10. Measured on XC4062XLA. 11. Measured on XCV800. 12. Only XCV100E and XCV812E have ESD threshold below 2KV, (XCV100E passed at 1.5KV and XCV812E passed at 1KV) 13. Measured on XCV50E. 14. Measured on XCV2600 (shrink) and XCV3200 (shrink).
15. Measured on XCS10 and XCS30. 16. Measured on XCS30XL. 17. Measured on XC2S200. 18. Measured on XC5210. 19. Measured on XC95108. 20. Measured on XC9536XL. 21. Measured on XC95288XV. 22. Measured on XCR3064XL. 23. Human body model data collected on XC2V40, XC2V80, XC2V250, XC2V500, XC2V1000, XC2V1500, XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000. Using the human body model, these devices have a threshold below 2KV: The XC2V40 passes at 1.75KV. The XC2V4000 (from UMC 8D) passes at 1.5KV. The XC2V500 pass at 750V. Results do not include DXN and DXP temperature sensing pins. Results do not include VBATT pins for XC2VxxxX devices.
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The ESD results in Table 1-9 do not include DXN and DXP temperature sensing pins. Table 1-9: ESD and Latch-up Data for XC2VPxxx
Human Body Model Passing Voltage Device Latch-up 200 mA Regular I/O and Power MGT Charge Device Model Passing Voltage Regular I/O and Power MGT
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VPX20
Pass Pass Pass Pass Pass Pass Pass Pass Pass Pass
+1,500V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V
+2,000V +1,500V +1,000V +2,000V +2,000V +2,000V +2,000V +2,000V +1,000V +1,500V
+500V +500V +500V +500V +500V +500V +500V +500V +500V +400V
+300V +300V +500V +300V +300V +300V +300V +300V +300V +200V
Table 1-10:
ESD and Latch-up Data for XC4VFXxxx

Human Body Model Passing Voltage Charge Device Model Passing Voltage STDIO +450V +500V +500V +500V +450V +500V MGT N/A +300V +300V +300V +300V +300V
Device XC4VFX12 XC4VFX60 XC4VFX40 XC4VFX20 XC4VFX100 XC4VFX140
Latch-up pass pass pass pass pass pass
STDIO +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V
MGT N/A +1,000V +1,000V +1,000V +1,000V +1,000V
Table 1-11:
ESD and Latch-up Data for XC4VLXxxx and XC4VSXxxx

Latch-up pass pass pass pass pass pass Human Body Model Passing Voltage +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V Charge Device Mode Passing Voltage +500V +450V +450V +400V +450V +350V
Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100
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Table 1-11:
ESD and Latch-up Data for XC4VLXxxx and XC4VSXxxx (Contd)

Latch-up pass pass pass pass pass Human Body Model Passing Voltage +2,000V +2,000V +2,000V +2,000V +2,000V Charge Device Mode Passing Voltage +450V +350V +500V +450V +400V
Device XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55
Table 1-12: ESD and Latch-up Data for XC5VxXxxx/T Human Body Model Passing Voltage Device XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VFX30T XC5VFX70T XC5VFX100T XC5VFX130T XC5VFX200T XC5VSX35T XC5VSX50T XC5VSX95T Latch-up pass pass pass pass pass pass pass pass pass SelectIO(1) +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V +2,000V GTP +1,000V N/A +1,000V N/A +1,000V N/A +1,000V N/A +1,000V N/A +1,000V N/A +1,000V N/A +1,000V +1,000V +1,000V +1,000V +1,000V +1,000V +1,000V +1,000V +1,000V Charge Device Model Passing Voltage SelectIO +400V +400V +400V +400V +400V +400V +400V +400V(3) +400V(3) +400V +400V +400V +400V +400V +400V +400V +400V +400V +400V +400V +400V +400V +400V GTP +250V N/A +250V N/A +250V(2) N/A +250V(2) N/A +250V(2) N/A +250V(4) N/A +250V(4) N/A +250V(2) +250V +250V +250V +250V +250V +250V +250V(2) +250V
pass pass
pass(5) pass(5) pass(6) pass(6) pass pass pass pass pass pass pass pass
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Table 1-12: ESD and Latch-up Data for XC5VxXxxx/T (Contd) Human Body Model Passing Voltage Device XC5VSX240T XC5VTX150T XC5VTX240T Notes:
1. Human body model passing voltage for VBATT pin is 1,000V. This data is updated based on the data collected after the HBM tester was upgraded to remove the HBM-ESD trailing pulse. 2. If an internal AC coupling capacitor is used in the GTP receiver input (RX) pin, charge device model passing voltage is 200V. Compliance to ANSI/ESD S20.20 (ESD Association standard for the electrostatic discharge control program) is necessary. 3. Charge device model passing voltage for VBATT pin is 300V. 4. If an internal AC coupling capacitor is used in the GTP receiver input (RX) pin, the CDM level is 150V. Compliance to ANSI/ESD S20.20 (ESD Association standard for the electrostatic discharge control program) is necessary. 5. The D_IN and CS_B pins on XC5VLX220 and XC5VLX220T devices pass at 150 mA. 6. The D_IN, CS_B, and RDWR_B pins on XC5VLX300 and XC5VLX330T devices pass at 150 mA.
Charge Device Model Passing Voltage SelectIO +400V +400V +400V GTP +250V(2) +250V +250V
Latch-up pass pass pass
SelectIO(1) +2,000V +2,000V +2,000V
GTP +1,000V +1,000V +1,000V
Table 1-13:
Device XC6SLX16 XC6SLX25
ESD and Latch-up Data for XC6Sxxx

Latch-Up Pass Pass Pass Pass Pass Pass Pass Pass Pass Pass Pass HBM Passing Voltage SelectIO 2,000V 2,000V 2,000V 2,000V 2,000V 2,000V 2,000V 2,000V 2,000V 2,000V 2,000V GTP N/A N/A 2,000V N/A 2,000V N/A 2,000V N/A 2,000V N/A 2,000V CDM Passing Voltage SelectIO 500V 500V 500V 500V 500V 500V 500V 500V 500V 500V 500V GTP N/A N/A 400V N/A 400V N/A 400V N/A 400V N/A 450V
XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T
Table 1-14:
Device
ESD and Latch-up Data for XC6VxXxxx

HBM Passing Voltage Latch-Up SelectIO and Special Functions 2,000V(1) 2,000V(1) 2,000V(1) 2,000V(1) 2,000V(1) Transceiver 1,000V 1,000V 1,000V 1,000V 1,000V CDM Passing Voltage SelectIO and Special Functions 500V(2) 500V(2) 500V(2) 500V(2) 500V(2) Transceiver 250V 250V 250V 250V 250V
XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T
Pass Pass Pass Pass Pass
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Failure Rate Determination
Table 1-14:
Device
ESD and Latch-up Data for XC6VxXxxx (Contd)

HBM Passing Voltage Latch-Up SelectIO and Special Functions 2,000V(1) 2,000V(1) 2,000V(1) 2,000V(1) 2,000V(1) 2,000V(1) 2,000V(1) 2,000V(1) Transceiver 1,000V N/A 1,000V 1,000V 1,000V 1,000V 1,000V 1,000V CDM Passing Voltage SelectIO and Special Functions 500V(2) 500V(2) 500V(2) 500V(2, 3) 500V(2, 3) 500V(2, 3) 500V(2) 500V(2, 3) Transceiver 250V N/A 200V 250V 250V 250V 250V 250V
XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T

Notes:
Pass Pass Pass Pass Pass Pass Pass Pass
1. If the system monitor function is used, HBM passing voltage is: 1,000V for all of the devices. 2. If the system monitor function is used, CDM passing voltage for the AVDD, AVSS, VN, VP, VREFN, VREFP, DXN and DXP pins is: 200V for XC6VLX130T, XC6VLX195T, XC6VLX240T, XC6VSX315T, XC6VHX250T, XC6VHX255T, and XC6VHX565T devices; 150V for XC6VLX75T, XC6VLX365T, XC6VLX550T, XC6VLX760, XC6VSX475T, and XC6VHX380Tdevices. The DXN and DXP pins can withstand CDM voltages up to 500V without impacting the temperature sensing function. 3. The CDM passing voltage for the CCLK pin of the XC6VSX475T, XC6VHX250T, XC6VHX255T, and XC6VHX565T devices is 450V.
Table 1-15:
Device
ESD and Latch-up Data for 7 Series FPGAs

HBM Passing Voltage Latch-Up SelectIO and Special Functions 2,000V Transceiver 1,500V CDM Passing Voltage SelectIO and Special Functions 350V Transceiver 300V
XC7K325T
Pass
Failure Rate Determination

The failure rate is typically defined in FIT units. One FIT equals 1 failure per 1 billion device hours. For example, 5 failures expected out of 1 million components operating for 1,000 hours have a failure rate of 5 FIT. The following is the failure rate calculation method:
x 10 Failure Rate = ---------------------------------------------------------------------------------------------------------------------2(No. of Devices)(No. of Hours)(Acc. Factor)
2 9
Equation 1-1
where: x2 = Chi-squared value at a desired confidence level and (2f + 2) degrees of freedom, where f is the number of failures. The acceleration factor is calculated using the Arrhenius relationship:
Ea 1 1 A = exp ----- ------- ------ T J 1 T J 2 k
Equation 1-2
where:
Ea = Thermal activation energy (0.7eV is assumed and used in failure rate calculation except EPROM in which 0.58 eV is used).
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A = Acceleration factor k = Boltzman's constant, 8.617164 x 10-5 eV/K TJ1 = Use junction temperature in degrees Kelvin (K = C + 273.16) TJ2 = Stress junction temperature in degrees Kelvin (K = C + 273.16)
Failure Rate Summary

Table 1-16: Summary of the Failure Rates
Device Hours at TJ = 125C 495,908 1,565,214 1,074,022 3,058,944 10,685,692 2,220,131 3,287,432 2,110,352 2,511,926 3,777,837 2,115,203 1,974,124 3,054,550 2,151,754 4,321,681 1,051,816 2,068,881 813,893 1,069,748 FIT(1) 24 17 11 13 5 5 4 12 10 14 6 6 4 11 16 24 13 14 23 Process Technology 0.028 m 0.040 m 0.045 m 0.065 m 0.09 m 0.13 m 0.15 m (FPGA) 0.15 m (EPROM) 0.18/0.15 m 0.18 m 0.22/0.18 m 0.22 m 0.25 m 0.35 m/0.25 m 0.35 m 0.35 m (EPROM) 0.5 m 0.6 m 0.6 m (EPROM)
Notes:
1. FIT is calculated based on 0.7 eV (0.58 eV for EPROM), 60% C.L. and TJ of 55C.
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SEU and Soft Error Rate Measurements
SEU and Soft Error Rate Measurements

Table 1-17 shows the soft error rates caused by single event upsets (SEUs) affecting memory cells used as configuration memory and block RAM. Neutron cross-sections are determined from LANSCE beam testing according to JESD89A/89-3A. Failure rates (in FIT/Mb) are determined from real time (system level) measurements in various locations and altitudes and corrected for New York City, according to JESD89A/89-1A. All data is current as of date of this report. Note: The actual SEU FIT rate of a design running in a Xilinx FPGA is far lower than what is predicted by direct calculation from the numbers in Table 1-17. This is because most FPGA routing resources are unused within any particular implementation. Table 1-17:
Technology Node
Real Time Soft Error Rates

Neutron Cross-section per Bit(1) Product Family Configuration Memory 9.90 x 10-15 1.12 x 2.56 x 10-14 10-14 Block Ram 9.90 x 10-15 1.12 x 2.64 x 10-14 10-14 Error 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 135 34 180 53 50% +100% 50% +100% 40 100 50% +100% FIT/Mb (Alpha Particle)(2) FIT/Mb (Real Time Soft Error Rate)(3)
Configuration Configuration Block RAM Error(4) Block RAM Error(4) Memory Memory 160 181 405 437 263 165 104 190 104 185 71 160 181 478 770 484 692 247 373 293 389 59 20% 20% 8% 8% 11% 13% +15% 18% +24% 50% +80% 80% +90% -14% +18% -48% +110%
250 nm 180 nm 150 nm 130 nm 90 nm 65 nm 40 nm 90 nm 90 nm 45 nm 28 nm
Virtex Virtex-E Virtex-II Virtex-II Pro Virtex-4 Virtex-5 Virtex-6 Spartan-3 Spartan-3E Spartan-3A Spartan-6 7 Series FPGAs
2.74 x 10-14 1.55 x 10-14 6.70 x 10-15 1.26 x 10-14 2.40 x 10-14 1.31 x 10-14 1.00 x 10-14 6.99 x 10-15
3.91 x 10-14 2.74 x 10-14 3.96 x 10-14 1.14 x 10-14 3.48 x 10-14 2.73 x 10-14 2.20 x 10-14 6.32 x 10-15
Notes:
1. Data from Los Alamos Neutron Science Center (LANSCE). 2. Spartan-6 and 7 series FPGAs data based on thorium foil testing and package alpha emissivity of 0.0015 counts/cm2/hr. Virtex-6 FPGA alpha data estimated using Virtex-6 Real Time Soft Error Rate Results. 3. Data compiled from the Rosetta experiment which includes upsets from neutron secondaries and packaging alpha particles. See WP286, Continuing Experiments of Atmospheric Neutron Effects on Deep Submicron Integrated Circuits. 4. 90% confidence interval.
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Chapter 2
Results by Product Family

FPGA Products
High-Temperature Operating Life (HTOL) Test
The HTOL test is conducted under the conditions of TJ > 125C temperature, maximum VDD, and either dynamic or static operation. The FIT failure rate calculation in the following tables is based on the assumption of 0.7 eV activation energy and 60% confidence level (CL).
Summary
The failures listed in Table 2-1 are also listed in each family device table with failure analysis results in the footnotes. Table 2-1:
Summary of HTOL Test Results
Device
XC4xxx/E (0.6 m) XC4xxx/E (0.5 m) XC4xxxXL XC4xxxXLA XCSxxx XCSxxxXL XC2Sxxx XCVxxx XCVxxx (shrink) XCVxxxE XCVxxxE (shrink) XC2SxxxE XC2Vxxx XCE2Vxxx XC2VPxxx
Lot Quantity
13 12 26 12 14 14 10 20 11 31 17 15 21 9 8
Fail Quantity
0 1 3 0 0 0 0 0 0 3 1 0 0 0 0
Device Quantity
592 519 1,067 524 616 610 452 868 483 1,240 580 781 894 395 357
Actual Device Hours at TJ > 125C

362,812 998,220 1,443,697 994,225 864,404 996,727 912,017 1,323,861 936,282 1,768,713 1,013,731 845,263 1,630,546 792,767 677,671
Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT)
813,893 1,052,368 2,230,289 1,010,806 1,055,224 1,015,462 1,085,860 1,974,124 1,044,774 2,741,592 1,454,931 1,056,995 2,201,393 1,086,039 1,057,873 14 25 24 12 11 12 11 6 11 20 17 11 5 11 11
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Table 2-1:
Summary of HTOL Test Results (Contd)
Device
XCE2VPxxx XC3Sxxx XC3SxxxE XC3SxxxA XC3SxxxAN XC3SDxxxA
Lot Quantity
8 10 11 11 9 8 6 10 17 11 3 5 3 3
Fail Quantity
0 0 0 0 0 0
Device Quantity
384 445 495 531 435 332 304 470 1,000 617 249 273 240 231

834,489 802,610 816,920 1,020,463 830,832 644,727 521,129 898,128 1,526,048 1,137,683 249,000 506,000 240,000 385,000
1,162,258 1,017,942 1,060,436 1,103,151 1,103,223 1,137,253 1,223,275 2,054,365 3,204,320 2,428,064 630,879 1,061,660 503,554 495,908 10 12 11 11 11 10 10 19 8 16 19 24 23 24
XC6Sxxx
XC4VxXxxx XCE4VxVxxx XC5VxXxxx XCE5VxXxxx XC6VxXxxx XCE6VxXxxx 7 Series FPGAs
0
2 1 2 0 1 0 0
Data
Table 2-2:
Device
HTOL Test Results of 0.6 m, Si Gate CMOS Device Type XC4xxx/E

Lot Quantity Fail Quantity Device Quantity Actual Device Hours at TJ > 125C Equivalent Device Hours at TJ = 125C Failure Rate at 60% CL and TJ = 55C (FIT)
XC4005E XC4010E XC4013E XC4025E XC4xxx/E
2 8 2 1 13
0 0 0 0 0
94 364 87 47
24,064 190,462 136,254 12,032 362,812
63,878 505,683 212,393 31,939 813,893 14 FIT
592
Table 2-3:
Device
HTOL Test Results of 0.5 m, Si Gate CMOS Device Type XC4xxx/E

Lot Quantity Fail Quantity Device Quantity Actual Device Hours at Equivalent Device Hours at TJ = 125C Failure Rate at 60% CL and TJ = 55C (FIT)
TJ > 125C 90,180

90,585 271,485 545,970
XC4006E
XC4008E XC4010E XC4013E
1
1 3 7
0
0 0 1(1)
45
45 135 294
94,506
90,585 284,572 582,705
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FPGA Products
Table 2-3:
Device
HTOL Test Results of 0.5 m, Si Gate CMOS Device Type XC4xxx/E (Contd)
TJ > 125C
998,220
XC4xxx/E Notes:
12
519
1,052,368
25 FIT
1. Failure at post 2,006 hours. Failure analysis was not performed.
Table 2-4:
Device
HTOL Test Results for 0.35 m Si Gate CMOS Device Type XC4xxxXL
TJ > 125C
133,700 653,141 186,000 144,132 145,252 126,840 54,632 1,443,697
XC4005XL XC4010XL XC4020XL XC4028XL XC4036XL XC4044XL XC4062XL XC4xxxXL Notes:
2 9 2 4 4 2 3 26
89 398 93 150 183 63 91 1,067
207,111 888,820 334,904 302,705 218,721 133,009 145,020 2,230,289 24 FIT
1(1)
0 0 0 0
2(2)
3
1. The device failed at post 1,033 hours. No failure analysis was performed. 2. No defect was found at post 48 hours.
Table 2-5:
Device
HTOL Test Results for 0.25 m Si Gate CMOS Device Type XC4xxxXLA
TJ > 125C
409,785 157,000 88,797 84,000 254,643 994,225
XC4020XLA XC4028XLA XC4044XLA XC4052XLA XC4085XLA XC4xxxXLA
5 2 1 1 3 12
0 0 0 0 0 0
222 89 44 42 127 524
416,826 160,343 92,134 86,860 254,643 1,010,806 12 FIT
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Table 2-6:
Device
HTOL Test Results for 0.35 m Si Gate CMOS Device Type XCSxxx
TJ > 125C
78,351 218,639 340,038 227,376 864,404
XCS05 XCS20 XCS30 XCS40 XCSxxx
1 4 4 5 14
0 0 0 0 0
39 174 181 222 616
78,351 377,212 357,228 242,433 1,055,224 11 FIT
Table 2-7:
Device
HTOL Test Results for 0.25 m Si Gate CMOS Device Type XCSxxxXL
Lot Quantity
6 2 6 14
Fail Quantity
0 0 0 0
Device Quantity
266 80 264 610

423,072 160,330 413,325 996,727
433,766 159,566 422,130 1,015,462 12 FIT
XCS20XL XCS30XL XCS40XL XCSxxxXL
Table 2-8:
Device
HTOL Test Results for 0.22/0.18 m Si Gate CMOS Device Type XC2Sxxx
Lot Quantity 2 8 10 Fail Quantity 0 0 0 Device Quantity 89 363 452 Actual Device Hours at TJ > 125C 178,088 733,929 912,017 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 204,672 881,188 1,085,860 11 FIT
XC2S100 XC2S200 XC2Sxxx
Table 2-9:
Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV800
HTOL Test Results for 0.22 m Si Gate CMOS Device Type XCVxxx
Lot Quantity 4 1 1 5 5 2 2 20 Fail Quantity 0 0 0 0 0 0 0 0 Device Quantity 180 45 45 226 284 44 44 868 Actual Device Hours at TJ > 125C 319,500 90,090 90,090 455,724 309,695 28,402 30,360 1,323,861 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 340,250 97,778 97,655 527,095 822,081 38,484 50,780 1,974,124 6 FIT
XCV1000 XCVxxx
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FPGA Products
Table 2-10:
Device XCV300 XCV400 XCV600 XCV800 XCV1000 XCVxxx
HTOL Test Results for 0.22/0.18 m Si Gate CMOS Device Type XCVxxx (Shrink)
Lot Quantity 2 2 5 1 1 11 Fail Quantity 0 0 0 0 0 0 Device Quantity 90 90 213 45 45 483 Actual Device Hours at TJ > 125C 180,315 160,155 415,542 90,090 90,180 936,282 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 202,304 174,509 468,643 96,514 103,804 1,044,774 11 FIT
Table 2-11:
Device XCV50E XCV100E XCV200E XCV600E XCV405E XCV812E XCV1000E XCV1600E XCV2000E XCVxxxE
Notes:
HTOL Test Results for 0.18 m Si Gate CMOS Device Type XCVxxxE
Lot Quantity 2 2 3 4 4 4 2 5 5 31 Fail Quantity 0 0 0 0 1(1) 0 0 1(2) 1(3) 3 Device Quantity 84 80 165 118 209 159 97 195 133 1,240 Actual Device Hours at TJ > 125C 126,630 115,765 215,436 155,046 249,914 266,663 98,080 389,099 156,080 1,768,713 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 336,137 115,765 571,872 411,568 266,058 284,177 98,081 461,936 195,998 2,741,592 20 FIT
1. Functional failure at post 184 hours. 2. Marginal failure at post 501 hours. 3. No defect found at post 281 hours.
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Table 2-12:
Device XCV400E XCV600E XCV1000E XCV2000E XCV2600E XCV3200E XCVxxxE (shrink)
Notes:
HTOL Test Results for 0.18/0.15 m Si Gate CMOS Device Type XCVxxxE (Shrink)
Lot Quantity 3 1 7 5 1 1 17 Fail Quantity 0 0 0 0 1(1) 0 1 Device Quantity 135 45 234 166 22 23 580 Actual Device Hours at TJ > 125C 359,873 83,205 359,873 312,094 23,604 46,000 1,013,731 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 331,387 96,862 580,352 473,588 23,604 46,000 1,454,931 17 FIT
1. No defect found at post 189 hours.
Table 2-13:
Device XC2S100E XC2S150E XC2S300E XC2S400E XC2SxxxE
HTOL Test Results for 0.18/0.15 m Si Gate CMOS Device Type XC2SxxxE
Lot Quantity 6 1 7 1 15 Fail Quantity 0 0 0 0 0 Device Quantity 275 45 416 45 781 Actual Device Hours at TJ > 125C 278,162 91,665 384,671 95,765 845,263 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 415,349 110,293 416,410 114,943 1,056,995 11 FIT
Table 2-14:
Device XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000
HTOL Test Results for 0.15 m Si Gate CMOS Device Type XC2Vxxx
Lot Quantity 3 2 1 4 3 1 1 3 Fail Quantity 0 0 0 0 0 0 0 0 Device Quantity 134 88 45 164 135 45 27 134 Actual Device Hours at TJ > 125C 249,053 177,881 68,400 247,832 270,990 90,630 54,054 225,627 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 317,935 190,660 79,796 328,763 338,744 106,505 67,742 303,030
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FPGA Products
Table 2-14:
Device XC2V4000 XC2V6000 XC2Vxxx
HTOL Test Results for 0.15 m Si Gate CMOS Device Type XC2Vxxx (Contd)
Lot Quantity 1 2 21 Fail Quantity 0 0 0 Device Quantity 44 78 894 Actual Device Hours at TJ > 125C 88,088 157,991 1,630,546 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 99,435 368,783 2,201,393 5 FIT
Table 2-15:
Device XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VPxxx
HTOL Test Results for 0.13 m Si Gate CMOS Device Type XC2VPxxx
Table 2-16:
Device
HTOL Test Results for 0.15 m Si Gate CMOS Device Type XCE2Vxxx
XCE2V1000 XCE2V4000 XCE2Vxxx
Table 2-17:
Device XCE2VP7 XCE2VP40 XCE2VP50 XCE2VP70
HTOL Test Results for 0.13 m Si Gate CMOS Device Type XCE2VPxxx
XCE2VPxxx
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Table 2-18:
Device XC3S400 XC3S1000 XC3S1500 XC3Sxxx
HTOL Test Results for 0.09 m Si Gate CMOS Device Type XC3Sxxx
Lot Quantity 4 4 2 10 Fail Quantity 0 0 0 0 Device Quantity 175 180 90 445 Actual Device Hours at TJ > 125C 306,035 361,080 135,495 802,610 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 374,236 463,462 180,244 1,017,942 12 FIT
Table 2-19:
Device XC3S250E XC3S500E XC3S700E
HTOL Test Results for 0.09 m Si Gate CMOS Device Type XC3SxxxE
XC3S1600E XC3SxxxE
Table 2-20:
Device XC3S200A
HTOL Test Results for 0.09 m Si Gate CMOS Device Type XC3SxxxA
Lot Quantity 2 9 11 Fail Quantity 0 0 0 Device Quantity 49 482 531 Actual Device Hours at TJ > 125C 49,629 970,834 1,020,463 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 53,551 1,049,600 1,103,151 11 FIT
XC3S1400A XC3SxxxxA
Table 2-21:
Device
HTOL Test Results for 0.09 m Si Gate CMOS Device Type XC3SxxxAN
XC3S700AN XC3S1400AN XC3SxxxAN
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FPGA Products
Table 2-22:
Device
HTOL Test Results for 0.09 m Si Gate CMOS Device Type XC3SDxxxA
XC3SD1800A XC3SD3400A XC3SDxxxA
Table 2-23:
Device
HTOL Test Results for 0.045 m Si Gate CMOS Device Type XC6Sxxx
XC6SLX100T XC6SLX45 XC6SLX45T XC6SLX75T XC6SLX150T XC6Sxxx
Table 2-24:
Device XC4VLX60 XC4VLX80
HTOL Test Results for 0.09 m Si Gate CMOS Device Type XC4VxXxxx
Lot Quantity 3 1 1 1 1 1 1 1 10 Fail Quantity 0 0 0 2(1) 0 0 0 0 2 Device Quantity 136 75 45 45 45 42 37 45 470 Actual Device Hours at TJ > 125C 230,316 150,525 90,855 64,629 90,000 84,630 75,757 90,045 898,128 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 531,451 410,767 259,245 231,189 116,627 182,316 100,039 222,731 2,054,365 19 FIT
XC4VLX100 XC4VLX160 XC4VFX12 XC4VFX60 XC4VSX25 XC4VSX55 XC4VxXxxx

Notes:
1. Failure due to substrate defect. New process improvement has been implemented.
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33
Table 2-25:
Device
HTOL Test Results for 0.09 m Si Gate CMOS Device Type XCE4VxXxxx
Lot Quantity 8 4 3 2 17 Fail Quantity 0 1(1) 0 0 1 Device Quantity 597 180 133 90 1,000 Actual Device Hours at TJ > 125C 921,000 246,985 267,478 90,585 1,526,048 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 1,977,966 729,418 372,057 124,879 3,204,320 8 FIT
XCE4VLX100 XCE4VLX80 XCE4VLX40 XCE4VSX25 XCE4VxXxx

Notes:
1. Failure due to substrate defect. New process improvement has been implemented.
Table 2-26:
Device
Lot Quantity 1 6 3 1 11 Fail Quantity 0 1(1) 1 (2) 0 2 Device Quantity 40 401 134 42 617 Actual Device Hours at TJ > 125C 80,520 729,408 243,545 84,210 1,137,683 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 349,969 1,225,638 504,606 347,851 2,428,064 16 FIT
XC5VLX155T XC5VLX110T XC5VLX50T XC5VSX35T XC5VxXxxx

Notes:
1. Failure due to substrate defect. New process improvement has been implemented. 2. Failure due to fabrication process defect. New process improvement has been implemented.
Table 2-27:
Device
Lot Quantity 3 3 Fail Quantity 0 0 Device Quantity 249 249 Actual Device Hours at TJ > 125C 249,000 249,000 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 630,879 630,879 19 FIT
XCE05VL11 XCE5VxXxxx
Table 2-28:
Device
Lot Quantity 1 1 2 1 Fail Quantity 0 0 1(1) 0 Device Quantity 76 45 108 44 Actual Device Hours at TJ > 125C 114,000 90,000 214,000 88,000 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 239,188 188,833 449,002 184,637
XC6VHX255T XC6VLX130T XC6VLX240T XC6VLX365T
34
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FPGA Products
Table 2-28:
Device
HTOL Test Results for 0.040 m Si Gate CMOS Device Type XC6VxXxxx (Contd)
Lot Quantity 5 Fail Quantity 1 Device Quantity 273 Actual Device Hours at TJ > 125C 506,000 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 1,061,660 24 FIT
XC6VxXxxx
Notes:
1. One unit failed for configuration at post HTOL stress, but the root cause could not be identified during failure analysis.
Table 2-29:
Device XCE06L24T
XCE6VxXxxx
Table 2-30:
Device
HTOL Test Results for 0.028 m Si Gate CMOS Device Type 7 Series FPGAs
XC7K325T 7 Series FPGAs
Temperature Humidity with Bias Test

The THB test is conducted under the conditions of 85C and 85% RH and VDD bias. Package preconditioning is performed on the testing samples prior to the THB test. The failures listed in Table 2-31 are also listed by device with failure analysis results in the footnotes.
Summary
Table 2-31:
Device XC4xxxXLA XCSxxxXL XCSxxx XCVxxxE XCVxxxE (shrink) XC2Vxxx XC2VPxxx XC2SxxxE XC3Sxxx
THB Test Results for Si Gate CMOS Devices

Lot Quantity 1 1 1 1 1 2 9 2 2 Fail Quantity 0 0 0 0 0 1 0 0 0 Device Quantity 45 45 25 45 45 63 344 90 90 Total Device Hours 45,000 45,360 25,225 45,585 45,720 63,008 344,000 90,000 90,000
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Table 2-31:
Device
THB Test Results for Si Gate CMOS Devices (Contd)

Lot Quantity 5 1 1 1 10 7 19 6 Fail Quantity 0 0 0 0 0 0 0 0 Device Quantity 225 8 45 43 390 308 506 147 Total Device Hours 225,000 8,000 45,135 43,000 390,360 311,010 509,450 147,000
XC3SxxxE XC3SxxxA XC3SDxxxA XC3SxxxAN XC4VxXxxx XC5VxXxxx XC6VxXxxx 7 Series FPGAs
Data
Table 2-32:
Device XC4020XLA XC4xxxXLA
THB Test Results for Si Gate CMOS Device Type XC4xxxXLA

Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 45 45 Total Device Hours 45,000 45,000
Table 2-33:
Device
THB Test Results for Si Gate CMOS Device Type XCSxxxXL

Lot Quantity 1 Fail Quantity 0 Device Quantity 45 Total Device Hours 45,360
XCS40XL
Table 2-34:
Device XCS20 XCSxxx
THB Test Results for Si Gate CMOS Device Type XCSxxx

Table 2-35:
Device
THB Test Results for Si Gate CMOS Device Type XCVxxxE

XCV1600E
36
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FPGA Products
Table 2-36:
Device
THB Test Results for Si Gate CMOS Device Type XCVxxxE (Shrink)
XCV600E XCVxxxE (shrink)
Table 2-37:
Device
THB Test Results for Si Gate CMOS Device Type XC2Vxxx

Lot Quantity 1 1 Fail Quantity 1(1) 1 Device Quantity 18 18 Total Device Hours 17,918 17,918
XC2V3000 XC2Vxxx
Notes:
1. Failure due to an assembly process defect. Corrective action has been implemented.
Table 2-38:
Device
THB Test Results for Si Gate CMOS Device Type XC2VPxxx

Lot Quantity 3 2 4 9 Fail Quantity 0 0 0 0 Device Quantity 134 90 120 344 Total Device Hours 134,000 90,000 120,000 344,000
XC2VP20 XC2VP40 XC2VP50 XC2VPxxx
Table 2-39:
Device
THB Test Results for Si Gate CMOS Device Type XC2SxxxE

Lot Quantity 1 1 2 Fail Quantity 0 0 0 Device Quantity 45 45 90 Total Device Hours 45,000 45,000 90,000
XC2S150E XC2S300E XC2SxxxE
Table 2-40:
Device
THB Test Results for Si Gate CMOS Device Type XC3Sxxx

XC3S1000 XC3S400 XC3Sxxx
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Table 2-41:
Device
THB Test Results for Si Gate CMOS Device Type XC3SxxxE

XC3S100E XC3S250E XC3S500E XC3SxxxE
Table 2-42:
Device
THB Test Results for Si Gate CMOS Device Type XC3SxxxA

XC3S200A XC3SxxxA
Table 2-43:
Device
THB Test Results for Si Gate CMOS Device Type XC3SDxxxA

XC3SD1800A
Table 2-44:
Device
THB Test Results for Si Gate CMOS Device Type XC3SxxxAN

XC3S1400AN
Table 2-45:
Device
THB Test Results for Si Gate CMOS Device Type XC4VxXxxx

Lot Quantity 1 2 1 1 3 2 10 Fail Quantity 0 0 0 0 0 0 0 Device Quantity 45 90 45 45 75 90 390 Total Device Hours 45,000 90,000 45,360 45,000 75,000 90,000 390,360
XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VxXxxx
Table 2-46:
Device

XC5VSX50T XC5VLX85T
38
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Table 2-46:
Device
THB Test Results for Si Gate CMOS Device Type XC5VxXxxx (Contd)
XC5VLX110T XC5VLX155T XC5VxXxxx
Table 2-47:
Device

Lot Quantity 1 3 3 3 3 5 1 19 Fail Quantity 0 0 0 0 0 0 0 0 Device Quantity 45 73 75 73 64 131 416 506 Total Device Hours 45,540 74,533 75,225 73,384 64,270 131,498 45,000 509,450
XC6VHX565T XC6VHX255T XC6VLX115T(1) XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VxXxxx

Notes:
1. The XC6VLX115T device is an internal product qualification vehicle.
Table 2-48:
Device
THB Test Results for Si Gate CMOS Device Type 7 Series FPGAs
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Temperature Humidity Test

The TH test is conducted under the conditions of 85C and 85% RH Package preconditioning is performed on the testing samples prior to the TH test.
Summary
Table 2-49:
Device XC4xxxE XC4xxxXLA XCSxxx XCSxxxXL XCVxxx (shrink) XCVxxxE XCVxxxE (shrink) XC2Sxxx XC2SxxxE XC2Vxxx XC2VPxxx XC3Sxxx XC3SxxxE XC3SxxxA XC3SDxxxA XC4VxXxxx XC5VxXxxx XC6VxXxxx 7 Series FPGAs
Summary of TH Test Results

Lot Quantity 1 1 1 2 2 2 5 3 2 2 2 2 1 2 2 6 6 12 3 Fail Quantity 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Device Quantity 45 40 20 78 119 119 219 149 122 83 79 90 45 54 158 98 279 276 75 Total Device Hours 45,450 42,280 20,100 78,558 121,702 119,639 220,626 153,136 122,089 84,581 79,896 90,765 45,315 55,701 158,396 98,596 283,190 276,663 75,000
Data
Table 2-50:
Device XC4013E
TH Test Results for Si Gate CMOS Device Type XC4xxxE

40
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Table 2-51:
Device
TH Test Results for Si Gate CMOS Device Type XC4xxxXLA

XC4052XLA
Table 2-52:
Device XCS20
TH Test Results for Si Gate CMOS Device Type XCSxxx

Table 2-53:
Device
TH Test Results for Si Gate CMOS Device Type XCSxxxXL

XCS40XL
Table 2-54:
Device XCV300
TH Test Results for Si Gate CMOS Device Type XCVxxx (Shrink)

Table 2-55:
Device
TH Test Results for Si Gate CMOS Device Type XCVxxxE

XCV1600E
Table 2-56:
Device
TH Test Results for Si Gate CMOS Device Type XCVxxxE (Shrink)

XCV300E XCV600E XCVxxxE
Table 2-57:
Device XC2S30 XC2S15 XC2S200 XC2Sxxx
TH Test Results for Si Gate CMOS Device Type XC2Sxxx

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Table 2-58:
Device
TH Test Results for Si Gate CMOS Device Type XC2SxxxE

XC2S300E
Table 2-59:
Device XC2V500
TH Test Results for Si Gate CMOS Device Type XC2Vxxx

XC2V6000 XC2Vxxx
Table 2-60:
Device
TH Test Results for Si Gate CMOS Device Type XC2VPxxx

XC2VP20 XC2VP40 XC2VPxxx
Table 2-61:
Device XC3S200
TH Test Results for Si Gate CMOS Device Type XC3Sxxx

XC3S1500 XC3Sxxx
Table 2-62:
Device
TH Test Results for Si Gate CMOS Device Type XC3SxxxE

XC3S500E XC3SxxxE
Table 2-63:
Device
TH Test Results for Si Gate CMOS Device Type XC3SxxxA

XC3S1400A
Table 2-64:
Device
TH Test Results for Si Gate CMOS Device Type XC3SDxxxA

XC3SD3400A
42
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Table 2-65:
Device
TH Test Results for Si Gate CMOS Device Type XC4VxXxxx

XC4VLX80 XC4VLX100 XC4VxXxxx
Table 2-66:
Device

XC5VLX50T
Table 2-67:
Device

Lot Quantity 3 3 3 3 12 Fail Quantity 0 0 0 0 0 Device Quantity 74 45 82 75 276 Total Device Hours 74,345 45,000 82,318 75,000 276,663
XC6VHX255T XC6VLX115T(1) XC6VLX130T XC6VLX240T XC6VxXxxx

Notes:
1. The XC6VLX115T device is an internal product qualification vehicle.
Table 2-68:
Device
TH Test Results for Si Gate CMOS Device Type 7 Series FPGAs

Temperature Cycling Test

The temperature cycling test is conducted under the conditions of predefined maximum and minimum temperatures and in air-to-air environment. Package precondition is performed on the testing samples prior to the temperature cycling test.
Summary
Table 2-69:
Device XC4xxxE XC4xxxXL
Summary of Temperature Cycling Test Results

Lot Quantity 2 1 Failures 0 0 Device on Test 90 45 Total Device Cycles 90,000 45,000
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Table 2-69:
Device
Summary of Temperature Cycling Test Results (Contd)

Lot Quantity 2 3 2 4 11 2 1 2 3 6 9 20 19 5 7 9 33 19 18 61 3 Failures 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Device on Test 90 135 90 180 495 90 45 120 134 270 368 897 853 225 303 303 1,243 736 699 1,538 75 Total Device Cycles 90,000 135,000 90,000 182,250 497,250 90,000 45,000 120,720 136,250 270,900 370,250 887,250 857,500 225,900 303,000 303,000 1,252,212 736,000 711,152 1,512,811 75,000
XC4xxxXLA XCSxxx XCSxxxXL XC2Sxxx XC2SxxxE XCVxxx XCVxxx (shrink) XCVxxxE XCVxxxE (shrink) XC2Vxxx XC2VPxxx XC3Sxxx XC3SxxxE XC3SxxxA XC3SDxxxA XC3SxxxAN XC6Sxxx XC4VxXxxx XC5VxXxxx XC6VxXxxx 7 Series FPGAs
Notes:
1. Failures listed in this table are also listed in each family device table with failure analysis results in the footnote.
Data
Table 2-70:
Device XC4013E
Temperature Cycling Test Results for Si Gate CMOS Device Type XC4xxx/E
Stress Condition B: 55C to +125C Lot Quantity 2 Fail Quantity 0 Device Quantity 90 Total Device Cycles 90,000
44
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Table 2-71:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC4xxxXL
Stress Condition B: 55C to +125C B: 55C to +125C Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 45 45 Total Device Cycles 45,000 45,000
XC4005XL XC4xxxXL
Table 2-72:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC4xxxXLA
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 1 1 2 Fail Quantity 0 0 0 Device Quantity 45 45 90 Total Device Cycles 45,000 45,000 90,000
XC4013XLA XC4020XLA XC4xxxXLA
Table 2-73:
Device XCS10 XCS20 XCSxxx
Temperature Cycling Test Results of Si Gate CMOS Device Type XCSxxx

Table 2-74:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XCSxxxXL
XCS20XL
Table 2-75:
Device XC2S15
Temperature Cycling Test Results for Si Gate CMOS Device Type XC2Sxxx
XC2S150 XC2Sxxx
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Table 2-76:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC2SxxxE
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 2 4 2 3 11 Fail Quantity 0 0 0 0 0 Device Quantity 90 180 90 135 495 Total Device Cycles 90,000 182,250 90,000 135,000 497,250
XC2S50E XC2S100E XC2S150E XC2S300E XC2SxxxE
Table 2-77:
Device XCV50 XCV100
Temperature Cycling Test Results for Si Gate CMOS Device Type XCVxxx
XCVxxx
Table 2-78:
Device XCV400
Temperature Cycling Test Results for Si Gate CMOS Device Type XCVxxx (Shrink)
XCVxxx (shrink)
Table 2-79:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XCVxxxE
XCV405E XCV812E XCVxxxE
46
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Table 2-80:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XCVxxxE (Shrink)
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 1 1 1 3 Fail Quantity 0 0 0 0 Device Quantity 45 44 45 134 Total Device Cycles 45,000 44,000 47,250 136,250
XCV400E XCV600E XCV1000E XCVxxxE
Table 2-81:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC2Vxxx
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C and G: 40C to +125C Lot Quantity 2 2 1 1 Fail Quantity 0 0 0 0 Device Quantity 90 90 45 45 Total Device Cycles 90,000 90,000 45,000 45,900
XC2V1000 XC2V1500 XC2V4000 XC2V6000
XC2Vxxx
270
270,900
Table 2-82:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC2VPxxx
Stress Condition B: 55C to +125C B: 55C to +125C G: 40C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 3 2 3 1 9 Fail Quantity 0 0 0 0 0 Device Quantity 135 90 93 50 368 Total Device Cycles 135,000 90,000 95,250 50,000 370,250
XC2VP20 XC2VP40 XC2VP50 XC2VP70 XC2VPxxx
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Table 2-83:
Device
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 6 5 4 5 20 Fail Quantity 0 0 0 0 0 Device Quantity 270 222 180 225 897 Total Device Cycles 271,500 224,250 166,500 225,000 887,250
XC3S200 XC3S400 XC3S1000 XC3S1500 XC3Sxxx
Table 2-84:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC3SxxxE
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 6 3 4 2 4 19 Fail Quantity 0 0 0 0 0 0 Device Quantity 269 135 180 90 179 853 Total Device Cycles 269,000 137,250 180,000 90,000 181,250 857,500
XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E XC3SxxxE
Table 2-85:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC3SxxxA
XC3S200A XC3S400A XC3S1400A XC3SxxxA
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Table 2-86:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC3SDxxxA
Table 2-87:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC3SxxxAN
XC3S200AN XC3S400AN XC3S1400AN XC3SxxxAN
Table 2-88:
Device
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C C: 65C to +150C Lot Quantity 1 4 4 1 5 7 11 Fail Quantity 0 0 0 0 0 0 0 Device Quantity 45 135 135 45 176 358 349 Total Device Cycles 45,000 122,580 135,990 45,000 179,206 366,930 357,163
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX150T
XC6Sxxx
33
1,243
1,252,212
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Table 2-89:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC4VxXxxx
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 1 1 2 1 4 1 6 1 1 1 19 Fail Quantity 0 0 0 0 0 0 0 0 0 0 0 Device Quantity 45 45 90 45 120 45 206 50 45 45 736 Total Device Cycles 45,000 45,000 90,000 45,000 120,000 45,000 206,000 50,000 45,000 45,000 736,000
XC4VFX20 XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX200 XC4VSX25 XC4VSX35 XC4VxXxxx
Table 2-90:
Device
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 1 1 2 3 2 4 3 Fail Quantity 0 0 0 0 0 0 0 Device Quantity 45 45 90 128 90 120 74 Total Device Cycles 45,000 45,000 90,000 128,000 90,000 120,000 74,000
XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155T XC5VLX330T
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Table 2-90:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC5VxXxxx (Contd)
XC5VSX50T XC5VXxXxxx
Table 2-91:
Device
Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 2 1 7 3 9 1 13 1 2 22 61 Fail Quantity 1(1) 0 0 0 0 0 0 0 0 0 1 Device Quantity 50 25 118 45 283 44 362 45 43 523 1,538 Total Device Cycles 49,425 25,425 118,000 45,000 239,757 44,000 378,813 45,000 44,362 523,029 1,512,811
XC6VHX255T XC6VHX380T XC6VHX565T XC6VLX115T(2) XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX760 XC6VSX475T XC6VxXxxx
Notes:
1. Device failed at post temperature cycling stress was due to a solder particle at bump. Post bump cleaning improvement is being implemented. 2. XC6VLX115T is an internal product qualification vehicle.
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Table 2-92:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type 7 Series FPGAs
Autoclave Test
The autoclave test is conducted under the conditions of 121C, 100% RH (unbiased), and 29.7 PSI. Package preconditioning is performed on the testing samples prior to the autoclave stress test.
Summary
Table 2-93:
Device XC3Sxxx XC3SxxxE
Summary of Autoclave Test Results

Data
Table 2-94:
Device XC3S200
Autoclave Test Results for Si Gate CMOS Device Type XC3Sxxx

Table 2-95:
Device
Autoclave Test Results for Si Gate CMOS Device Type XC3SxxxE

XC3S100E
52
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High Accelerated Stress Test

The HAST test is conducted under the conditions of 130C, 85% RH and VDD bias or 110C, 85% RH and VDD bias. Package preconditioning is performed on the testing samples prior to the HAST test.
Summary
Table 2-96:
Device XC2SxxxE XCVxxxE XCVxxxE (shrink) XC3Sxxx XC3SxxxA XC3SDxxxA XC3SxxxAN XC6Sxxx XC4VxXxxx
Summary of HAST Test Results

Lot Quantity 2 1 3 1 1 1 2 11 2 Fail Quantity 0 0 0 0 0 0 0 0 0 Device Quantity 65 33 111 45 45 45 106 495 46 Total Device Hours 6,240 8,812 12,672 4,320 4,320 11,880 10,176 69,588 12,144
Data
Table 2-97:
Device XC2S100E XC2S150E XC2SxxxE
HAST Test Results for Si Gate CMOS Device Type XC2SxxxE

Stress Condition 130C, 85% RH 130C, 85% RH 130C, 85% RH Lot Quantity 2 1 2 Fail Quantity 0 0 0 Device Quantity 35 20 65 Total Device Cycles 6,240 1,920 6,240
Table 2-98:
Device
HAST Test Results for Si Gate CMOS Device Type XCVxxxE

Stress Condition 110C, 85% RH Lot Quantity 1 Fail Quantity 0 Device Quantity 33 Total Device Cycles 8,712
XCV1000E
Table 2-99:
Device
HAST Test Results for Si Gate CMOS Device Type XCVxxxE (Shrink)
Stress Condition 130C, 85% RH 130C, 85% RH Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 45 45 Total Device Cycles 4,320 4,320
XCV400E XCV600E
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Table 2-99:
Device
HAST Test Results for Si Gate CMOS Device Type XCVxxxE (Shrink) (Contd)
XCV1000E XCVxxxE
Table 2-100:
Device XC3S1500
HAST Test Results for Si Gate CMOS Device Type XC3Sxxx

Table 2-101:
Device
HAST Test Results for Si Gate CMOS Device Type XC3SxxxA

XC3S1400A XC3SxxxA
Table 2-102:
Device
HAST Test Results for Si Gate CMOS Device Type XC3SDxxxA

XC3SD3400A XC3SDxxxxA
Table 2-103:
Device
HAST Test Results for Si Gate CMOS Device Type XC3SxxxAN

Table 2-104:
Device
HAST Test Results for Si Gate CMOS Device Type XC6Sxxx

Stress Condition 110C, 85% RH 130C, 85% RH 110C, 85% RH 130C, 85% RH Lot Quantity 1 6 3 1 11 Fail Quantity 0 0 0 0 0 Device Quantity 45 318 87 45 495 Total Device Cycles 11,880 30,420 22,968 4,320 69,588
XC6SLX25T XC6SLX45T XC6SLX150T XC6SLX150T XC6Sxxx
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Table 2-105:
Device
HAST Test Results for Si Gate CMOS Device Type XC4VLXxxx

XC4VLX100
Unbiased High Accelerated Stress Test

The HASTU test is conducted under the conditions of 130C, 85% RH or 110C, 85% RH. Package preconditioning is performed on the testing samples prior to the HAST test.
Summary
Table 2-106:
Device XC4xxxXLA XCSxxx XCSxxxXL XC2Sxxx XC2SxxxE XCVxxx XCVxxx (shrink) XCVxxxE XCVxxxE (shrink) XC3Sxxx XC3SxxxE XC3SxxxA XC3SxxxAN XC3SDxxxA XC6Sxxx XC4xXxxx XC5VxXxxx
HASTU Test Results for Si Gate CMOS Devices

Lot Quantity 1 3 3 4 8 2 1 1 3 16 13 5 6 5 7 2 2 Fail Quantity 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Device Quantity 45 135 180 180 330 89 45 49 133 720 585 225 202 225 420 90 90 Total Device Hours 4,320 12,960 17,280 17,280 31,680 8,544 4,320 12,936 12,768 69,120 51,840 21,600 19,392 21,600 40,320 8,640 8,640
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Data
Table 2-107:
Device XC4013XLA XC4xxxXLA
HASTU Test Results for Si Gate CMOS Device XC4xxxXLA

Table 2-108:
Device XCS10 XCS20 XCSxxx
HASTU Test Results for Si Gate CMOS Device Type XCSxxx

Table 2-109:
Device XCS05XL XCS20XL XCSxxxXL
HASTU Test Results for Si Gate CMOS Device Type XCSxxxXL

Table 2-110:
Device XC2S15 XC2S150 XC2Sxxx
HASTU Test Results for Si Gate CMOS Device Type XC2Sxxx

Table 2-111:
Device XC2S50E XC2S100E XC2S300E XC2SxxxE
HASTU Test Results for Si Gate CMOS Device Type XC2SxxxE

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FPGA Products
Table 2-112:
Device XCV100 XCV200 XCVxxx
HASTU Test Results for Si Gate CMOS Device Type XCVxxx

Table 2-113:
Device XCV400
HASTU Test Results for Si Gate CMOS Device Type XCVxxx (Shrink)
Table 2-114:
Device XCV812E
HASTU Test Results for Si Gate CMOS Device Type XCVxxxE

Table 2-115:
Device XCV600E XCV1000E XCVxxxE
HASTU Test Results for Si Gate CMOS Device Type XCVxxxE (Shrink)
Table 2-116:
Device XC3S1000 XC3S200 XC3S400 XC3S1500 XC3Sxxx

Table 2-117:
Device XC3S100E XC3S1200E XC3S500E
HASTU Test Results for Si Gate CMOS Device Type XC3SxxxE

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Table 2-117:
Device XC3S1600E XC3SxxxE
HASTU Test Results for Si Gate CMOS Device Type XC3SxxxE (Contd)
Table 2-118:
Device XC3S200A XC3S400A XC3S1400A XC3SxxxA
HASTU Test Results for Si Gate CMOS Device Type XC3SxxxA

Table 2-119:
Device
HASTU Test Results for Si Gate CMOS Device Type XC3SxxxAN

Table 2-120:
Device
HASTU Test Results for Si Gate CMOS Device Type XC3SDxxxA

Table 2-121:
Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX45T

Lot Quantity 1 1 1 3 1 7 Fail Quantity 0 0 0 0 0 0 Device Quantity 45 45 45 240 45 420 Total Device Hours 4,320 4,320 4,320 23,040 4,320 40,320
XC6SLX150T XC6Sxxx
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FPGA Products
Table 2-122:
Device XC4VSX25 XC4VSX35
HASTU Test Results for Si Gate CMOS Device Type XC4Vxxxx

XC4VxXxxx
Table 2-123:
Device
HASTU Test Results for Si Gate CMOS Device Type XC5Vxxxx

XC5VLX30T XC5VLX50T XC5VxXxxx
High-Temperature Storage Life

The High-Temperature Storage Life test is conducted under the conditions of 150C and with the device unbiased.
Summary
Table 2-124:
Device XC4xxxE XC4xxxXL XC4xxxXLA XCVxxx XCVxxxE XCVxxx (shrink) XCVxxxE (shrink) XC2Sxxx XC2SxxxE XC2Vxxx XC2VPxxx XC3Sxxx XC3SxxxE XC3SxxxA
Summary of High-Temperature Storage Life Test Results

Lot Quantity 2 1 2 2 1 1 4 4 10 4 1 19 19 5 Fail Quantity 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Device Quantity 90 45 90 90 80 45 178 180 449 180 49 855 854 225 Total Device Hours 90,000 48,240 90,000 90,000 80,480 45,000 178,000 181,080 450,080 180,000 49,747 855,000 854,135 225,000
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Table 2-124:
Device
Summary of High-Temperature Storage Life Test Results (Contd)

Lot Quantity 7 7 11 4 2 9 3 Fail Quantity 0 0 0 0 0 0 0 Device Quantity 313 230 400 139 90 198 75 Total Device Hours 313,000 230,000 400,522 139,000 90,900 198,677 75,000
XC3SDxxxA XC3SxxxAN XC6Sxxx XC4VxXxxx XC5VxXxxx XC6VxXxxx 7 Series FPGAs
Data
Table 2-125: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC4xxxE
Device XC4013E Lot Quantity 2 Fail Quantity 0 Device Quantity 90 Total Device Hours 90,000
Table 2-126: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC4xxxXL
Device XC4005XL XC4xxxXL Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 45 45 Total Device Hours 48,240 48,240
Table 2-127: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC4xxxXLA
Device XC4013XLA XC4020XLA XC4xxxXLA Lot Quantity 1 1 2 Fail Quantity 0 0 0 Device Quantity 45 45 90 Total Device Hours 45,000 45,000 90,000
Table 2-128: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XCVxxx
Device XCV50 XCV100 XCVxxx Lot Quantity 1 1 2 Fail Quantity 0 0 0 Device Quantity 45 45 90 Total Device Hours 45,000 45,000 90,000
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FPGA Products
Table 2-129: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XCVxxxE
Device XCV405E XCVxxxE Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 80 80 Total Device Hours 80,480 80,480
Table 2-130: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XCVxxx (Shrink)
Device XCV400 XCVxxx (shrink) Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 45 45 Total Device Hours 45,000 45,000
Table 2-131: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XCVxxxE (Shrink)
Device XCV400E XCV600E XCV1000E XCVxxxE (shrink) Lot Quantity 1 1 2 4 Fail Quantity 0 0 0 0 Device Quantity 44 44 90 178 Total Device Hours 44,000 44,000 90,000 178,000
Table 2-132: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC2Sxxx
Device XC2S15 XC2S150 XC2Sxxx Lot Quantity 2 2 4 Fail Quantity 0 0 0 Device Quantity 90 90 180 Total Device Hours 90,000 91,080 181,080
Table 2-133: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC2SxxxE
Device XC2S50E XC2S100E XC2S150E XC2S300E XC2SxxxE Lot Quantity 2 3 2 3 10 Fail Quantity 0 0 0 0 0 Device Quantity 90 135 90 134 449 Total Device Hours 90,000 135,000 91,080 134,000 450,080
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Table 2-134: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC2Vxxx
Device XC2V1000 XC2V1500 XC2Vxxxx Lot Quantity 2 2 4 Fail Quantity 0 0 0 Device Quantity 90 90 180 Total Device Hours 90,000 90,000 180,000
Table 2-135: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC2VPxxx
Device XC2VP100 XC2VPxxx Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 49 49 Total Device Hours 49,747 49,747
Device XC3S200 XC3S400 XC3S1000 XC3S1500 XC3Sxxx Lot Quantity 6 4 4 5 19 Fail Quantity 0 0 0 0 0 Device Quantity 270 180 180 225 855 Total Device Hours 270,000 180,000 180,000 225,000 855,000
Table 2-137: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC3SxxxE
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E XC3SxxxE Lot Quantity 6 3 4 2 4 19 Fail Quantity 0 0 0 0 0 0 Device Quantity 270 135 179 90 180 854 Total Device Hours 270,000 135,000 179,000 90,000 180,135 854,135
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FPGA Products
Table 2-138: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC3SxxxA
Device XC3S200A XC3S400A XC3S1400A XC3SxxxA Lot Quantity 1 2 2 5 Fail Quantity 0 0 0 0 Device Quantity 45 90 90 225 Total Device Hours 45,000 90,000 90,000 225,000
Table 2-139: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC3SDxxxA
Device XC3SD1800A XC3SD3400A XC3SDxxxA Lot Quantity 1 6 7 Fail Quantity 0 0 0 Device Quantity 43 270 313 Total Device Hours 43,000 270,000 313,000
Table 2-140: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC3SxxxAN
Device XC3S400AN XC3S1400AN XC3SxxxAN Lot Quantity 3 4 7 Fail Quantity 0 0 0 Device Quantity 84 146 230 Total Device Hours 84,000 146,000 230,000
Device XC6SLX9 XC6SLX16 XC6SLX25T XC6SLX150T XC6SLX45T XC6Sxxx Lot Quantity 4 1 1 2 3 11 Fail Quantity 0 0 0 0 0 0 Device Quantity 135 44 45 90 86 400 Total Device Hours 135,000 44,000 45,000 90,000 86,522 400,522
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Table 2-142: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type XC4VxXxxx
Device XC4VLX80 XC4VSX25 XC4VSX35 XC4VxXxxx Lot Quantity 2 1 1 4 Fail Quantity 0 0 0 0 Device Quantity 50 44 45 139 Total Device Hours 50,000 44,000 45,000 139,000
Device XC5VLX30T XC5VLX50T XC5VxXxxx Lot Quantity 1 1 2 Fail Quantity 0 0 0 Device Quantity 45 45 90 Total Device Hours 45,900 45,000 90,900
Device XC6VHX255T XC6VLX115T(1) XC6VLX130T XC6VxXxxx
Notes:
1. XC6VLX115T is an internal product qualification vehicle.
Lot Quantity 3 3 3 9
Fail Quantity 0 0 0 0
Device Quantity 72 45 81 198
Total Device Hours 72,000 45,000 81,677 198,677
Table 2-145: High-Temperature Storage Life Test Results of Si Gate CMOS Device Type 7 Series FPGAs
Device XC7K325T 7 Series FPGAs Lot Quantity 3 3 Fail Quantity 0 0 Device Quantity 75 75 Total Device Hours 75,000 75,000
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Flash PROM Products

HTOL Test
The HTOL test is conducted under the conditions of TJ > 125C temperature, maximum VDD, and either dynamic or static operation. The FIT failure rate calculation in the following tables is based on the assumption of 0.7 eV activation energy and 60% confidence level (CL).
Summary
Table 2-146: Summary of HTOL Test Results
Lot Quantity 10 13 16 12 Fail Quantity 0 0 0 0 Device Quantity 445 584 715 482 Failure Rate Actual Device Equivalent at 60% CL Device Hours Hours at and TJ = 55C TJ > 125C at TJ = 125C (FIT) 898,995 969,015 760,225 1,067,500 1,069,747 1,070,586 1,004,700 1,105,652 23 23 25 22
Device
XC17(S)xxx/(X)L XC17Vxxx/XC17SxxxA XC18Vxxx XCFxxxS/P
Data
Table 2-147:
Device XC1702L XC1704L XC17S30XL XC17S40XL XC17Sxx/XL
HTOL Test Results for 0.6 m Si Gate CMOS Device Type XC17(S)xxx/(X)L
Table 2-148:
Device XC17V04 XC17V08 XC17V16 XC17S50A XC17Vxx/ XC17SxxxA
HTOL Test Results of 0.35 m Si Gate CMOS Device Type XC17Vxx/XC17SxxxA

Lot Quantity 6 3 3 1 13 Fail Quantity 0 0 0 0 0 Device Quantity 268 135 136 45 584 Actual Device Hours at TJ > 125C 4,080,015 275,856 195,144 90,000 969,015 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 478,847 298,948 202,791 90,000 1,070,586 23 FIT
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Table 2-149:
Device XC18V02 XC18V04 XC18V512 XC18Vxxx
HTOL Test Results for 0.15 m Si Gate CMOS Device Type 18Vxxx
Table 2-150:
Device XCF08P XCF16P XCF32P XCF128X XCFxxxS/P
HTOL Test Results for 0.15 m Si Gate CMOS Device Type XCFxxxS/P
Lot Quantity 2 4 5 1 12 Fail Quantity 0 0 0 0 0 Device Quantity 90 122 225 45 482 Actual Device Hours at TJ > 125C 90,000 730,000 225,000 22,500 1,067,500 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 90,000 730,000 263,152 22,500 1,105,652 22 FIT

The THB test is conducted under the conditions of 85C, 85% RH, and VDD bias. Package preconditioning is performed on the testing samples prior to the THB test.
Summary
Table 2-151: Summary of THB Test Results
Device XC17(S)xxx/(X)L/E XC17Vxxx/XC17Sxxx A XCFxxxS/P
Data
Table 2-152: THB Test Results for Si Gate CMOS Device Type XC17(S)xxx/(X)L/E
Device XC17S50XL XC17(S)xxx/(X)L/E
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Table 2-153: THB Test Results for Si Gate CMOS Device Type XC17Vxxx/XC17SxxxA
Device XC17S15A XC17Vxxx/XC17SxxxA Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 45 45 Total Device Hours 46,530 46,530
Table 2-154:
THB Test Results of Si Gate CMOS Device Type XCFxxxS/P

Device XCF16P XCF32P XCFxxxS/P

The TH test is conducted under the conditions of 85C and 85% RH. Package preconditioning is performed on the testing samples prior to the TH test.
Summary
Table 2-155: Summary of TH Test Results
Device XC17Vxxx
Data
Table 2-156: TH Test Results of Si Gate CMOS Device Type XC17Vxxx/XC17SxxxA
Device XC17S100A XC17Vxxx/XC17SxxxA
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Temperature Cycling Tests

The temperature cycling test is conducted under the conditions of predefined maximum and minimum temperatures and in an air-to-air environment. Package precondition is performed on the testing samples prior to the temperature cycling test.
Summary
Table 2-157: Summary of Temperature Cycling Test Results
Lot Quantity 2 2 9 10 Fail Quantity 0 0 0 0 Device Quantity 90 90 390 482 Total Device Cycles 90,000 90,000 390,000 780,380
Device XC17(S)xxx/(X)L/E XC17Vxxx/XC17SxxxA XC18Vxxx XCFxxxS/P
Data
Table 2-158:
Device XC1702L XC17S50XL XC17(S)xxx/(X)L/E
Temperature Cycling Test Results for Si Gate CMOS Device XC17(S)xxx/(X)L/E

Table 2-159:
Temperature Cycling Test Results for Si Gate CMOS Device Type XC17Vxxx/XC17SxxxA
Device XC17S200A XC17Vxxx/XC17SxxxA
Table 2-160:
Temperature Cycling Test Results for Si Gate CMOS Device Type XC18Vxxx
Stress Condition C: 65C to +150C C: 65C to +150C C: 65C to +150C C: 65C to +150C C: 65C to +150C Lot Quantity 2 4 2 1 9 Fail Quantity 0 0 0 0 0 Device Quantity 90 165 90 45 390 Total Device Cycles 90,000 165,000 90,000 45,000 390,000
Device XC18V01 XC18V02 XC18V04 XC18V512 XC18Vxxx
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Flash PROM Products
Table 2-161:
Temperature Cycling Test Results for Si Gate CMOS Device Type XCFxxxS/P
Stress Condition C: 65C to +150C C: 65C to +150C C: 65C to +150C Lot Quantity 2 8 10 Fail Quantity 0 0 0 Device Quantity 90 392 482 Total Device Cycles 90,000 636,380 780,380
Autoclave Test
Summary
Table 2-162: Summary of Autoclave Test Results
Device XC17(S)xxx/(X)L/E XC17Vxxx/XC17SxxxA XCFxxx
Data
Table 2-163: Autoclave Test Results for Si Gate CMOS Device Type XC17(S)xxx/(X)L/E
Device XC1702L XC17(S)xxx/(X)L/E Lot Quantity 1 1 Fail Quantity 0 0 Device Quantity 43 43 Total Device Hours 4,128 4,128
Table 2-164: Autoclave Test Results for Si Gate CMOS Device Type XC17Vxxx/XC17SxxxA
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Table 2-165:
Autoclave Test Results for Si Gate CMOS Device Type XCFxxx

Device XCF16P XCF32P XCFxxx
High Accelerated Stress Test

The HAST test is conducted under the conditions of 130C, 85% RH, and VDD bias. Package preconditioning is performed on the testing samples prior to the HAST test.
Summary
Table 2-166:
Device XC18Vxxx XCFxxx
Summary of HAST Test Results

Data
Table 2-167:
HAST Test Results for Si Gate CMOS Device Type XC18Vxxx

Stress Condition 130C, 85% RH 130C, 85% RH 130C, 85% RH 130C, 85% RH 130C, 85% RH Lot Quantity 1 2 4 2 9 Fail Quantity 0 0 0 0 0 Device Quantity 45 90 180 90 405 Total Device Cycles 4,320 8,640 17,280 8,640 38,880
Table 2-168:
Device XCF01S XCF04S XCFxxx
HAST Test Results for Si Gate CMOS Device Type XCFxxx

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The HASTU test is conducted under the conditions of 130C, 85% RH or 110C, and 85% RH. Package preconditioning is performed on the testing samples prior to the HASTU test.
Summary
Table 2-169: Summary of HASTU Test Results
Data
Table 2-170:
Device XC1702L XC17Sxxx/XL
HASTU Test Results for Si Gate CMOS Device Type XC17Sxxx/XL

Table 2-171:
Device XC17S200A XC17SxxxA
HASTU Test Results for Si Gate CMOS Device Type XC17SxxxA

Table 2-172:
HASTU Test Results for Si Gate CMOS Device Type XC18Vxxx

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Table 2-173:
Device XCF01S XCF04S XCF08P XCF16P XCF32P XCFxxx
HASTU Test Results for Si Gate CMOS Device Type XCFxxx

Lot Quantity 1 1 2 2 3 9 Fail Quantity 0 0 0 0 0 0 Device Quantity 45 45 90 90 180 405 Total Device Hours 4,320 4,320 8,640 8,640 12,960 34,560
Program/Erase Endurance Test

The Program/Erase Endurance test is conducted under nominal voltage and room temperature.
Qualification Data
Table 2-174: Program/Erase Endurance Test Results of Si Gate CMOS Device Type XC18Vxxx/XCFxxxS/P
Device XC18V04 XCF08P XCF16P XCF32P Lot Quantity 1 1 2 2 Fail Quantity 0 0 0 0 Device Quantity 32 16 93 93 Total Device Hours 640,000 320,000 1,860,000 1,860,000
Data Retention Bake Test

The data retention bake test is conducted at 150C ambient temperature. The devices are programmed prior to the bake test.
Summary
Table 2-175: Summary of Data Retention Bake Test Results
Lot Quantity 2 3 8 10 Fail Quantity 0 0 0 0 Device Quantity 89 135 355 1,210 Total Device Hours 89,000 135,900 355,000 2,018,280
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Data
Table 2-176: Data Retention Bake Test Results for Si Gate CMOS Device Type XC17(S)xxx/(X)L/E
Device XC1702L XC17S50XL XC17(S)xxx/(X)L/E Lot Quantity 1 1 2 Fail Quantity 0 0 0 Device Quantity 45 44 89 Total Device Cycles 45,000 44,000 89,000
Table 2-177: Data Retention Bake Test Results for Si Gate CMOS Device Type XC17Vxxx/XC17SxxxA
Table 2-178: XC18Vxxx
Data Retention Bake Test Results for Si Gate CMOS Device Type
Device XC18V01 XC18V02 XC18V04 XC18Vxxx
Table 2-179: XCFxxxS/P
Lot Quantity 1 9 10 Fail Quantity 0 0 0 Device Quantity 45 1,165 1,210 Total Device Hours 45,000 1,943,220 2,018,280
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CPLD Products
HTOL Tests
The HTOL test is conducted under the conditions of TJ > 125C temperature, maximum VDD, and either dynamic or static operation. The FIT calculations in Table 2-180 through Table 2-185 are based on the assumption of 0.7 eV activation energy and 60% confidence level.
Summary
Table 2-180:
Device XC95xxx XC95xxxXL XC95xxxXV XCRxxxXL XC2Cxxx/A
Notes:
Summary of HTOL Test Results

Lot Quantity 8 20 14 13 13 Fail Quantity 0 0 0 1 0 Device Quantity 345 1,101 746 615 728 Actual Device Hours at TJ > 125C 673,885 1,533,959 982,430 1,034,982 1,007,075 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 1,016,513 2,151,754 1,028,282 1,036,168 1,036,246 12 5 11 25 11
Data
Table 2-181:
Device XC95108 XC95288 XC9572 XC95xxx
HTOL Test Results for 0.5 m Si Gate CMOS Device Type XC95xxx
Table 2-182:
Device XC951288XL XC95144XL XC95288XL XC9572XL XC95xxxXL
HTOL Test Results of 0.35 m Si Gate CMOS Device Type XC95xxxXL

Lot Quantity 1 7 8 4 20 Fail Quantity 0 0 0 0 0 Device Quantity 45 344 472 240 1,101 Actual Device Hours at TJ > 125C 90,630 482,312 611,310 349,881 1,533,959 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 231,398 664,712 821,688 433,956 2,151,754 5 FIT
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CPLD Products
Table 2-183:
Device XC9572XV XC95144XV XC95288XV XC95xxxXV
HTOL Test Results of 0.25 m Si Gate CMOS Device Type XC95xxxXV

Table 2-184:
Devices XCR3032XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL XCRxxxXL
Notes:
HTOL Test Results of 0.35 m Si Gate CMOS Device Type XCRxxxXL

Lot Quantity 1 3 4 3 2 13 Failures 0 0 1(1) 0 0 1 Device on Test 76 135 180 132 92 615 Actual Device Hours at TJ > 125C 152,076 270,855 292,393 175,302 144,356 1,034,982 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 152,076 271,487 292,767 175,482 144,356 1,036,168 25 FIT
1. Inter-layer dielectric (ILD) defect at M2 to M1 at post 48 hours.
Table 2-185:
Device XC2C64A XC2C128 XC2C256 XC2C384 XC2C512 XC2Cxxx/A
HTOL Test Results of 0.18 m Si Gate CMOS Device Type XC2Cxxx/A

Lot Quantity 2 1 3 6 1 13 Fail Quantity 0 0 0 0 0 0 Device Quantity 154 45 167 350 44 728 Actual Device Hours at TJ > 125C 154,000 91,260 257,186 469,865 44,000 1,007,075 Equivalent Failure Rate at Device Hours 60% CL and at TJ = 125C TJ = 55C (FIT) 154,000 91,339 258,179 496,699 45,029 1,036,246 11 FIT
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The THB test is conducted under the conditions of 85C, 85% RH, and VDD bias. Package preconditioning is performed on the testing samples prior to the THB test.
Summary
Table 2-186:
Device XC95xxxXL XC95288XV XC2Cxxx/A
Summary of THB Test Results

Data
Table 2-187:
Device XC95144XL XC95xxxXL
THB Test Results for Si Gate CMOS Device Type XC95xxxXL

Table 2-188:
Device XC95288XV
THB Test Results for Si Gate CMOS Device Type XC95xxxXV

Table 2-189:
Device XC2C64A XC2C128 XC2C256
THB Test Results for Si Gate CMOS Device Type XC2Cxxx/A

XC2Cxxx/A
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The TH test is conducted under the conditions of 85C and 85% RH. Package preconditioning is performed on the testing samples prior to the TH test.
Summary
Table 2-190:
Device XC95xxx XC95xxxXL XCRxxxXL XC2Cxxx/A
Summary of TH Test Results

Data
Table 2-191:
Device XC95144 XC95xxx
TH Test Results of Si Gate CMOS Device Type XC95xxxx

Table 2-192:
Device XC9572XL XC95144XL XC95xxxXL
TH Test Results of Si Gate CMOS Device Type XC95xxxXL (Shrink)

Table 2-193:
Device
TH Test Results of 0.35 m Si Gate CMOS Device Type XCRxxxXL

XCR3256XL XCRxxxXL
Table 2-194:
Device XC2C64A XC2C256
TH Test Results of Si Gate CMOS Device Type XC2Cxxx/A

XC2Cxxx/A
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Temperature Cycling Test

The temperature cycling test is conducted under the conditions of predefined maximum and minimum temperatures and in air-to-air environment. Package precondition is performed on the testing samples prior to the temperature cycling test.
Summary
Table 2-195:
Summary of Temperature Cycling Test Results

Lot Quantity 2 7 1 1 26 Fail Quantity 0 0 0 0 0 Device Quantity 90 315 45 45 1,167 Total Device Cycles 90,000 316,350 45,360 45,000 1,124,250
Data
Table 2-196:
Temperature Cycling Test Results for Si Gate CMOS Device Type XC95xxx
Table 2-197:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC95xxxL
XC95144XL XC95288XL XC9572XL XC95xxxXL
Table 2-198:
Device
Temperature Cycling Test Results for Si Gate CMOS Device Type XC95xxxXV
XC95288XV
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Table 2-199:
Device XCR3256X
Temperature Cycling Test Results of Si Gate CMOS Device Type XCRxxxXL

XCRxxxXL
Table 2-200:
Device XC2C64A XC2C32A XC2C64 XC2C128 XC2C256 XC2C384
Temperature Cycling Test Results of Si Gate CMOS Device Type XC2Cxxx/A

Stress Condition B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C B: 55C to +125C Lot Quantity 4 4 1 7 8 2 26 Fail Quantity 0 0 0 0 0 0 0 Device Quantity 180 180 45 314 358 90 1,167 Total Device Cycles 182,250 180,000 45,000 314,000 358,000 90,000 1,124,250
XC2Cxxx/A
Autoclave Test
Summary
Table 2-201:
Device XC95xxxXL XC2Cxxx
Summary of Autoclave Test Results

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Data
Table 2-202:
Device XC9572XL
Autoclave Test Results for Si Gate CMOS Device Type XC95xxxXL

Table 2-203:
Device XC2C128
Autoclave Test Results for Si Gate CMOS Device Type XC2Cxxx


The HASTU test is conducted under the conditions of 130C and 85% RH or 110C and 85% RH. Package preconditioning is performed on the testing samples prior to the HASTU test.
Summary
Table 2-204:
HASTU Test Results for Si Gate CMOS Devices

Lot Quantity 2 7 1 1 22 Fail Quantity 0 0 0 0 0 Device Quantity 90 314 28 45 990 Total Device Cycles 8,640 30,144 2,688 4,320 95,040
Data
Table 2-205:
HASTU Test Results for Si Gate CMOS Device Type XC95xxx

Lot Quantity 2 2 Fail Quantity 0 0 Device Quantity 90 90 Total Device Cycles 8,640 8,640
Table 2-206:
Device XC95144XL XC95288XL
HASTU Test Results for Si Gate CMOS Device Type XC95xxxXL

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CPLD Products
Table 2-206:
Device XC9572XL XC95xxxXL
HASTU Test Results for Si Gate CMOS Device Type XC95xxxXL

Table 2-207:
Device XC95144XV
HASTU Test Results for Si Gate CMOS Device Type XC95xxxXV

XC95xxxXV
Table 2-208:
Device
HASTU Test Results for Si Gate CMOS Device Type XCRxxxXL

XCR3256XL XCRxxxXL
Table 2-209:
Device XC2C128 XC2C256 XC2C384 XC2C32A XC2C64A
HASTU Test Results for Si Gate CMOS Device Type XC2Cxxx/A

Lot Quantity 7 6 2 4 3 22 Fail Quantity 0 0 0 0 0 0 Device Quantity 315 270 90 180 135 990 Total Device Cycles 30,240 25,920 8,640 17,280 12,960 95,040
XC2Cxxx/A
Program/Erase Endurance Test

The Program/Erase Endurance test is conducted under nominal voltage and predefined temperature.
Qualification Data
Table 2-210: Erase Endurance Test Results for Si Gate CMOS Device Type XC95xxx; Test Condition at 55C
Device XC9536 XC95108 XC95xxx Lot Quantity 1 1 2 Fail Quantity 0 0 0 Device Quantity 29 80 109 Total Device Hours 290,000 875,120 1,165,120
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Table 2-211: Erase Endurance Test Results for Si Gate CMOS Device Type XC95xxx; Test Condition at 40C
Device XC9536 Lot Quantity 2 Fail Quantity 0 Device Quantity 64 Total Device Hours 5,088,000
Table 2-212: Erase Endurance Test Results for Si Gate CMOS Device Type XC95xxxXL; Test Condition at 40C
Device XC95144XL Lot Quantity 1 Fail Quantity 0 Device Quantity 21 Total Device Hours 420,000
Table 2-213: Erase Endurance Test Results for Si Gate CMOS Device Type XC95xxxXL; Test Condition at 70C
Device XC95144XL Lot Quantity 1 Fail Quantity 0 Device Quantity 32 Total Device Hours 320,000
Table 2-214: Erase Endurance Test Results for Si Gate CMOS Device Type XC95xxxXV; Test Condition at 70C
Device XC95144XV Lot Quantity 1 Fail Quantity 0 Device Quantity 32 Total Device Hours 320,000
Table 2-215: XCRxxx/XL

Device XCR3128
Erase Endurance Test Results of Si Gate CMOS Device Type

XCR3032XL
Data Retention Bake Test

The Data Retention Bake Test is conducted at 150C. The devices are programmed prior to the bake test.
Summary
Table 2-216:
Device XC95xxx XC95xxxXL XC95xxxXV
Summary of Data Retention Bake Test Results

Lot Quantity 3 7 1 Fail Quantity 0 0 1(1) Device Quantity 135 315 43 Total Device Hours 135,000 315,000 42,671
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CPLD Products
Table 2-216:
Device XCRxxxXL
Summary of Data Retention Bake Test Results (Contd)

Lot Quantity 2 28 Fail Quantity 0 0 Device Quantity 90 1,260 Total Device Hours 90,000 1,221,480
XC2Cxxx/A
Notes:
Data
Table 2-217: XC95xxx
Table 2-218: XC95xxxXL

Device XC9572XL XC95144XL XC95288XL XC95xxxXL
Table 2-219: Data Retention Bake Test Results for Si Gate CMOS Device Type XC95xxxXV
Device XC95144XV XC95xxxXV
Notes:
1. The device failure was due to a bond ball alignment issue. An improvement process change has been implemented.
Lot Quantity 1 1
Fail Quantity 1(1) 1
Device Quantity 43 43
Total Device Hours 42,671 42,671
Table 2-220: XCRxxxXL

Device
Data Retention Bake Test Results of Si Gate CMOS Device Type

XCR3128XL
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Table 2-220: Data Retention Bake Test Results of Si Gate CMOS Device Type XCRxxxXL (Contd)
Device XCR3256XL XCRxxxXL Lot Quantity 1 2 Fail Quantity 0 0 Device Quantity 45 90 Total Device Hours 45,000 90,000
Table 2-221: XC2Cxxx/A

Device XC2C64 XC2C128 XC2C256 XC2C384 XC2C32A XC2C64A
Data Retention Bake Test Results of Si Gate CMOS Device Type

Lot Quantity 1 9 9 2 4 3 28 Fail Quantity 0 0 0 0 0 0 0 Device Quantity 45 405 405 90 180 135 1,260 Total Device Hours 45,000 363,240 408,240 90,000 180,000 135,000 1,221,480
XC2Cxxx/A
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Chapter 3
Results by Package Type

Reliability Data for Non-Hermetic Packages
PD8
Table 3-1: Test Results for Device Types XC17256E, XC17S200A, XC17S40XL, and XC17S10
Reliability Test
Temperature cycling
Lot Quantity 1 1 1
Failures 0 0 0
Device on Test 45 45 45
Total Device Hours/Cycles 45,000 45,000 4,320
55C to +125C HTS HASTU
SO20
Table 3-2: Test Results for Device Types XC17S50A, XC17S100A/XL, and XC18V01
Reliability Test
Temperature cycling 55C to +125C
Lot Quantity 1 1 1
Failures 0 0 0
Temperature humidity 85C, 85% RH with bias HTS
VO20 and VO48

Table 3-3: Test Results for Device Types XCF08P, XCF32P, XC18V01, XC18V02, and XC18V04
Reliability Test
Temperature cycling
Lot Quantity 2 2
Failures 0 0
Device on Test 90 90
Total Device Hours/Cycles 144,000 150,120
65C to +150C Temperature humidity 85C, 85% RH with bias
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Table 3-3:
Test Results for Device Types XCF08P, XCF32P, XC18V01, XC18V02, and XC18V04 (Contd)
Reliability Test PP HTS Lot Quantity 2 1 Failures 0 0 Device on Test 90 45 Total Device Hours/Cycles 8,640 75,060
PC44, PC84, and PC20

Table 3-4: Test Results for Device Types XC1704L, XC17V16, XC18V04, XC9572XL, XCR3064XL, XCS05, XCS10XL, and XC4006E
Reliability Test
Lot Quantity 1 1 1
Failures 0 0 0
HASTU HTS
PQ100, PQ160, PQ208, PQ240

Table 3-5: Test Results for Device Types XC3S200, XC2S300E, XC4013E, XC4010XL, XC3S1500, XC95144, XC95216, XC95288XL, XC95288XV, XCR3512XL, and XCR3384XL
Reliability Test
Lot Quantity 5 1 1 2 4
Failures 0 0 0 0 0
Device on Test 229 45 33 90 180
Total Device Hours/Cycles 229,000 45,000 33,198 8,640 180,000
Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias HASTU HTS
TQ100, TQ144
Table 3-6: Test Results for Device Types XC2C256, XC2C384, XC2S50E, XC2S100/E, XC3S50A, XC3S200, XC3S400, and XC95288XL
Reliability Test
Lot Quantity 6 1
Failures 0 0
Autoclave 121C, 100% RH
86
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Table 3-6: Test Results for Device Types XC2C256, XC2C384, XC2S50E, XC2S100/E, XC3S50A, XC3S200, XC3S400, and XC95288XL (Contd)
Reliability Test Temperature humidity 85C, 85% RH no bias HASTU HTS Lot Quantity 2 3 7 Failures 0 0 0 Device on Test 75 134 270 Total Device Hours/Cycles 75,600 12,864 273,240
VQ44, VQ100
Table 3-7: Test Results for Device Types XC1702L, XC17V04, XC18V02, XC18V04, XC2C128, XCS30, XCS20XL, XC9572XL, XC3S200, and XC3S250E
Reliability Test
Failures 0 0 0 0 0
Device on Test 135 42 62 225 135
Autoclave 121C, 100% RH Temperature humidity 85C, 85% RH no bias HASTU HTS
HQ208, HQ240
Table 3-8: Test Results for Device Types XCV400 (Shrink), XCV600 (Shrink), XCV600E, XC95216, XC95288, and XC4028EX
Reliability Test
Failures 0 0 0 0
Device on Test 45 40 45 45
Total Device Hours/Cycles 45,000 40,240 45,000 45,000
Temperature humidity 85C, 85% RH no bias HASTU HTS
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87
BG256
Table 3-9: Test Results for Device Type XCS40XL
Reliability Test
Lot Quantity 1 1 1
Failures 0 0 0
HTS HASTU
BG352, BG432, BG560

Table 3-10: Test Results for Device Types XCV1000E, XC1600E, XC4052XLA, XC4062XLA, and XCV300
Lot Quantity 1 2 1 1 2 Failures 0 0 0 0 0 Device on Test 45 79 45 45 90 Total Device Hours/Cycles 45,000 79,720 4,320 45,000 90,810
Reliability Test
Temperature humidity 85C, 85% RH with bias HASTU HTS Temperature humidity 85C, 85% RH no bias
CS280
Table 3-11: Test Results for Device Types XC95288XL, XC95288XV, XCR3256XL, and XCR3512XL
Lot Quantity 2 1 1 2 Failures 0 0 0 0 Device on Test 90 24 45 90 Total Device Hours/Cycles 90,000 24,240 4,320 90,000
Reliability Test
Temperature humidity 85C, 85% RH no bias HASTU HTS
88
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CS324
Table 3-12: Test Results for Device Types XC6SLX16, XC6SLX45T, and XC6SLX45
Lot Quantity 3 9 Failures 0 0 Device on Test 86 295 Total Device Hours/Cycles 8,148 299,013
Reliability Test HAST

CP56
Table 3-13: Test Results for Device Type XCR3064XL
Lot Quantity 1 1 1 Failures 0 0 0 Device on Test 77 77 77 Total Device Hours/Cycles 88,088 77,539 7,392
Reliability Test
HTS HASTU
CP132
Table 3-14: Test Results for Device Types XC2C128, XC2C256, and XC2S300E
Reliability Test
Temperature humidity 85C, 85% RH with bias HASTU HTS
FS48
Table 3-15: Test Results for Device Types XCF08P, XCF16P, and XCF32P
Lot Quantity 7 8 8 8 Failures 0 0 0 0 Device on Test 424 424 822 1,120 Total Device Hours/Cycles 561,320 707,232 78,912 1,868,160
Reliability Test
Temperature humidity 85C, 85% RH with bias PP HTS
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89
FG256
Table 3-16: Test Results for Device Types XC2V80, XC2V250, XC2V500, and XCV1000
Lot Quantity 1 Failures 0 Device on Test 45 Total Device Hours/Cycles 4,320
Reliability Test HASTU
FG320
Table 3-17: Test Results for Device Types XC3S1500
Reliability Test HTS

Temperature humidity 85C, 85% RH no bias
FG324, FG456, FG484

Table 3-18: Test Results of Device Types XC2V250, XC3S1000, XC3S1500, XC6SLX45T, XC6SLX150T, XC2S300E, and XCR3512XL
Reliability Test
Lot Quantity 7 1 7 5 8 2
Failures 0 0 0 0 0 0
Device on Test 418 30 364 330 311 90
Total Device Hours/Cycles 426,466 30,150 49,560 31,680 312,602 90,000
Temperature humidity 85C, 85% RH no bias HAST HASTU HTS THB
FG676
Table 3-19: Test Results for Device Types XC2VP20, XC3S1400A, XC3S1500, XC3SD1800A, XC6SLX150T, XC3SD3400A, XCE2V2000, and XCV600E
Reliability Test
Lot Quantity 8 4
Failures 0 0
HAST
90
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Table 3-19: Test Results for Device Types XC2VP20, XC3S1400A, XC3S1500, XC3SD1800A, XC6SLX150T, XC3SD3400A, XCE2V2000, and XCV600E (Contd)
Reliability Test HASTU HTS Lot Quantity 4 5 Failures 0 0 Device on Test 180 222 Total Device Hours/Cycles 17,280 222,000
FG680
Table 3-20: Test Results for Device Types XCV2000E, and XCV1000E
Reliability Test
HASTU HTS
FG900
Table 3-21: Test Results for Device Type XC6SLX150T
Reliability Test
FG1156
Table 3-22: Test Results for Device Types XCV2000E, and XCV1600E
Reliability Test
FT256
Table 3-23: Test Results for Device Types XCR3512XL, XC2S150E, XC2S300E, XC2S400E, XC2C512, XC3S1000, XC3S400A, XC3S1200E, XC3S200AN, XC3S200, XC3S50A, and XC3S200A
Reliability Test Temperature cycling 55C to +125C Autoclave 121C, 100% RH HASTU Lot Quantity 3 1 3 Failures 0 0 0 Device on Test 135 44 135 Total Device Hours/Cycles 136,080 4,224 12,960
www.xilinx.com
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Table 3-23: Test Results for Device Types XCR3512XL, XC2S150E, XC2S300E, XC2S400E, XC2C512, XC3S1000, XC3S400A, XC3S1200E, XC3S200AN, XC3S200, XC3S50A, and XC3S200A (Contd)
Reliability Test Temperature humidity 85C, 85% RH no bias HTS Lot Quantity 1 3 Failures 0 0 Device on Test 45 134 Total Device Hours/Cycles 47,745 134,000
FF668
Table 3-24: Test Results for Device Types XC4VLX25, XC4VLX60, and XC4VFX20
Reliability Test HASTU

Temperature humidity 85C, 85% RH with bias HTS
FF484, FF784
Table 3-25: Test Results for Device Types XC6VLX130T and XC6VLX240T
Reliability Test TCB
FF1136, FF1148, FF1152

Table 3-26: Test Results for Device Types XC4VLX60, XC4VLX100, XC4VLX160, XC4VFX60, XC2VP20, XC2VP50, XC2V6000, XC2V8000, XC2V4000, XC5VSX95T, XC5VLX50T, and XC5VLX110T
Failures 0 0 0 0
HASTU Temperature humidity 85C, 85% RH with bias
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FF1156
Table 3-27: Test Results for Device Types XC6VSX475T, XC6VLX240T, XC6VLX115T(1), XC6VLX195T and XC6VLX130T
TCB
Failures 0 0 0 0
TH THB
Notes:
FF1923
Table 3-28: Test Results for Device Types XC6VHX565T, XC6VHX255T and XC6VHX380T
Lot Quantity 9 3 3 3 Failures 1(1) 0 0 0 Device on Test 148 74 74 72 Total Device Hours/Cycles 148,000 74,000 74,000 72,000
Reliability Test
Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias High temperature storage
Notes:
1. One unit failed at post temperature cycling stress was due to a solder particle at bump. Post bump cleaning improvement is being implemented.
FF1513, FF1517
Table 3-29: Test Results for Device Types XC2V6000, XC2V8000, XC2VP50, XC2VP70, XC4VLX100, XC4VLX200, XC4VLX160, and XC4VLX200
Reliability Test HTS HASTU
Lot Quantity 1 1 1
Failures 0 0 0
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FF1704
Table 3-30: Test Results for Device Types XC2VP100 and XC2VP70

FF1759, FF1760
Table 3-31: Test Results for Device Types XC6VLX240T, XC6VLX475T and XC6VLX760
Reliability Test
TCB
SF363
Table 3-32: Test Results for Device Type XC4VLX25
Reliability Test
Temperature humidity 85C, 85% RH with bias
Reliability Data for Hermetic Packages

Reliability Data for PGA Packages
Table 3-33: Tests of Package Types PG84, PG120, PG132, PG156, PG175, PG191, PG223, PG299, and PG475
Code B2 B3 B5 D1 D2 Test Resistance to solvents Solderability Bond strength Physical dimension Lead integrity Seal Sample Quantity 15 15 24 30 30 Failures 0 0 0 0 0 Total Device Cycles
94
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Table 3-33: Tests of Package Types PG84, PG120, PG132, PG156, PG175, PG191, PG223, PG299, and PG475 (Contd)
Code Test Thermal shock Temperature cycle D3 Seal Visual examination End-point electrical Parametrics Mechanical shock Vibration, variable frequency D4 Constant acceleration Seal Visual examination End-point electrical parameters Salt atmosphere D5 Seal Visual examination D6 D7 D8 Internal water-vapor content Adhesion of lead finish Lid Torque 30 30 15 0 0 0 30 0 30 0 Sample Quantity 30 Failures 0 Total Device Cycles 450
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95
Reliability Data for CB Packages

Table 3-34:
Code B2 B3 B5 D1 D2
Tests of Package Types CB-100, CB164, CB196, and CB228

Test Resistance to solvents Solderability Bond strength Physical dimension Lead integrity Seal Thermal shock Temperature cycle 60 0 Sample Quantity 48 27 36 60 60 Failures 0 0 0 0 0 Total Device Cycles
D3
Seal Visual examination End-Point electrical Parametrics Mechanical shock Vibration, variable frequency 60 0
D4
Constant acceleration Seal Visual examination End-point electrical parameters Salt atmosphere 60 0
D5
Seal Visual examination
D6 D7 D8-LID HTOL
Internal water-vapor content Adhesion of lead finish Lid Torque Life Test
60 60 30 45
0 0 0 0
96
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Reliability Data for DD8 Packages

Table 3-35:
Code B2 B3 B5 D1 D2
Tests of Package Type DD8

Test Resistance to solvents Solderability Bond strength Physical dimension Lead integrity Seal Thermal shock Temperature cycle 30 0 225 1,500 Sample Quantity 9 9 12 30 30 Failures 0 0 0 0 0 Total Device Cycles
D3
Seal Visual examination End-point electrical Parametrics Mechanical shock Vibration, variable frequency 30 0
D4
D5
D6 D7 D8
Internal water-vapor content Adhesion of lead finish Lead torque
30 30 15
0 0 0
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Reliability Data for Chip Scale CC44 Package

Table 3-36:
Code B2 B3 B5 D1 D2
Tests of Package Type Chip Scale CC44

Test Resistance to solvents Solderability Bond strength Physical dimension Lead integrity Seal Thermal shock Temperature cycle 30 0 675 4,500 Sample Quantity 9 9 12 15 15 Failures 0 0 0 0 0 Total Device Cycles
D3
Seal Visual examination End-point electrical Parametrics Mechanical shock Vibration, variable frequency 15 0
D4
D5
D6 D7 D8
Internal water-vapor content Adhesion of lead finish Lead torque
20 18 15
0 0 0
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Reliability Data for Pb-Free Packages
Reliability Data for CF1144 Package

Table 3-37:
Code
Tests of Package Type CF1144

Test Thermal shock Parametrics Mechanical shock High temperature storage 15 22 15 18 14 0 0 0 0 0 2,112 1,500 1,728 29,260 Sample Quantity 15 Failures 0 Total Device Hours/Cycles 225
D3
D4
Temperature cycling 65 to +155C
HAST (130C, 85% RH) TCB

Temperature cycling -55 to +125C
Reliability Data for CG717 Package

Table 3-38:
Code
Tests of Package Type CG717

Test Thermal shock Mechanical shock Vibration High temperature storage
Temperature cycling 65 to +155C
Sample Quantity 15 15 15 22 15 44
Total Device Hours/Cycles 225
225 2,112 1,500 44,000
HTOL

PDG8
Table 3-39: Test Results for Device Types XC17256E and XC17S200A
Reliability Test TCB HASTU HTS
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BGG256
Table 3-40: Test Results for Device Type XCS40XL
Reliability Test
Temperature cycling
55 to +125C HTS HASTU
BGG352, BGG432, BGG560

Table 3-41: XC4062XL Test Results for Device Types XCV300E (Shrink), XCV600E (Shrink), XCV1000E (Shrink), and
Reliability Test HAST HASTU HTS
Lot Quantity 1 1 1
Failures 0 0 0
CPG132
Table 3-42: Test Results for Device Types XC2C256, XC2C128, XC3S50, XC3S250E, and XC3S500E
Reliability Test
Temperature cycling
55 to +125C Temperature humidity 85C, 85% RH with bias HASTU HTS
CPG196
Table 3-43: Test Results for Device Type XC6SLX16
Reliability Test
Temperature cycling
55 to +125C HASTU HTS
100
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CSG144
Table 3-44: Test Results of Device Types XC95144XL, XCR3128XL, and XCV200E
Reliability Test
Temperature cycling
CSG280
Table 3-45: Test Results of Device Types XC95288XV, XCR3512XL, and XCR3256XL
Reliability Test
Temperature cycling
55 to +125C HASTU HTS Temperature humidity 85C, 85% RH no bias
CSG324
Table 3-46: Test Results of Device Types XC6SLX16, XC6SLX45, and XC6SLX45T
Reliability Test
Temperature cycling
55 to +125C HAST HTS
CSG484
Table 3-47: Test Results of Device Type XC6SLX150T
Reliability Test
Temperature cycling
55 to +125C HAST HTS
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FGG256
Table 3-48: Test Results of Device Types XCV300E (Shrink), and XC2V500
Reliability Test
Temperature cycling
55 to +125C Temperature humidity 85C, 85% RH no bias
FGG320
Table 3-49: Test Results of Device Types XC3S1500 and XC3S1600E
Reliability Test HASTU Temperature humidity 85C, 85% RH no bias

Temperature cycling
55 to +125C HTS
FGG400
Table 3-50: Test Results of Device Type XC3S1600E
Reliability Test
Temperature cycling
FGG324, FGG456, and FGG484

Table 3-51: Test Results of Device Types XC2V250, XC2VP4, XC2S300E, XC3S1500, XC3S1600E, XC3S700AN, XC3S1400AN, XC6SLX45T, and XC6SLX150T
Reliability Test
Temperature cycling
Lot Quantity 15 1 1
Failures 0 0 0
55 to +125C Temperature humidity 85C, 85% RH no bias THB
102
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Table 3-51: Test Results of Device Types XC2V250, XC2VP4, XC2S300E, XC3S1500, XC3S1600E, XC3S700AN, XC3S1400AN, XC6SLX45T, and XC6SLX150T (Contd)
Reliability Test HAST HASTU HTS Lot Quantity 6 12 14 Failures 0 0 0 Device on Test 319 627 547 Total Device Hours/Cycles 45,240 60,192 547,657
FGG676
Table 3-52: Test Results of Device Types XCV405E, XCV800, XCV600E, XC2V3000, XC2VP20, XC2VP30, XC2VP40, XC2S600E, XC3S1500, XC3S2000, XC3S1400A, XC3S1400AN, XC3SD1800A, XC6SLX150T, and XC3SD3400A
Reliability Test
Temperature cycling
Failures 0 0 0 0 0
Device on Test 492 43 90 450 405
55 to +125C Temperature humidity 85C, 85% RH with bias HAST HASTU HTS
FGG680
Table 3-53: Test Results of Device Type XCV1000E (Shrink)
Reliability Test
Temperature cycling
FGG900
Table 3-54: Test Results of Device Type XC6SLX150T
Reliability Test
Temperature cycling
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FGG1156
Table 3-55: Test Results of Device Types XCV2000E (Shrink), XCV1600E, XC3S4000, and XC3S5000
Reliability Test
Temperature cycling
55 to +125C
FTG256
Table 3-56: Test Results for Device Types XCR3512XL, XC2C512, XC2S150E, XC3S250E, XC2S300E, XC2S400E, XC3S1000, XC3S50A, XC3S200A, XC3S400A, XCR3512XL, and XC3S200AN
Reliability Test
Temperature cycling
Lot Quantity 19 2 1 2 15 16
Device on Test 804 90 45 65 594 669
Total Device Hours/Cycles 806,250 90,000 47,745 6,240 57,024 670,080
55 to +125C Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias HAST HASTU HTS
PQG160, PQG208
Table 3-57: Test Results of Device Types XC95144, XC95216, XCS40XL, XC2S200, XC2S300E, XC3S400, and XC3S500E
Reliability Test
Temperature cycling
Failures 0 0 0 0 0
Device on Test 223 45 33 180 223
55 to +125C Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias HASTU HTS
104
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HQG240, HQG208
Table 3-58: Test Results of Device Types XCV1000E (Shrink), XC5215, XCV600, XCV600E, XC4085XLA, and XC95216
Reliability Test
Temperature cycling
Lot Quantity 1 1 1
Failures 0 0 0
PCG44, PCG84
Table 3-59: Test Results for Device Types XC9572XL, XCS05, XC18V02, and XC1702L
Reliability Test
Temperature cycling
SOG20
Table 3-60: Test Results for Device Types XC17S50A, XC17S100A, and XC18V01
Reliability Test
Temperature cycling
55 to +125C HTS
VQG44, VQG64, VQG100

Table 3-61: Test Results of Device Types XCS30XL, XC18V02, XC18V04, XC2C64A, XC2C128, XC2C256, XC9572XL, XC3S200, XC3S250E, and XC3S100E
Reliability Test
Temperature cycling
Lot Quantity 15 4 2
Failures 0 0 0
55 to +125C Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias
www.xilinx.com
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Table 3-61: Test Results of Device Types XCS30XL, XC18V02, XC18V04, XC2C64A, XC2C128, XC2C256, XC9572XL, XC3S200, XC3S250E, and XC3S100E (Contd)
Reliability Test HASTU HTS Lot Quantity 15 18 Failures 0 0 Device on Test 720 810 Total Device Hours/Cycles 60,480 768,240
VOG20, VOG48
Table 3-62: Test Results of Device Types XCF01S, XCF02S, XCF04S, XCF08P, XCF16P, and XCF32P
TQG100, TQG144
Table 3-63: Test Results of Device Types XC2S100, XC95144XL, XC95288XL, XC2C384, XC3S50A, XC3S200, XC3S400, XC3S100E, XC3S250E, XC4010XL, and XC3S50AN
Reliability Test
Temperature cycling
Failures 0 0 0 0 0
Device on Test 764 135 75 495 765
55 to +125C Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias HASTU HTS
FFG668
Table 3-64: Test Results of Device Types XC4VLX60
Reliability Test
Temperature cycling
106
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FFG484, FFG784
Table 3-65: Test Results of Device Types XC6VLX130T and XC6VLX240T
Reliability Test
Temperature cycling
55 to +125C
FFG1136, FFG1148, FFG1152

Table 3-66: Test Results of Device Types XC2V8000, XC2VP20, XC2VP50, XC4VLX60, XC4VLX100, XC4VLX160, XC4VFX60, XC4VSX95T, XC5VLX50T, and XC5VLX110T
Reliability Test
Temperature cycling
Failures 0 0 0 0
FFG1759, FFG1760
Table 3-67: Test Results of Device Types XC6VSX475T, XC6VLX760 and XC6VLX240T
Reliability Test
Temperature cycling
55 to +125C
FFG1156
Table 3-68: Test Results of Device Types XC6VLX115(1)T, XC6VLX130T, XC6VLX365T, XC6VSX475T, XC6VLX195T and XC6VLX240T
Temperature cycling
Failures 0 0 0 0
55 to +125C Temperature humidity 85C, 85% RH no bias Temperature humidity 85C, 85% RH with bias
Notes:
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107
FFG1923
Table 3-69: Test Results of Device Types XC6VHX565T, XC6VHX255T and XC6VHX380T
Lot Quantity 10 4 3 3 Failures 1(1) 0 0 0 Device on Test 192 118 74 72 Total Device Hours/Cycles 192,850 120,073 74,345 72,000
Reliability Test
Temperature cycling
55 to +125C Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias High temperature storage
Notes:
1. One unit failed at post temperature cycling stress was due to a solder particle at bump. Post bump cleaning improvement is being implemented.
FFG1513, FFG1517
Table 3-70: Test Results of Device Types XCE2VP50, XC2V6000, XC2VP50, XC2VP70, XC4VLX100, XC4VLX160, and XC4VLX200
Reliability Test
Temperature cycling
Lot Quantity 2
Failures 0
Device on Test 100
Total Device Hours/Cycles 100,000
55 to +125C
FFG1704
Table 3-71: Test Results of Device Types XC2VP70 and XC2VP100

Temperature cycling
55 to +125C
FFG324
Reliability Test
Temperature cycling
55 to +125C
108
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FFG900
Table 3-73: Test Results of Device Type XC7K325T
Reliability Test
Temperature cycling
55 to +125C Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias High temperature storage
FFG1738
Table 3-74: Test Results of Device Types XC5VLX330T
Reliability Test
Temperature cycling
55 to +125C
SFG363
Reliability Test
Temperature cycling
55 to +125C Temperature humidity 85C, 85% RH with bias Temperature humidity 85C, 85% RH no bias
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109
Board-Level Reliability Tests, SnPb Eutectic

FG676, FG680, FG900, FG1156, BF957, FF672, FF896, FF1152, FF1704, SF363, and CF1144
Table 3-76:
Package
Package Details (All Dimensions in mm)

Size I/O Pitch Ball/ Column Size 0.60 0.60 0.60 0.60 0.75 0.60 0.60 0.60 0.60 0.50 0.52 Pad Opening 0.46 0.46 0.46 0.46 0.61 0.53 0.53 0.53 0.53 0.40 0.80 Pad Type Die Size Substrate 0.56 thick, 4-layer 0.98 thick, 3-layer 0.56 thick, 4-layer 0.56 thick, 4-layer 1.152 thick, 6-layer 1.152 thick, 6-layer 1.152 thick, 6-layer 1.152 thick, 6-layer 1.152 thick, 6-layer 0.60 thick, 4-layer 1.59 thick, 10-layer
FG676 FG680 FG900 FG1156 BF957 FF672 FF896 FF1152 FF1704 SF363 CF1144
27 x 27 40 x 40 31 x 31 35 x 35 40 x 40 27 x 27 31 x 31 35 x 35 42.5 x 42.5 17 x 17 35 x 35
676 680 900 1,156 957 672 896 1,152 1,704 363 1,144
1.00 1.00 1.00 1.00 1.27 1.00 1.00 1.00 1.00 0.8 1.00
SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD SMD
17.8 x 17.8 x 0.3 20.3 x 20.3 x 0.3 17.0 x 17.0 x 0.3 23 x 21 x 0.3 22 x 20 x 0.7 12 x 10 x 0.7 10 x 10 x 0.7 22 x 20 x 0.7 26 x 22 x 0.7 10 x 10 x 0.3 22 x 20 x 0.7
Mother Board Design and Assembly Details

8-Layer, FR-4, 220 x 140 x 2.3622 mm size, HASL Finish 0.5 mm pad diameter/0.65 mm solder mask opening (NSMD Pads) Board layer structure: Signal/GND/signal/power/signal/GND/signal/power Power/GND layer has 70% metal. Internal signal layer has 40% metal. 0.1524 mm laser cut stencil, 0.50 mm aperture, alpha metals WS609 paste
Test Condition
0C 100C, 10 minutes dwells, 5 minutes ramps, 2 cycles/hour
110
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Failure Criteria
Table 3-77: Continuous scanning of daisy chain nets (every 2 minutes) OPEN: Resistance of net > threshold resistance (300) FAIL: At least 2 opens within one cycle, log 15 failures for each net
Summary of Test Results

Cycles Completed 7,027 4,000 7,027 5,000 4,145 5,840 7,027 4,158 4,150 2,370 2,288 5,000 # Tested 30 30 28 32 35 30 12 30 35 24 24 21 # Failed 30 0 28 25 35 30 10 30 35 21 24 0 First Failure (cycle) 4,686 NA 4,405 2,786 1,958 3,764 5,607 2,668 3,003 1,642 1,555 NA Characteristic Life (cycle) 6,012 NA 5,344 4,892 3,662 4,881 6,783 3,822 3,389 2,048 1,999 NA
Package FG676 FG680 FG900 FG1156 BF957 FF672 FF896 FF1152 FF1704 SF363 (Lot 1) SF363 (Lot 2) CF1144
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111
Weibull Plots
X-Ref Target - Figure 3-1
99.00
P=2 F=30 | S=0
Cumulative % Failed
50.00
10.00 5.00
1.00 1000.00
10000.00
Cycles to Failure
=11.01, =6012.65
UG116_c3_01_0528 09
Figure 3-1:
Cycles to Failure in the Second-Level Reliability Tests for FG676
99.0 P=2 F=28 | S=0
Cumulative % Failed
50.0
10.0 5.0
1.0 1000.0
10000.0
Cycles to Failure
=8.46, =5344.4
UG116_c3_02_052709
Figure 3-2:
112
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90 80 70 60 50 40
FBGA 1156 W/rr
Occurence CDF %
30 20
10 5
2 1 1000
YR2001 M11DE14 RJC 10000
Test Cycles
= 6.713 = 4,892 r2 = 0.973 n/s = 39/14
UG116_c3_03_0528 09
Figure 3-3:
99.00 90.00 BF957 W2 RRX - SRM MED F=35 / S=0
Cumulative % Failed
50.00
10.00
5.00 1.00 1000.00
10000.00
Cycles to Failure
1=7.33, 1=3662.67, =0.9589
UG116_c3_04_0528 09
Figure 3-4:
Cycles to Failure in the Second-Level Reliability Tests for BF957
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113
99.00 90.00 Data 1 W2 RRX-SRM MED F=30 / S=0
Cumulative % Failed
50.00
10.00 5.00
1.00 2000.00
9000.00
Cycles to Failure
FF672 2VP7 BLR TCA Test
UG116_c3_05_052709
Figure 3-5:
Cycles to Failure in the Second-Level Reliability Tests for FF672
99.00 90.00
P=2 F = 10 S = 2
Cumulative % Failure
50.00
10.00 5.00
1.00 1000.00
10000.00
Cycles to Failure
=14.53 = 6783.77
UG116_c3_06_0528 09
Figure 3-6:
114
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99.00 90.00 FF1152-2v6000 (TCA) F=30 / S=0
Cumulative % Failed
50.00
10.00 5.00
1.00 1000.00
10000.00
Cycles to Failure
=11.9146, = 3822/1219. p=0.9685
UG116_c3_07_052709
Figure 3-7:
99.00 90.00
LX25 SF363 (Lot #2) F=24 / S=0 LX25-SF363 (Lot #1) F=21 / S=3
Cumulative % Failed
50.00
10.00 5.00
1.00 1000.00
10000.00
Cycles to Failure
1=14.9811, 1=2048.4279, =0.9921 2=10.5433, 2=1999.5023, =0.9360
UG116_c3_0 8 _052709
Figure 3-8:
Cycles to Failure in the Second-Level Reliability Tests for SF363
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115
99.00 90.00 SRM MED W2-RRX F=35 / S=0
Cumulative failure (%)
50.00
10.00 5.00
1.00 1000.00
10000.00
Cycles to Failure
=19.1835, =3389.4518, =0.8659
UG116_c3_09_0528 09
Figure 3-9:
116
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Board-Level Reliability Tests, Pb-Free
Board-Level Reliability Tests, Pb-Free

FGG676, FFG1152
Table 3-78:
Package FGG676 FFG1704 FFG1152
Package Details (All Dimensions in mm)

Size 27 x 27 42.5 x 42.5 35 x 35 I/O 676 1,704 1,152 Pitch 1.00 1.00 1.00 Ball/Column Size 0.60 0.60 0.60 Pad Opening 0.46 0.53 0.53 Pad Type SMD SMD SMD Die Size 17.8 x 17.8 x 0.3 23 x 23 22 x 20 x 0.7 Substrate 0.56 thick, 4-layer 1.152 thick 6-layer 1.152 thick, 6-layer
Mother Board Design and Assembly Details

8-layer, FR-4, 220 x 140 x 2.3622 mm size, OSP finish 0.5 mm pad diameter/0.65 mm solder mask opening (NSMD Pads) Board layer structure: Signal/GND/signal/power/signal/GND/signal/power Power, GND layer has 70% metal. Internal signal layer has 40% metal. 0.1524 mm laser cut stencil, 0.50 mm aperture, alpha metals WS609 paste
Test Condition
FGG676: 0C 100C, 40-minute thermal cycle, 10 minutes dwells, 10C/minute ramp rate FFG1152: 0C 100C, 10 minutes dwells, 5 minutes ramps, 2 cycles/hour
Failure Criteria
Table 3-79: Continuous scanning of daisy chain nets (every 2 minutes) OPEN: resistance of net > threshold resistance (300) FAIL: At least 2 opens within one cycle, log 15 failures for each net
Summary of Test Results

Cycles Completed 7,027 5,000 4,640 # Tested 35 32 28 # Failed 27 0 26 First Failure (cycle) 4,390 NA 3,186 Characteristic Life (cycle) 5,974 NA 4,121
Package FGG676 FFG1704 FFG1152
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117
Weibull Plots
99.00 90.00
SnAgCu Sphere [SnPb Paste] [215C Peak] SnAgCu Sphere [SnPb Paste] [205C Peak] SnAgCu Sphere [SnAgCu Paste] [235C Peak] Eta Beta 9.3090 12.0093 r^2
50.00
Figure 3-10:
Cumulative % Failed
Figure 3-11:
)%( eruliaf evitalumuC
10.00 5.00
4.639 5.797
W2P/RRX
1.00 1000.00
10000.00
Cycles to Failure
UG116_c3_10_102908
Cycles to Failure in the Second-Level Reliability Tests for FGG676
99.0 90.0 Pb -Free
50.0
10.0 5.0
1.0 1000.00
Cycles to Failure
10000.00
UG116_c3_11_052709
Cycles to Failure in the Second-Level Reliability Tests for FFG1152
118
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Xilinx Spartan3 Device Reliability

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Device Reliability Report

First Quarter 2012

UG116 (v9.0) May 8, 2012

UG116 (v9.0) May 8, 2012

UG116 (v9.0) May 8, 2012

UG116 (v9.0) May 8, 2012

UG116 (v9.0) May 8, 2012

UG116 (v9.0) May 8, 2012

Chapter 1: The Reliability Program

Non-Hermetic and Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reliability Monitor Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 2: Results by Product Family

Reliability Report UG116 (v9.0) May 8, 2012

Flash PROM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Reliability Report UG116 (v9.0) May 8, 2012

Chapter 3: Results by Package Type

Reliability Data for Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Reliability Data for Pb-Free Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Reliability Report UG116 (v9.0) May 8, 2012

Board-Level Reliability Tests, SnPb Eutectic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Board-Level Reliability Tests, Pb-Free . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Reliability Report UG116 (v9.0) May 8, 2012

The Reliability Program

The Reliability Program

High-temperature operating life (HTOL) THB(3) or High-accelerated stress test (HAST)(3)

1,000 hours 1,000 hours 96 hours

200 FIT(1) 50 FIT(2)

Reliability Report UG116 (v9.0) May 8, 2012

Chapter 1: The Reliability Program

Wafer Process Qualification Tests (Contd)

Temperature humidity (TH)(3) or Unbiased high accelerated stress test (HASTU)(3)

85C, 85% RH 130C, 85% RH 110C, 85% RH 65C to +150C

Temperature cycling (TC)(3,4,5,6)

55C to+125C 40C to +125C

Data Retention Bake(7) or High Temperature Storage (HTS) Program Erase(8)

Non-Hermetic and Hermetic Packages

Reliability Report UG116 (v9.0) May 8, 2012

Reliability Monitor Program

Non-Hermetic Package/Assembly Qualification (Contd)

55C to +125C 40C to +125C

Autoclave(1) or Temperature humidity unbiased(1) or HASTU(1) High-Temperature Storage (HTS)

Reliability Monitor Program

Reliability Report UG116 (v9.0) May 8, 2012

Chapter 1: The Reliability Program

Condition Tj > 125C, VDD Max TA = 150C

Duration 1,000 hours 1,000 hours

Sample Size per Process per Family per Quarter 45 45

Reliability Report UG116 (v9.0) May 8, 2012

Process Technology Family

Tests Used by the Reliability Package Monitor Program (Contd)

Temperature humidity unbiased(1, 6) or HASTU(1, 6) HTS(7)

Process Technology Family

7 series FPGAs XC6VxXxxx, XCE6VxXxxx XC6Sxxx

Reliability Report UG116 (v9.0) May 8, 2012

Chapter 1: The Reliability Program

Wafer Process Technology Family (Contd)

ESD and Latch-up Summary

Product ESD and Latch-up Data

Reliability Report UG116 (v9.0) May 8, 2012

ESD and Latch-up Summary

Product ESD and Latch-up Data (Contd)

Reliability Report UG116 (v9.0) May 8, 2012

Chapter 1: The Reliability Program

ESD and Latch-up Data for XC4VFXxxx