DC DC Cv : hysteretic current mode control

DC-DC Converter with Fast Transient ResponseLoads and High E ciency for Low-Voltage Microprocessor
Power Electronics Group Department of Electrical and Computer Engineering University of Colorado, Boulder, CO 80309-0425 Phone: 303492-4863, Fax: 303492-2758, arbetteb@rtt.colorado.edu, maksimov@colorado.edu

Barry Arbetter and Dragan Maksimovi c

95 Abstract The paper describes a DC-DC converter 94 for use with low voltage microprocessor loads. The 93 control method is a hysteretic current-mode control with current estimator in the continuous conduction mode which has fast 92 transient response. At light loads, the converter op91 with sense resistor erates in the discontinuous conduction mode using a 90 peak current control method which causes the switch89 ing frequency to be proportional to load current, thus 88 maintaining high e ciency in a very wide range of loads. The control method implementation, transient 87 response and output inductor design equations, and 86 equations for designing an input lter to reduce input 85 current di dt are provided. An inductor current esti84 mator which provides higher e ciency, good transient 0.1 1 10 100 response, and current limiting, is presented. ExperLoad current I [A] imental results for a 5.0V input, 3.1V output, 13A 1: E ciency vs load current in the experimental 3 1V, DC-DC converter are included to verify the theoreti- Figure 45W converter with the current sense resistor and with the current cal information. estimator circuit. Efficiency [%]
LOAD

1 Introduction
Microprocessors, such as the Intel Pentium Pro, require low voltage and high current operation. They also have special requirements regarding DC voltage regulation, output voltage ripple, load current slew rate, maximum input current di dt, and e ciency. In the Pentium Pro example 1 , output voltages from 2.4 to 3.5Vdc with DC load currents up to 13A are required. The input voltages available for the converter are 12Vdc and 5Vdc. The power supply must maintain the regulated output under load current slew rate requirements of 30A s, while the input current di dt must be less than 0.1A s. The output must be current limited and operate in constant current mode for a shorted output. The e ciency must be greater than 80 at high current load and greater than 40 at low current load. Higher e ciency in a wide range of loads is particularly bene cial in battery-powered systems with power management.
This work was supported in part by the University of Colorado Center for Advanced Manufacturing and Packaging of Microwave, Optical and Digital Electronics CAMPmode.

Because of the high load current slew rate requirements, a large bulk capacitor with low equivalent series resistance is required at the output. This means that a low switching frequency can be used to get higher e ciency, since the large capacitor can support large output inductor ripple current without excessive power loss or output voltage ripple. Therefore a lower switching frequency can be used to optimize e ciency as long as the response of the converter to load transients is fast. This paper discusses design of a DC DC converter that can meet the requirements of low-voltage microprocessor loads. The converter uses a standard buck topology with a synchronous switch 3 , and the control method described in 2 . Selection of input and output lter components to meet the input current di=dt and transient response requirements are described. Also discussed is a circuit for estimating the current in the output lter inductor which results in higher e ciency and good transient response compared with a conventional resistor current sense approach. The theoretical information is veri ed on an experimental circuit constructed to meet the Pentium Pro example speci cations and with measured e -

ciency results shown in Fig. 1. The power stage used in experimental veri cation is described in Section 2. Section 3 describes the control method and its implementation. Section 4 discusses output transient response to a full load change. Section 5 discusses the input lter used to reduce input current di dt. Section 6 describes an inductor current estimator used to reduce power loss and still provide a current limit function, as required in 1 . Results of experimental veri cation are given in Section 7 of the paper, and conclusions are in Section 8.

iL

DCM

iL Ip

CCM

Ip Iv

Figure 3: Inductor current waveform in the discontinuous-

tp

tz

tp

2 Power Stage

conduction mode left and the continuous-conduction mode right.

Fig. 2 shows a schematic of the experimental 45W buck converter with synchronous recti er. The power stage converts an input voltage, VIN, to the desired regulated output voltage, vOUT . VIN is 5 Vdc, while vOUT is regulated at 3.1Vdc. The DC load current is in the range 0:1 ILOAD 13A. The high side switch, QH, is controlled by control signal cH . The low side switch, QL , which is the synchronous recti er, is controlled by control signal cL . The inductor current, iL , is sensed by resistor Rs and a di erential ampli er to produce control signal vi proportional to the inductor current. The desired output voltage is set by VREF . Inductor L is made by winding 4 turns of 18AWG wire on a PQ20 16 core, with gap spacing 0.250 mm between the core halves. Inductor Lin is made by winding 2 turns of 18AWG wire an a PQ20 16 core, with gap spacing 0.050 mm between the core halves. Capacitor C consists of two 10uF multilayer surface-mount ceramic capacitors near L, and two 10uF multilayer surface-mount ceramic capacitors near R, with six 220uF surface-mount tantalum capacitors and ten 150uF surfacemount tantalum capacitors in between, all in parallel. Capacitor Cin consists of two 10uF multilayer surface-mount ceramic capacitors near QH and twenty 330uF surface-mount tantalum capacitors between these and Lin , all in parallel. The ceramic capacitors are made by AVX-Kyocera, and the tantalum capacitors are Sprague Type 595D. The transistors are in TO-220 packages and the Schottky diode is in a surface mount package, all are made by International Recti er. Resistor Rs is four surface-mount, 1 watt, 25m resistors in parallel. Resistors RQH and RQL each consist of two surfacemount, 0:5W, 10 resistors made by IRC in parallel.

then QH is turned o . While iL ramps down to zero, QL is turned on. Switch QL provides the synchronous recti cation and is turned o when iL reaches zero amps. The current in the inductor causes a pulse of charge which increases vOUT by charging C. Capacitor C is discharged by the load, thus repeating the process. The converter operates in the DCM if ILOAD  1=2Ip . In the CCM, the output voltage can no longer be regulated based on the output voltage ripple only. The sensed inductor current is used to accomplish a hysteretic current-mode control: QH is turned on when the inductor current reaches a minimum, called the valley inductor current, Iv , and o when the maximum inductor current, called the peak inductor current, Ip , is reached. The values of Iv and Ip are determined by the control circuit, as discussed in the following section on implementation.

3.1 Controller Implementation

Fig. 4 shows a block diagram of the control circuit. The output voltage vOUT is followed by an optional switching noise lter and then goes to an ampli er. The di erence between the desired output voltage VREF and the actual output voltage is multiplied by the voltage-loop error ampli er with gain Av . The result passes through a limiter, LIMv , and the resulting signal is control signal vv . A constant value VRipple , is added to vv . The result passes through a limiter, LIMp , and the resulting signal is control signal vp . The vp signal cannot go below VpDCM, thus providing a minimum peak current in the DCM. The vv signal cannot go above Vvmax, therefore the vp signal cannot go above Vvmax +VRipple , thus providing a current limit protection. The iL signal develops a voltage across resistor Rs and this is ampli ed by Ai to get the vi signal. The comparator comp1 output is high when vi vv , and will set the latch LH and reset the latch LL . The cL signal will go low in the CCM or stay low in the DCM, causing the low side switch to go low or stay low. The cH signal will go high after a delay tdH, causing the high side switch to turn on and the inductor current iL to ramp up. This can occur in both the CCM and the DCM. In the DCM the signal vi will be zero, ideally, when the comp1 output goes high. Note that when vv = 0, vOUT = VREF . The comparator comp2 output is high when vi vp , and will set LL and reset LH . The cH signal will go low, causing the high side switch to turn o and iL to ramp down. The cL signal will go high after a delay tdL , providing synchronous

3 Control Method

The converter operates in the discontinuous conduction mode DCM at light loads and in the continuous conduction mode CCM at higher loads. Typical inductor current waveforms in the two modes are shown in Fig. 3. In the DCM, the output voltage regulation is based on sensing the output voltage ripple on vOUT , so that the ripple stays approximately the same, and the transient response has no overshoots or undershoots. The peak inductor current Ip is preset at a constant value so that the e ciency in DCM is at maximum, as described in 4 . The controller operates as follows: initially both switches are o . When capacitor C is discharged by the load to the DC reference voltage VREF , QH is turned on. The inductor current iL ramps up to Ip and

Lin + V IN 2.7uH Cin 6620uF IRL2203N R QH 5ohm c H

i H v SW

L 3.1uH

LOAD +

6.25mOhm v

5.0V V GATE

R QL 5ohm c Q L IRL2203N L D 10BQ015

C 2860uF -

DRIVERS AND CONTROL CIRCUIT V

REF v

A R i i = i s L

A = 55 i +
-

OUT
:

Figure 2: Schematic of the 3 1V, 45W power stage.

LIMv v OUT Switching noise filter (if needed) V REF Av + ve V vmin vv 0 0 V vmax + + V Ripple + V pDCM vp LIMp

+ v i = A i Rs i L + -

comp1

vi < v

SetH

cH

LH comp2 vi > v
p R Q

Delay t dL

Voffset

+ -

comp3 v i < Voffset

LL
R Q

cL Delay t dH Shoot-through protection

Figure 4: Block diagram of the control circuit.

recti cation. This can occur in both the CCM and the DCM. The comparator comp3 output is high when vi Voffset and will reset LL . The signal cL will go low and the low side switch will turn o . This occurs in the DCM and is necessary to prevent iL from changing direction after it ramps down to zero amps. The DC signal Voffset is used to ensure that the synchronous recti er is turned o before iL changes polarity through the synchronous recti er QL . Delays tdH and tdL are used to prevent both the high and low switches from being on at the same time, a condition known as shoot-through. Because there is some parasitic capacitance at the switching node, the inductor will exchange current with the parasitic capacitance, and the inductor current will have a small oscillation around zero amps for some time after the inductor current crosses zero. The control circuit may be modi ed to take this into account. The modi cation replaces the comp1 output which produces the signal SetH with the circuit shown in Fig. 5. The peak amplitude of the vi signal due to the oscillation occurring after the inductor current crosses zero is called VpOSC . The comparator comp5 is implemented with hysteresis voltages VL and VH where VL = 0 and VpOSC VH VpDCM . The comp5 output goes low when vi VL and goes high when vi VH . If the comp5 comparator output is high it indicates the CCM and if the output is low it indicates the DCM. The CCM signal is used to gate the comp1 output so that vi vv sets the high switch, as before. The DCM signal is used to gate the comp4 output which goes high if 0 vv , and then
vi V pDCM

V L =0 vi
+ -

VH comp5 CCM DCM

VH V pOSC 0

t vv vi vv 0
+ -

comp1 v v i< v Set H comp4 0<vv

+ -

Figure 5: Modi cation of the controller circuit because of DCM

ringing due to parasitics.

this signal sets the high switch. Thus vv is compared to 0 in the DCM.

4 Analysis of Transient Response to Full Load Current Changes

Fig. 6 shows the inductor current transient waveforms where the load current goes from 0 to ILOAD MAX and back to 0. When a load transient occurs, the initial voltage change is due to the voltage drops across the output capacitor equivalent series resistance and equivalent series inductance. The capacitor, actually many capacitors in parallel, should consist of some capacitors which provide bulk energy storage and some

LOAD

OUT

i IN

L IN R LIN R CIN C IN I TRAN L IN C IN Zs

iL I p MAX I LOAD MAX I v MAX

V IN
+ -

Figure 7: Left Circuit model for calculating maximum input

current di dt and Right Circuit model for calculating the input lter output impedance s .
Z

Figure 6: Inductor current waveform in the zero-load-to-full-load

transient.

tr

tf

which provide high frequency decoupling. The bulk energy storage capacitors should be chosen to provide the required equivalent series resistance and the high frequency decoupling capacitors should be chosen to provide the required equivalent series inductance, as discussed in 1 . As time progresses, the capacitor provides or accepts current until the controller can change the output inductor current to be compatible with the load current. If the load current increases, the capacitor discharges until the average inductor current increases to be equal to the load current. If the load current decreases, the capacitor charges until the average inductor current decreases to be equal to the load current. For fast transient response, the inductor must have a low enough inductance to allow the inductor current to slew fast enough to prevent excessive voltage changes on the capacitor. Ideally the inductor current will be compatible with the load before the voltage on the capacitor reaches the steady state value determined by the controller for the load current under steady state conditions. This will prevent overshoot or undershoot of the output voltage and provide a damped response to load transients. The inductance of the output inductor is determined by calculating the change in voltage on the output capacitor under worst case transient conditions. To simplify the calculations, the capacitor equivalent series resistance is neglected and it is assumed that the output voltage does not change signi cantly during the transient so that the nominal DC value VOUT can be used in the calculations. The inductor current rise and fall times are: LIpMAX LOAD MAX 1 tr = LI VIN , VOUT ; tf = VOUT : The inductor current waveform can be used to nd the change in the output voltage: LOAD MAX ILOAD MAX
vOUT = , LI 2 VIN , VOUT 2C for the zero-to-full-load transient, and pMAX IpMAX
vOUT = LI 3 VOUT 2C for the full-to-zero-load transient. Equations 2 and 3 can be used to solve for L with worst case values for VIN and VOUT and with
vOUT =the

di erence between the minimum and maximum load DC values as determined by the controller voltage error ampli er gain Av and the control waveforms as discussed in 2 . With C = 2860F,
vOUTleq0:1V, VIN = 5V, VOUT = 3:1V, and ILOAD MAX = 16:5A maximum load current plus ripple current, from 2 we have that the output lter inductance should satisfy L  4:1H. The inductance used in the experimental power stage is L = 3:1H.

5 Input Filter

An input lter is needed to keep the maximum input current diIN =dt below a certain value. The left portion of Fig. 7 shows the circuit model used in 3 to calculate the maximum diIN =dt given a maximum load transient ITRAN caused by the output inductor current slewing. To simplify the calculation, it is assumed that the inductor current changes instantaneously from 0 to ITRAN . The resulting equation for iIN is  4 iIN = ITRAN 1 , cos p t LIN CIN and the maximum input current diIN =dt is diIN MAX = pITRAN 5 dt LIN CIN The addition of an input lter can cause the converter to become unstable and or a ect its performance. As discussed in 5 , there are two practical design criteria to ensure system stability and maintain the performance of the converter: the input lter cuto frequency should be lower than the averaging lter cuto frequency; the input lter output impedance, Zs , should be made much smaller than the regulator open-loop input impedance. The averaging lter for a buck converter is the output lter. The second criterion requires knowledge of the output impedance of the input lter at resonance, since that will give its maximum impedance. This lter relies on parasitic resistances to provide the damping necessary to achieve a sufciently low output impedance at resonance. The right portion of Fig. 7 shows the parasitic inductor resistance, RLIN , and parasitic capacitor resistance, RCIN . By solving for the Zs and setting the imaginary part to zero to determine the resonance frequency !RES , it is found that if 1 LIN CIN RLIN RLIN + RCIN  then !RES  pLIN CIN . Under this condition, the impedance at resonance, ZRES , is =CIN ZRES = R LIN+ 6 LIN RCIN

By making the ratio LIN =CIN small enough, the component parasitic series resistances RLIN , RCIN can provide sufcient damping of the input lter. The values used in the power stage of Fig. 2 are LIN = 2:7H and CIN = 6620F. Transient response measurements can be used to con rm stability of the converter with the input lter.

L v SW R L+ 100 L ideal RL v OUT R L100 R DIF3 4.7k

+ -

iL

R DIF1 4.7k BUF L4.7k R DIF2

+

BUF L+ V null

v DIF DIF Q DCM ZVN3310A R gain 10k v ie R DC C slope 1M

6 Output Inductor Current Estimator Circuit

+15V R null 10k -15V

R DIF4 4.7k

The current sense circuit described in Section 3 requires a high gain and bandwidth ampli er that is subject to noise. Also, the current sense resistors dissipate power. Power loss in the current sense resistors is given by PRsDCM = 2 7 3 ILOADIp Rs in the DCM and 2 R 8 PRsCCM = ILOAD2 + Iripple s 12 Iripple = Ip , Iv 9 in the CCM. Observer-based techniques for estimating inductor current for sensorless current mode control are discussed in 6 . The idea is to reconstruct a signal proportional to the inductor current by sensing the voltage across the inductor rather than sensing the inductor current itself. The inductor current estimator circuit we implemented and tested is shown Fig. 8. The circuit works by measuring the voltage across the output inductor L, and converting this voltage into a current source. The current source is applied to a resistor, RDC , and capacitor, Cslope , which are in parallel, and the voltage across these is the estimated current signal vie , which is then used to replace the measured current signal vi described in Section 3. The capacitor provides the sloping waveform to simulate the inductor current. Because the inductor has some parasitic resistance RL , there will be an average DC voltage across the inductor corresponding to ILOADRL . This average voltage is converted to an average current in the current source and then to an average voltage by the RDC , providing a means of measuring the output inductor DC current. NMOS FET, QDCM , ensures the vie voltage is zero when the inductor current is zero in DCM. Details of the circuit operation are as follows: resistors RL+ and RL, isolate the vSW and vOUT waveforms, which are then bu ered to provide low output impedance and become the inputs to a di erential ampli er DIF. An o set vADD is added to these and the result is vDIF = vSW , vOUT + vADD . The voltage vADD = vieB +0:1Vnull , where vieB is a bu ered version of vie and Vnull is an o set adjustment to null out any DC o sets in the ampli ers. Thus vDIF = vSW , vOUT + vieB + 0:1Vnull . For simplicity, assume that vieB = vie and that Vnull = 0. Then the voltage across Rgain is vSW , vOUT . The current charging Cslope and RDC is vSW , vOUT =Rgain . The dynamic equations describing the inductor current iL and the estimated inductor current vie are: L vSW , vOUT = Lideal di 10 dt + iL RL

R ADD1 47k
+

R ADD3 4.7k

ADD R ADD4 4.7k

v ADD
AND3

cH DCM cL

47k R ADD2

v ieB To Control Circuit

BUF ie

Figure 8: Inductor current estimator circuit.

and

vSW , vOUT = C dvie + vie 11 slope dt Rgain RDC respectively. Eq. 11 shows that by making Cslope Rgain proportional to L and Rgain =RDC proportional to RL , vie will estimate iL . In DCM, vie should be zero when iL is zero. To ensure this occurs, the control signals cH and cL shown in Fig. 4 and the DCM signal from Fig. 5 are used to turn on MOSFET QDCM and keep vie at zero volts when iL = 0. Thus when both switches are o and the inductor current has crossed zero amps both switches are also o when the current is at its peak in order to prevent shoot-through, the vie signal is shorted to ground through the MOSFET.

7 Experimental Results

For the following results, VIN = 5V, VGATE = 12V, and the nominal output voltage is 3:1V. Current Estimator: Steady state waveforms comparing the estimated current signal vieB with the current sense signal vi when the inductor is in DCM are shown in Fig. 9. The estimator circuit has been tuned to match the vieB signal to the vi signal as closely as possible, with Cslope = 1nF. The same waveforms are shown in CCM in Fig. 10. In both cases the controller is using the vi signal for control, and one can observe that the estimated and the sensed current signals are nearly indistinguishable. Fig. 11 shows the vp vieB and vv waveforms in steady state with the load current at 8A and the estimator circuit used in the controller. The controller operates as a hysteretic current-mode controller, but without sensing the inductor current. E ciency: The e ciency was found by measuring the DC currents and voltages at VIN, VGATE , and VOUT, and using: IOUT   = V I VOUT 100  12 IN IN + VGATE IGATE The current waveforms were veri ed to have very small ripple compared to their DC components. The gate voltage was ltered with an RC lowpass lter before the measurement point to lter out the gate current ripple. The output inductor peak current in DCM, and the output inductor current ripple in

iL [5A/div]

vp vieB vv

vi , vieB

Figure 9: Current estimator operation in the DCM: sensed current

v

i , estimated

current

ieB , and iL

waveforms.

Figure 11: Controller operation in the CCM using the estimated

current signal
v

ieB , with

control signals

and p .
v

iL [5A/div]

vi , vieB

Figure 10: Current estimator operation in the CCM: sensed current i , estimated current
v v

ieB , and iL

waveforms.

CCM are adjusted to maximize e ciency at light and heavy loads, respectively, as described in 2 . Fig. 1 shows the resulting e ciency plotted versus the load current for the current sense and the current estimator cases. It can be seen that the estimator circuit provides higher e ciency, especially at the higher load currents. For the case where the current sense circuit is used in the controller, the DCM peak current is 6A and the CCM ripple current is 6A. The switching frequency in the CCM at 5A load is 60kHz. For the case where the estimator circuit is used in the controller, the DCM peak current is 6A and the CCM ripple current is 7A. The switching frequancy in the CCM at 5A load is 52kHz. Output voltage ripple For DCM, the output voltage ripple is 40mVp-p. For CCM, 6A ripple current corresponds to 25mVp-p of output voltage ripple and 7A ripple current corresponds to 28mVp-p of output voltage ripple. All are within the 1 speci cation in 1 .

Output transient response: To do the transient response measurement, the load consists of a resistor of approximately 15:5 in parallel with an IRF520 NMOS FET, which has a speci ed on resistance of 0:27 . The MOSFET gate rise and fall times were approximately 30ns, but there was about 100ns of ringing on the gate signal after the fall time. Fig. 12 shows the output inductor current at 5A div, the AC coupled output voltage and the reference square wave signal VSQ used to turn the load MOSFET on and o the load MOSFET is on when VSQ is high. These waveforms are taken with the current sense resistor circuit used in the control circuitry. Fig. 13 shows the same waveforms with the current estimator circuit. The transient response in both cases is overdamped, as the output voltage does not have any overshoots or undershoots. We have also tested the case when the current-estimator circuit was de-tuned by changing the capacitor Cslope 1nF to 820pF so that the estimated current does not match the sensed current. Again no signi cant di erence in the transient response was observed. Input current transient response: The input current transient response to a full load change is shown in Fig. 14 along with the AC coupled output voltage and VSQ . The input current waveform and output inductor current waveform in DCM with Ip = 6A are shown in Fig. 15. The maximum input current di dt is under 0.02A s, which meets the speci cation in 1 . DC output voltage regulation: The DC output voltage ranges from 3.18V at 100mA load to 3.05V at 13A load, a 2 change. The output voltage transient response waveforms show that the change in voltage stays well within 5 of the DC output voltage, which meets the speci cation in 1 . The speci cation would be met even if the nominal DC output voltage were 2.4V. Output Current Limit: A wire was connected across the output. The output voltage measured 0.439V and the output current was measured to be 16A by sensing the output inductor current with a current probe and taking the average value.

iL [5A/div] iIN [2A/div]

vout vout vSQ

vSQ

Figure 12: Full-load transient response with the current sense

resistor.

Figure 14: Input current transient response to full load change.

iL [5A/div] iIN [50mA/div]

iL [2A/div] vout

vSQ

Figure 13: Full-load transient response with the current estimator.

Figure 15: Input current for DCM operation.

8 Conclusions
A DC-DC converter meeting the speci cations for the Intel Pentium Pro was presented. The control method for this converter allows for relatively low switching frequency for high e ciency yet the converter has fast transient response. Equations were presented for selecting the inductance value of the output inductor so that the output voltage response to full load output current transients is overdamped. Equations were presented for designing the input lter to meet maximum input current di dt speci cations. An inductor current estimator circuit which replaces a current-sense resistor and can also be used for current limiting was described. Experimental results validating the performance of the converter and the current estimator circuit were presented to show that the converter has high e ciency and can meet the speci cations for the Intel Pentium Pro microprocessor.

References

1 Pentium Pro Power Processor Power Distribution Guidelines, Intel Application Note AP-523. 2 B. Arbetter, D. Maksimovi c, Control Method for Low-Voltage DC Power Supply in Battery-Powered Systems with Power Management," Proc. IEEE PESC 1997, pp. 1198-1204. 3 S. Brown, Microprocessor controls its dedicated voltage regulator module," PCIM, April 1997, pp. 66-76. 4 B. Arbetter, R. Erickson, and D. Maksimovi c, DC-DC Converter Design for Battery-Operated Systems," Proc. IEEE PESC 1995, pp. 103-109. uk, Advances in Switched-Mode 5 R.D. Middlebrook, Slobodan C Power Conversion, Volumes I & II , TESLAco, 1983, Input Filter Considerations in Design and Application of Switching Regulators . 6 Pallub Midya, Matthew Greuel, Phillip T. Krein, Sensorless Current Mode Control - An Observer-Based Technique for DcDc Converters, Proc. IEEE PESC 1997, pp. 197-202.