IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO.

3, MARCH 2013

475

Computing Two-Pattern Test Cubes for Transition Path Delay Faults

Irith Pomeranz, Fellow, IEEE
AbstractConsidering full-scan circuits, incompletely-specied tests, or test cubes, are used for test data compression. When considering path delay faults, certain specied input values in a test cube are needed only for determining the lengths of the paths associated with detected faults. Path delay faults, and therefore, small delay defects, would still be detected if such values are unspecied. The goal of this paper is to explore the possibility of increasing the number of unspecied input values in a test set for path delay faults by unspecifying such values in order to make the test set more amenable to test data compression. Experimental results indicate that signicant numbers of such values exist. The proposed procedure unspecies them gradually to obtain a series of test sets with increasing numbers of unspecied values and decreasing path lengths. Experimental results also indicate that lling the unspecied values randomly (as with some test data compression methods) recovers some or all of the path lengths associated with detected path delay faults. The procedure uses a matching of the sets of detected faults for the comparison of path lengths. Index TermsFull-scan circuits, path delay faults, test cubes, transition faults, two-pattern tests.

I. INTRODUCTION EST DATA compression methods for full-scan circuits use incompletely-specied tests, or test cubes, to accommodate the constraints of test data decompression logic on the tests applicable to the circuit [1][4]. An incompletely-specied test is obtained if test generation for a target fault stops as soon as the fault is detected. However, even in this case, due to the order by which inputs are considered during test generation, a test may contain specied values that are not necessary for the detection of the fault. Due to this possibility, dynamic test compaction procedures include processes that increase the numbers of unspecied values in a test without losing the detection of target faults [5], [6]. Dynamic test compaction procedures use the unspecied values for detecting additional faults by the same test. However, the specication of additional values can be done under the constraints of a test data compression method. The procedures described in [7] and [8] start from a completelyspecied test set and unspecify as many input values as possible without reducing the number of detected target faults. The unspecied values can then be used for test data compression. In the procedures described in [5][8], the decision to unspecify an input value in a test is made based on its effect on
Manuscript received July 19, 2011; revised December 14, 2011; accepted February 16, 2012. Date of publication March 22, 2012; date of current version February 20, 2013. The author is with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: pomeranz@ecn.purdue. edu). Digital Object Identier 10.1109/TVLSI.2012.2188727

the fault coverage. If the fault coverage is reduced, the input retains its specied value. Otherwise, it is unspecied. This approach, where unspecifying input values is guided by the fault coverage, is applicable to any fault model (stuck-at faults are considered in [5][8]). When considering path delay faults for the detection of small delay defects, in addition to the fault coverage, another parameter of a test set is related to the lengths of the paths associated with detected path delay faults. In this case, certain specied input values may be needed only for determining the lengths of the paths associated with detected faults. If such input values are unspecied, one or more path delay faults would still be detected for every originally detected fault. Therefore, small delay defects would continue to be detected. However, the detected faults would be associated with shorter paths. The goal of this paper is to explore the possibility of unspecifying input values that affect the lengths of the paths associated with detected path delay faults, thus making a test set for path delay faults more amenable to test data compression. The terminology used in this paper with respect to path delay faults is the following. A small delay defect has an extra delay that is smaller than the clock period. Path delay faults model the case where the accumulation of small delay defects along a path causes the delay of the path to exceed the clock period. A full path starts from an input and ends at an output of the combinational logic of the circuit. A subpath starts from an internal line or an input, and ends at an internal line or an output. A path can be a full path or a subpath. The importance of subpaths to the discussion of path delay faults results from the fact that the percentage of detectable path delay faults can be low [9][13]. To allow small delay defects to be detected even when path delay faults are not detected, path delay faults that are associated with full paths as well as path delay faults that are associated with subpaths are considered in [14][16]. To dene the conditions under which a path delay fault associated with a subpath is considered to be detected, the transition path delay fault model is used in [16]. A test for a transition path delay fault requires the detection of a transition fault on every line along the path associated with the fault. Tests for transition path delay faults are a special type of strong non-robust tests for path delay faults. A strong non-robust test sensitizes the path by assigning non-controlling values to off-path inputs during the or second pattern of the test. In addition the test creates a a transition on every line of the path corresponding to the transition at the source of the path. To detect a transition path delay fault the test is also required to detect each corresponding transition fault along the path. This paper considers transition path delay faults associated with full paths and subpaths when determining values that can

1063-8210/$31.00 2012 IEEE

476

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

be unspecied under a two-pattern (broadside) test set for a full-scan circuit. The ability to dene the detection conditions of a transition path delay fault based on a set of transition faults that need to be detected facilitates the proposed procedure. Starting from a completely-specied test set, denoted by , the procedure focuses on scan-in values that can be unspecied. The procedure consists of two parts, as follows. The rst procedure described in this paper ensures that the transition path delay faults that are detected by will continue to be detected after scan-in values are unspecied under . Let denote the set of transition path delay faults detected by . This procedure does not allow the detection of any fault from to be lost when is unspecied. This is similar to requiring that the fault coverage of with respect to transition path delay faults would not decrease. It provides a baseline where as many values as possible are unspecied without reducing the fault coverage. This baseline represents the case where the test generation procedure produces incompletely-specied tests to detect a set of target path delay faults. The main contribution of this paper is in allowing additional values to be unspecied in case the test set cannot be compressed by a selected test data compression method, as discussed next. To allow additional scan-in values in to be unspecied, the second procedure described in this paper allows the lengths of the paths associated with the transition path delay faults in to be reduced as is unspecied. For a fault that is associated with a path of length , it is possible to consider subpaths of lengths . The proposed procedure allows path lengths to be reduced to one. It thus allows the detection of a transition path delay fault to be replaced by the detection of each transition fault included in individually. By unspecifying scan-in values gradually, the procedure ensures that the path lengths in are reduced gradually. Test data decompression logic applies completely-specied tests, where the unspecied values of a test cube may be lled randomly or based on other, specied values. Randomly lling the unspecied values of a test set produced by the proposed procedure imitates this. Due to variations in path lengths associated with detected path delay faults that occur when unspecied values are lled randomly, the paper denes a matching between the transition path delay faults detected by the completely-specied test set to which the proposed procedure is applied, and the test sets produced by the proposed procedure. The matching provides a more accurate assessment of the effects of unspecied values, and of randomly lling these values, on the path lengths associated with detected faults. Experimental results indicate that randomly lling the unspecied values of a test set obtained by the proposed procedure increases the path lengths associated with detected faults. For the rst few test sets in the series produced by the proposed procedure from a test set , the path lengths are equal or close to those of . The discussion in this paper is independent of any particular test data compression method, and targets only the number of unspecied values in the test set. Additional unspecied values are assumed to improve the ability to compress a test set. It is also possible to use the constraints of a particular test data

compression method for guiding the proposed procedure to unspecify certain input values. This paper is organized as follows. Section II describes the background necessary for the proposed procedure. Section III describes the rst procedure that unspecies a test set without affecting the set of detected transition path delay faults. Section IV describes the second procedure that unspecies a test set while allowing detected transition path delay faults to be associated with shorter paths. Section V gives a more formal description of the proposed procedure. Section VI discusses the random lling of incompletely-specied test sets, and the matching between sets of detected faults for the purpose of evaluating the effects on path lengths associated with detected faults. Section VII presents experimental results. II. PRELIMINARIES This section describes the background needed for describing the proposed procedure. A. Tests A two-pattern test for a full-scan circuit has the form , where is the rst pattern and is the second pattern of the test. For and 2, is the present-state of the circuit during pattern , and is the primary input vector applied during pattern . The state is scanned in at the beginning of a test. In a broadside test, and are applied in two consecutive functional clock cycles after is scanned in. Consequently, is the next-state for and . The test sets considered in this paper are broadside test sets that were generated by the test generation procedure described in [17]. The procedure targets path delay faults that are associated with the longest paths, and produces strong non-robust tests. The procedure described in this paper unspecies only scan-in values, which are values included in . Let the number of state variables be . For a state , the value of state variable is denoted by , where . If needed, the primary input values can be unspecied by the same procedure used for unspecifying the scan-in values. If primary input vectors are held constant to accommodate tester constraints, the proposed procedure will not modify them. B. Transition Path Delay Faults Path delay faults model small delay defects whose accumulation along a path cause the path to fail. The transition path delay fault model was dened in order to capture the situation where the accumulation of small extra delays is sufcient for causing faulty behavior after a transition is propagated through a subpath. As a result, the model captures both small and large delay defects. This is accomplished as follows. Similar to a path delay fault, a transition path delay fault is associated with a path and a transition on its rst line. When the transition is propagated along the path, it denes corresponding transitions for all the lines of the path. Based on these transitions it is possible to dene transition faults along the path. A

POMERANZ: COMPUTING TWO-PATTERN TEST CUBES FOR TRANSITION PATH DELAY FAULTS

477

transition path delay fault is detected when all the single transition faults along the path are detected by the same test. For the discussion in this paper, a transition path delay fault is denoted by , where are the transition faults that need to be detected in order to detect . The relationship between the faults is the following. Let be the transition fault on line . Then forms a path. In addition, if the number of inverters between and is even, and if the number of inverters between and is odd. If is associated with a full path, a test for is a strong non-robust test for the path delay fault associated with and the transition on . If or is an internal line, the requirement to detect a transition fault on guarantees that a test for will cause a transition to occur on even if it is an internal line. The transition is propagated to under the strong non-robust propagation conditions. The requirement to detect a transition fault on guarantees that a test will propagate fault effects from to an output if is an internal line. The ease of dealing with subpaths under the transition path delay fault model, and the uniformity in dealing with full paths and subpaths, is one of the reasons for using the transition path delay fault model in this work. The disadvantage of using this model is that fault simulation requires simulation of transition faults under every test, as discussed below. With an appropriate denition for the detection conditions of faults associated with subpaths, the procedures developed in this paper can be applied to other path delay fault models, including ones for which fault simulation requires only logic simulation. Given a two-pattern test , to nd the transition path delay faults detected by , the procedure from [16] rst simulates all the transition faults under . Next, the procedure marks all the lines with detected transition faults. It then identies a set of lines where detected transition path delay faults begin. The set is denoted by . A line is associated with a detected transition fault. In addition it satises one of the following conditions, which ensure that a detected transition path delay fault starting at cannot be extended towards the inputs. 1) is an input. 2) If is a gate output, none of the gate inputs is marked as having a detected transition fault. 3) If is a fan-out branch, the fan-out stem of is not marked as having a detected transition fault. Starting from every line in , the procedure traces all the possible paths using only lines that are marked as having detected transition faults. Tracing proceeds from the lines in towards the outputs. It stops when a path cannot be extended any further. The set of transition path delay faults detected by a test is denoted by . A given test set typically detects a limited number of transition path delay faults (or path delay faults in general). Therefore, there is no need to perform path selection for the purpose of transition path delay fault simulation. The fault simulation procedure used in this paper nds all the transition path delay faults detected by a given test set , and uses them as targets

Fig. 1.

TABLE I TEST SET

when it unspecies the test set. The set of transition path delay faults detected by is denoted by . The set is obtained by the following process. Initially, . For every test , the set of detected transition path delay faults, denoted by , is obtained as described earlier. After adding to , the fault simulation procedure removes from duplicated faults. It also removes faults that are contained in other faults. This is illustrated by the example in the next subsection. C. Example Fig. 1 shows ISCAS-89 benchmark . Table I shows a broadside test set for path delay faults. Table II shows the sets of transition path delay faults detected by the rst tests in . The transition fault on line is denoted by . Column full shows whether the path is a full path (indicated by a 1) or a subpath (indicated by a 0). After is added to , the transition path delay fault 1.01-8.10-12.10-25.01 appears twice, due to and due to . Only one appearance of this fault is retained. After is added to , the transition path delay fault 1.01-8.10-13.10-14.10-17.10-18.10-20.01-21.10-22.10-25.01, which is detected by , contains the transition path delay fault 14.10-17.10-18.10-20.01, which is detected by . The fault detected by is removed. Table III shows the set of detected transition path delay faults for and the tests that detect them. The test that detects a transition path delay fault is denoted by . According to Table III, the fault 4.10-19.10-20.01-21.1022.10-25.01 is detected by the test from Table I. If is unspecied into the test , the fault 4.10-19.10-20.01-21.10-22.10-25.01 is not detected, but the fault 4.10-19.10-20.01 is. Other tests address the detection of the fault 21.10-22.10-25.01. This illustrates a case

478

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

TABLE II SETS OF DETECTED FAULTS

TABLE IV TEST SET AFTER THE FIRST PROCEDURE

TABLE III SET OF DETECTED FAULTS

where unspecifying a test reduces the lengths of the paths associated with detected path delay faults. III. FIRST PROCEDURE FOR UNSPECIFYING A TEST SET The rst procedure for unspecifying a test set with a set of detected transition path delay faults maintains the detection of all the faults in . The procedure proceeds as described next. Section V includes a more formal description of the procedure. For every test and for every such that , the procedure attempts to unspecify the scan-in value . It

considers the scan-in values of all the tests one at a time in a random order. This helps in distributing the unspecied values as evenly as possible. When is considered, the procedure sets , where is an unspecied value. It updates by recomputing it as the next-state for and . It then performs fault simulation to determine the effect of the unspecied value on the set of detected transition path delay faults, . If the procedure nds that a fault from is not detected, it restores the previous, specied value of , and updates . Otherwise, it keeps unspecied. The procedure determines the effect on as follows. Since unspecifying can only affect the set of faults detected by , the procedure only checks whether all the faults in that are detected by continue to be detected. To simplify the check, it only checks whether the faults are detected by . This is implemented as follows. Let be the subset of that contains every fault with . Let , and suppose that . To check whether is detected, the procedure needs to simulate the transition faults included in . The procedure adds these faults to a set of target faults denoted by . Thus, for every includes the faults . The procedure simulates under . To accept the unspecied value on , all the faults in must continue to be detected. For illustration, the next example shows the process of unspecifying the test set of shown in Table I. Considering the scan-in values in a random order, the procedure rst attempts to unspecify . Based on Table III, and . Fault simulation of under , after setting and updating , shows that all the faults in are detected. Therefore, the unspecied value is accepted. Next, the procedure attempts to unspecify . Fault simulation of under , after setting and updating , shows that the fault 2.01 is not detected. Therefore, the procedure restores the specied value of and updates again. Considering next, the procedure nds that , , and that all the faults in are detected after setting and updating . Therefore, the unspecied value is accepted. After considering all the scan-in values in , the test set shown in Table IV is obtained. This test set detects the same transition path delay faults as the test set in Table I.

POMERANZ: COMPUTING TWO-PATTERN TEST CUBES FOR TRANSITION PATH DELAY FAULTS

479

IV. SECOND PROCEDURE FOR UNSPECIFYING A TEST SET The goal of the second procedure is to unspecify additional scan-in values, in order to make the test set more amenable to test data compression, at the cost of reducing the lengths of the paths associated with detected transition path delay faults. The procedure unspecies values and reduces path lengths gradually to produce a series of test sets. Any one of these test sets can be selected as the one that will be used for the circuit. The procedure is described next. A more formal description is given in Section V. The procedure is based on the following considerations. 1) While unspecifying the test set, the procedure considers the tests in one at a time. This provides a gradual decrease in path lengths while increasing the number of unspecied values. 2) The procedure considers the tests in by order of decreasing number of specied values, starting with the tests that have the highest number of specied values. In this way the procedure gives precedence to unspecifying these tests. 3) The shortest path that a transition path delay fault can be associated with is of length one. The largest number of unspecied values will be obtained if the procedure is allowed to reduce the path lengths associated with detected transition path delay faults to one. With a path of length one, a transition path delay fault consists of a single transition fault. Thus, allowing path lengths to be reduced to one is equivalent to requiring that the unspecied test set would detect all the transition faults that are detected by the completely-specied test set. This is the constraint used by the procedure. Experimental results indicate that the path lengths associated with detected transition path delay faults decrease gradually even though the procedure allows paths of length one to be obtained. For an even slower decrease in path lengths it is possible to dene longer subpaths of the transition path delay faults detected by every test, and use them while unspecifying the test. Before attempting to unspecify the scan-in values of a test , the procedure computes the set of transition faults that are only detected by . This set is denoted by . To obtain , the procedure performs transition fault simulation with fault dropping of the tests in excluding . It then simulates . The faults detected by are ones that are not detected by any other test in . These faults are included in . Using as the set of target faults, the procedure unspecies the scan-in values of one at a time in a random order. When is considered, the procedure sets and updates . It then performs fault simulation of under . If any of the faults in is not detected, the procedure restores the previous, specied value of , and updates . Otherwise, it keeps unspecied. It is possible to obtain if all the transition faults detected by are also detected by other tests. In this case, the procedure can unspecify all the scan-in values of . The procedure removes from the test set only after simulating transition path delay faults, as follows.

TABLE V TEST SET AFTER THE SECOND PROCEDURE

SET

TABLE VI AFTER APPLYING THE SECOND PROCEDURE

During transition path delay fault simulation, if a fault is detected by a test , the procedure sets . If a test does not have any transition path delay fault such that , the test is unnecessary and can be removed from . For illustration, the next example shows the application of this procedure to the test set of shown in Table IV. The test with three specied scan-in values is considered rst. Transition fault simulation where is simulated last shows that . Unspecifying the bits of one at a time in a random order, the procedure does not accept to unspecify and , but it accepts to unspecify . The test of the test set in Table IV is considered next. The procedure nds that . It does not accept to unspecify , but it unspecies . After considering all the tests, the test set shown in Table V is obtained. The set of detected transition path delay faults for this test set is shown in Table VI. Tables V and VI demonstrate the following effects. The test set of Table V has more unspecied values than the test set of Table IV. In particular, the test set of Table IV has a test with three specied scan-in values. In Table V the maximum number of specied scan-in values in any test is two. The cost is reduced path lengths associated with detected transition path delay faults. In general, there are also intermediate test sets with fewer unspecied values and higher path lengths.

480

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

TABLE VII TEST SETS FOR

TABLE VIII TEST SETS FOR

V. OVERALL PROCEDURE FOR UNSPECIFYING A TEST SET Procedures 1 and 2 given below summarize the procedures described in Sections III and IV, respectively. Given a test set , the proposed procedure applies Procedure 1 followed by Procedure 2. In both procedures, is used for storing the indices and of the scan-in values, , that the procedure needs to attempt to unspecify. is the set of faults that need to be detected by for to be unspecied. It is dened based on transition

path delay faults that are detected by in Procedure 1, and based on transition faults that are detected by in Procedure 2. In both cases, contains transition faults. Procedure 1: First procedure for unspecifying a test set. 1) Let be a given test set. Perform transition path delay fault simulation of to nd the set of detected transition path delay faults. 2) Set . 3) Select an entry from randomly. Remove from .

POMERANZ: COMPUTING TWO-PATTERN TEST CUBES FOR TRANSITION PATH DELAY FAULTS

481

TABLE IX TEST SETS FOR

4) Set

. 5) Set , and update . 6) Simulate under . If any fault from is not detected, set and update . 7) If , go to Step 3. Procedure 2: Second procedure for unspecifying a test set. 1) Let be a given test set. For every set to indicate that has not been considered yet. 2) Select a test with that has the highest number of specied scan-in values of all the tests with . Set . 3) Perform fault simulation with fault dropping of the set of transition faults under . 4) Continue fault simulation with fault dropping of the set of transition faults under . Include the transition faults detected by in . 5) Set . 6) Select an entry from randomly. Remove from . 7) Set , and update . 8) Simulate under . If any fault from is not detected, set and update . 9) If , go to Step 6.

. For every such that to

, add the faults

10) Perform transition path delay fault simulation of to nd the set of detected transition path delay faults. 11) For every , if does not contain any fault such that , remove from . 12) If there is a test with , go to Step 2. VI. RANDOMLY FILLED TEST SETS, AND COMPARISON OF SETS OF DETECTED FAULTS When compressed tests are applied to a circuit through decompression logic, the tests are completely-specied. The decompression logic may ll unspecied values with random values, or such that they are equal to other, specied values. This section discusses the random lling of incompletely-specied test sets. For ease of reference, the completely-specied test set to which the proposed procedure is applied, and the various test sets produced by the proposed procedure, are denoted as follows. is the completely-specied test set to which the proposed procedure is applied. is the test set obtained by applying Procedure 1 is the test set obtained after Procedure 2 unspecies the th test in the order by which it considers the tests. is the test set obtained after Procedure 2 considers all the tests.

482

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

TABLE X TEST SETS FOR

Let be an incompletely-specied test set obtained by the proposed procedure. The procedure described in this section lls the unspecied values of randomly to obtain a completelyspecied test set denoted by . Let be the set of transition path delay faults detected by . Let be the set of transition path delay faults detected by . When comparing with , it is guaranteed that every fault will have a corresponding fault such that is contained in (as a special case, may be obtained). This is due to the fact that randomly lling the unspecied values of can only increase the lengths of the paths associated with detected transition path delay faults. A more interesting comparison is of with , where is the set of transition path delay faults that are detected by the completely-specied test set . This comparison needs to take into account the following effects. The most dominant effect is expected to be that unspecied values in may result in a reduction of path lengths associated with detected transition path delay faults. Randomly lling these values may or may not recover the path lengths. However, the following competing effects also occur. was generated targeting path delay faults that are associated with the longest full paths. During transition path delay fault simulation, faults associated with shorter paths and subpaths are considered as well. Due to the random lling of , it is possible for to detect more faults than . It is also possible for to detect a fault associated with a longer subpath than . In general, this implies that may detect a fault that is not contained in any fault detected by .

However, the detection of transition path delay faults associated with shorter paths may cause the average path length associated with a detected transition path delay fault to be lower even when the test set detects faults associated with long paths. To alleviate these effects, the procedure used for comparing with matches every fault with exactly one fault based on . The fault may be one of the faults in , or it may be contained in such a fault. It is selected such that it is as similar to as possible, and it is associated with the longest possible path. This is based on the observation that may be replaced by one or more faults associated with shorter paths when is unspecied, and may or may not recover the detection of . The procedure computes for every by applying the following steps. 1) Considering the faults in by order of decreasing length, the procedure looks for the rst fault such that contains . If is found, the procedure sets and does not consider further. In this case, is matched with a fault that is similar to it. It may be the same or it may be associated with a longer path. It is possible for to be associated with a longer path than due to the random ll as discussed above. 2) Considering the faults in by order of decreasing length again, the procedure looks for the rst fault such that contains . If is found, the procedure sets and does not consider further. In this case, is as similar to as possible,

POMERANZ: COMPUTING TWO-PATTERN TEST CUBES FOR TRANSITION PATH DELAY FAULTS

483

TABLE XI TEST SETS FOR

TABLE XII TEST SETS FOR

but it is associated with a shorter path. The random ll does not recover the length of in this case. 3) If no match is found for during the rst or second step, the procedure considers subpaths of where it removes transition faults from the beginning and transition faults from the end of , for . Let be the fault obtained by removing transition faults from the beginning and transition faults from the end of . Considering the faults in by order of decreasing length, the procedure looks for the rst fault such that is contained in . The

. In this case, the best procedure sets match for is the part of corresponding to . Since detects all the transition faults detected by , it is guaranteed that when consists of a single transition fault, it will be contained in one of the faults in . Therefore, the third step guarantees that a match will be found for every fault in . After computing for every , the procedure computes a set that contains for every . The comparison between and is made based on and .

484

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

TABLE XIII TEST SETS FOR

Matching of sets of detected faults can also be applied to , which is the incompletely-specied test set produced by the proposed procedure, and from which was obtained. This allows the effects of the random ll in to be seen relative to based on the same matching of the sets of detected faults. VII. EXPERIMENTAL RESULTS This section reports on the application of the proposed procedure to benchmark circuits. The test sets to which the procedure was applied are the ones computed by the procedure from [17] as discussed in Section II. The results are shown in Tables VIIXIII. In order to show detailed results and demonstrate the effects of gradually increasing the numbers of unspecied values on path lengths, results are shown only for several benchmark circuits. The results are shown as follows. There are several rows in every table corresponding to different test sets. The type of the test set is shown under column . The corresponding test set is , using the notation introduced in the previous section. Of all the test sets obtained by Procedure 2, the tables report on the ones where a reduction is obtained in the maximum number of specied values for any test in the test set, or the total number of specied values in the test set is reduced by 10%. Each row is organized as follows. Column shows the total number of tests in . Column shows the percentage of specied scan-in values in , and the maximum percentage of specied scan-in values in any test. With state variables, the total number of scan-in values in is , and there are scan-in values per test. The percentages of specied scan-in values are computed with respect to these numbers. Column shows the total number of detected transition path delay faults, the number of detected faults that are associated with full paths, and the number of detected faults that are associated with subpaths. Column shows the average length of a path associated with a detected transition path delay fault considering all the detected faults, considering detected faults associated with full paths, and considering detected faults associated with subpaths.

Column shows the normalized run time of the proposed procedure. For normalization, the run time is divided by the run time for simulating . Normalization to the fault simulation time of is appropriate since the proposed procedure is based on fault simulation. Column shows the average length of a path associated with a detected transition path delay fault using the matching of sets of detected faults described in Section VI. Subcolumn shows this information for the test set . Subcolumn shows this information for the test set obtained after the random values of are lled randomly. The following points can be seen from the tables. Large numbers of detected transition path delay faults are associated with subpaths. Therefore, it is important to consider subpaths during the process of unspecifying a test set. The rst procedure reduces the percentages of specied values without affecting the detected transition path delay faults. The reduction is limited by the need to detect the same transition path delay faults as the completely-specied test set. In all the cases, the maximum percentage of specied values for a test remains high. The second procedure is able to reduce the percentages of specied values signicantly compared with the rst procedure. While the transition fault coverage remains the same, the number of detected transition path delay faults is reduced, and the lengths of the paths associated with detected faults are reduced. The reductions are gradual, and allow an appropriate test set to be selected for every circuit depending on the constraints of a test data compression method. Randomly lling a test set that has unspecied scan-in values increases the lengths of the paths associated with detected transition path delay faults. Typically there are several test sets (the rst test sets produced by the proposed procedure) where the average length of the paths associated with transition path delay faults that are detected by is close to that of . It may be slightly higher if there are detectable faults that are associated with long subpaths, or if does not detect all the detectable transition path delay faults associated with the longest paths. It is possible to stop the application of Procedure 2 when the percentage of unspecied values is high enough such that a selected test data compression method can be applied to the test

POMERANZ: COMPUTING TWO-PATTERN TEST CUBES FOR TRANSITION PATH DELAY FAULTS

485

set. This would limit the run time of the procedure, and prevent path lengths from being reduced unnecessarily. VIII. CONCLUDING REMARKS This paper described two procedures for unspecifying a twopattern test set for transition path delay faults in full-scan circuits. Both procedures unspecify scan-in values. The rst procedure ensures that the same transition path delay faults will be detected by the test set after it is unspecied. To allow additional scan-in values to be unspecied, and thus make the test set more amenable to test data compression, the second procedure allows the lengths of the paths associated with the detected transition path delay faults to be reduced. Experimental results demonstrated that the second procedure is able to unspecify signicant numbers of scan-in values that the rst procedure cannot unspecify. When the unspecied values were lled randomly, the path lengths were increased, and became closer to those of the completely-specied test set to which the procedure was applied. Thus, it is possible to allow scan-in values to be unspecied while reducing the path lengths associated with detected path delay faults even if the goal is to maintain the path lengths of the completely-specied test set. The comparison of the sets of detected path delay faults of different test sets used a matching of detected faults. The matching provided a more accurate assessment of the effects of unspecifying values and of randomly lling them on path lengths associated with detected faults. REFERENCES
[1] K. Lee, J. Chen, and C. Huang, Using a single input to support multiple scan chains, in Proc. Int. Conf. Comput.-Aided Design, 1998, pp. 7478. [2] C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koenemann, OPMISR: The foundation for compressed ATPG vectors, in Proc. Int. Test Conf., 2001, pp. 748757. [3] B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, A smartBIST variant guaranteed encoding, in Proc. Asian Test Symp., 2001, pp. 325330. [4] J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.-H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G. Eide, and J. Qian, Embedded deterministic test for low cost manufacturing test, in Proc. Int. Test Conf., 2002, pp. 301310. [5] P. Goel and B. C. Rosales, Test generation and dynamic compaction of tests, in Proc. Test Conf., 1979, pp. 189192.

[6] I. Pomeranz, L. N. Reddy, and S. M. Reddy, COMPACTEST: A method to generate compact test sets for combinational circuits, IEEE Trans. Comput.-Aided Design, vol. 12, no. 7, pp. 10401049, Jul. 1993. [7] S. Kajihara and K. Miyase, On identifying dont care inputs of test patterns for combinational circuits, in Proc. Int. Conf. Comput.-Aided Design, 2001, pp. 364369. [8] A. El-Maleh and A. Al-Suwaiyan, An efcient test relaxation technique for combinational & full-scan sequential circuits, in Proc. VLSI Test Symp., 2002, pp. 5359. [9] K. Fuchs, F. Fink, and M. H. Schulz, DYNAMITE: An efcient automatic test pattern generation for path delay faults, IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 10, no. 10, pp. 13231335, Oct. 1991. [10] U. Sparmann, D. Luxenburger, K.-T. Cheng, and S. M. Reddy, Fast identication of robust dependent path delay faults, in Proc. Design Autom. Conf., 1995, pp. 119125. [11] S. Kajihara, K. Kinoshita, I. Pomeranz, and S. M. Reddy, A method for identifying robust dependent and functionally unsensitizable paths, in Proc. VLSI Design Conf., 1997, pp. 8287. [12] K. Heragu, J. H. Patel, and V. D. Agrawal, Fast identication of untestable delay faults using implications, in Proc. Int. Conf. Comput.-Aided Design, 1997, pp. 642647. [13] S. Padmanaban and S. Tragoudas, A critical path selection method for delay testing, in Proc. Int. Test Conf., 2004, pp. 232241. [14] K. Heragu, J. H. Patel, and V. D. Agrawal, Segment delay faults: A new fault model, in Proc. VLSI Test Symp., 1996, pp. 3239. [15] M. Sharma and J. H. Patel, Testing of critical paths for delay faults, in Proc. Int. Test Conf., 2001, pp. 634641. [16] I. Pomeranz and S. M. Reddy, Path selection for transition path delay faults, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 3, pp. 401409, Mar. 2010. [17] I. Pomeranz and S. M. Reddy, Input necessary assignments for testing of path delay faults in standard-scan circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 2, pp. 333337, Feb. 2011. Irith Pomeranz (M89SM96F99) received the B.Sc. degree (summa cum laude) in computer engineering and the D.Sc. degree from the Department of Electrical Engineering, TechnionIsrael Institute of Technology, Haifa, Israel, in 1985 and 1989, respectively. From 1989 to 1990, she was a Lecturer with the Department of Computer Science, the Technion. From 1990 to 2000, she was a faculty member with the Department of Electrical and Computer Engineering, University of Iowa. In 2000, she joined the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN. Her research interests include testing of VLSI circuits, design for testability, synthesis and design verication. Dr. Pomeranz was a recipient of the NSF Young Investigator Award in 1993 and the University of Iowa Faculty Scholar Award in 1997. She is a Golden Core Member of the IEEE Computer Society.