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3, MARCH 2013

IR-Drop in On-Chip Power Distribution Networks

of ICs With Nonuniform Power Consumption

Josep Rius, Member, IEEE

AbstractA compact IR-drop model for on-chip power

distribution networks in array and wire-bonded ICs is analyzed.

Chip dimensions, size, and location of the supply pads, metal

coverage, piecewise distribution of IC consumption, and the

resistance between the pads and the power supply are considered

to obtain closed-form expressions for the IR-drop. The IR-drop

model is validated by comparing its results with electrical

simulations. The obtained error is in the range of 1%.

Index TermsIC modeling, IR-drop, power distribution

networks (PDNs), power supply noise (PSN).

I. INTRODUCTION

T

O ENSURE a good supply voltage throughout the IC, and

for the high-consumption and high-density ICs available

in current technologies, the on-chip power distribution network

(PDN) is usually organized as a grid of wide parallel wires

in the two or more upper metal layers covering the IC

surface. Connection to the package is currently made by two

approaches: the so-called peripheral bonding, in which the

supply pads are distributed along the sides of the IC, and

array bonding, where the supply pads are distributed in an

array over the whole IC surface, in a ip-chip package.

The PDN behaves as a conductive mesh with resistive,

inductive, and capacitive properties. As a consequence, the

electric current spikes produced during the circuit activity are

transformed into voltage bounces at the supply terminals of the

internal circuits. This power supply noise (PSN) has several

undesirable effects on the performance and reliability of ICs

[1]. A good PDN design is therefore necessary to reduce the

PSN below a specied value. The PSN can be roughly divided

into static and dynamic. Static PSN, or IR-drop, is the voltage

drop caused by the DC supply current in the PDN resistances,

whereas dynamic PSN is due to transients exciting the PDN

inductances and capacitances. The analysis of the IR-drop is

important [2], [3], [1] because it allows addressing the most

important issues in PDN design, that is, width and pitch of

the PDN wires [4][8], [9] and size, number, and location of

pads [10], [11], [4], [5], [12][13]. When a dynamic analysis

of the PSN is required, there are additional important issues

to solve, such as the impact of on-chip PDN inductance [14],

[15] and the amount and distribution of on-chip decoupling

capacitance [15], [1].

Manuscript received June 6, 2011; revised November 9, 2011; accepted

February 16, 2012. Date of publication March 20, 2012; date of current version

February 20, 2013.

The author is with the Department of Electronic Engineering,

Universitat Politecnica de Catalunya, Barcelona 08028, Spain (e-mail:

josep.rius@upc.edu).

Digital Object Identier 10.1109/TVLSI.2012.2188918

The design of a good, reliable on-chip PDN of a digital IC

is a very complex task because designers cannot anticipate all

the details of the design. The PSN depends on the location,

size, and activity of the circuit blocks. Therefore, in order to

check that the PSN is below the specied value, it is necessary

to simulate the complete circuit, which is clearly unfeasible

for large ICs. The help of specic CAD tools alleviates this

problem. However, due to the simulation time, CAD tools are

primarily intended for use in postlayout verication, after the

design is complete. A failure in the design involves a costly

rework of the PDN. This leads to overdimensioning, resulting

in the sacrice of valuable routing resources. For this reason,

the use of prelayout tools in the early stages of the PDN

design, which give approximate results for the PSN expected,

becomes a necessity [16], [9], [17].

This paper is exclusively centered on IR-drop. It addresses

the estimation of the PDN performance in the early steps of an

IC design by an analytical approach. As mentioned, this prob-

lem can also be tackled with numerical tools. However, the

analytical approach has the advantage that, in addition to pro-

viding a numerical solution, it shows the relationships between

the signicant parameters, improving the understanding of the

problem. Thus, there is room for an analytical tool that, in an

interactive fashion, rapidly provides approximate results for

the expected IR-drop of a PDN. This tool shows the depen-

dency of IR-drop on the number and size of pads and consum-

ing blocks, IC dimensions, current density and sheet resistance,

thus allowing rapid optimization of these parameters.

In their seminal paper [16], Shakeri and Meindl demonstrate

that the PDN can be approximated as a continuous layer of

conductive material and that IR-drop can be calculated by

solving a partial differential equation, that is, Poisson equation,

with the proper boundary conditions and source function. This

paper takes as the starting point the framework and denition

of the problem as presented in [16] without repeating the

derivation of the Poisson equation and related concepts, which

are extensively discussed in [16]. The organization of this

paper is as follows. Section II presents the problem to solve.

In Section III, expressions to obtain the IR-drop at any point

of an innite array-bonded PDN are derived for any number

and location of pads and any number of rectangular consuming

blocks. The results are used in Section IV to nd the solution

of the same problem in nite PDNs. In Section V, we compare

our formulas with electrical simulations of several PDNs.

Section VI discusses some features of the proposed approach

and nally, Section VII summarizes the conclusions of this

paper.

10638210/$31.00 2012 IEEE

RIUS: IR-DROP IN ON-CHIP POWER DISTRIBUTION NETWORKS OF ICs 513

Fig. 1. IC with six consuming blocks and an array of power/ground pads.

II. STATEMENT OF THE PROBLEM

According to the approach of [16], the IR-drop in a PDN

follows the Poisson equation:

2

V = R

S

J (1)

where V is the IR-drop (V), R

S

is the sheet resistance of the

PDN (), and J is the current density function (A/m

2

). The

sheet resistance R

S

is assumed to be constant in the whole

IC. In the array-bonding conguration, the supply current

drawn by the consuming blocks is supplied by an array of

power/ground pads distributed over the IC surface. Fig. 1

illustrates an IC with six blocks and an array of power/ground

pads (small black and white squares).

In the array-bonding conguration, the normal derivative of

the voltage, V/n (where symbol n in a rectangular IC means

either x or y), at the four sides of the PDN is zero; that is, the

current drawn by the blocks ows from the power to ground

pads through the PDN.

The solution of (1) for the simple case of constant J in an

innite IC with an innite PDN and an innite regular array

of pads is shown in [16]. A solution for the IR-drop at any

point is given in the form of several double and triple innite

series in [16]. After some approximations and numerical work,

the authors show that the maximum IR-drop (which is at the

center of a square with four supply pads at its vertices) is

given by

V

IRmax

=

R

S

I

PAD

2

ln

_

0.387a

D

PAD

_

(2)

where a is the distance between adjacent pads, is a correc-

tion factor related to the pad shape, and D

PAD

is the side

length of a square pad. The coefcient 0.387 is obtained

after a numerical calculation of the double and triple innite

series and assuming several approximations. Equation (2)

puts together the relevant variables in PDN design: the sheet

resistance of the power grid, R

S

, which is related to the metal

coverage of such grid; the current per pad, I

PAD

; the pad

density, a, which is related to the distance between the pads;

and the pad size, D

PAD

.

a

b

PAD

observation

point P

r

pp

r

pxy

dxdy

A

a

p

R

pad

V

0

a

b

PAD

observation

point P

r

pp

r

pxy

dxdy

A

a

p

R

pad

V

0

Fig. 2. Parameters involved in the analysis of the IR-drop at the observation

point P in an innite resistive plane with one pad and one consuming block.

In Sections III and IV, we obtain approximate expressions

for the IR-drop under more realistic conditions, that is, the

current density J is not constant in the whole IC and/or

the PDN is of nite dimensions. Instead of solving (1)

directly, we use several results from potential theory and

conformal mapping techniques to nd the IR-drop in these

cases.

At this point, it is appropriate to say that if the sheet

resistance R

S

of the PDN is nonisotropic, that is, if the sheet

resistance in the x-direction, R

SX

, and in the y-direction, R

SY

,

is different, a change in the independent variables x and y

makes the sheet resistance isotropic at the small price of a

change in the PDN dimensions [16]. Hence, our analysis only

considers the isotropic case, with R

S

constant.

Moreover, our analysis is intended for circular pads but, as

shown in [16] and [18], it can be extended to square pads by

using the concept of a circular pad of equivalent radius having

the same resistance to the PDN as the square pad.

III. IR-DROP IN AN INFINITE PDN

Let us now attack the following simpler problem: we

consider an innite PDN as a continuous conductive surface

with constant sheet resistance R

S

. A single block A of

dimensions a b m

2

and a constant current density J A/m

2

is connected to the PDN at an arbitrary place. At another

arbitrary point, there is a circular pad of radius a

P

that

supplies the current I

PAD

= abJ required by A. A resistance

R

pad

connects the pad to the power supply, which is assumed

to be at a constant voltage V

0

= 0. Fig. 2 illustrates the

geometry of the problem. The IR-drop between the pad

(whose voltage is V

pad

= JabR

pad

) and the potential V

P

at

any observation point P over the PDN is found as follows.

We denote the distance between the center of the pad and

the observation point P as r

Pp

, and the distance between

the differential area dxdy inside A and point P as r

Pxy

. The

potential at P is [19]

V

P

=

J R

S

2

a

_

0

b

_

0

ln

_

r

Pxy

_

dxdy

JabR

S

2

ln

_

r

Pp

_

. (3)

514 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

a

b

PAD

1

observation

point P

r

P1

r

pxy

dxdy

A

PAD

2

PAD

3

r

P2

r

P3

PAD

N

r

PN

a

p2

a

pN

a

p1

a

p3

R

pad

V

0 R

pad

V

0

R

pad

V

0

R

pad

V

0

a

b

PAD

1

observation

point P

r

P1

r

pxy

dxdy

A

PAD

2

PAD

3

r

P2

r

P3

PAD

N

r

PN

a

p2

a

pN

a

p1

a

p3

R

pad

V

0

R

pad

V

0 R

pad

V

0

R

pad

V

0

R

pad

V

0

R

pad

V

0

R

pad

V

0

R

pad

V

0

Fig. 3. Parameters involved in the analysis of the IR-drop at the observation

point P in an innite resistive plane with multiple pads and one consuming

block.

Integrals like the one in (3) are well known in engineering

electromagnetics. Their explicit solution can be found else-

where [20]. They dene the so-called geometric mean distance

(GMD) between a point P and the rectangular block A, as

shown in the following equation:

a

_

0

b

_

0

ln

_

r

pxy

_

dxdy = ab ln (GMD

P

) . (4)

Now, (3) can be written as

V

P

=

J R

S

ab

2

ln

GMD

P

r

Pp

. (5)

If point P is at a distance a

P

from the center of the pad,

that is, at any point of its circumference, then the following

equalities hold:

r

Pp

= a

P

, V

P

= V

pad

, GMD

P

= GMD

pad

(6)

where GMD

pad

is the GMD from the center of the pad to

A, which is assumed to be the same as the distance from the

circumference of the pad to A provided that the pad radius a

P

is small with respect to the block dimensions.

Now the complete IR-drop, V

P

, between the power supply

and point P becomes

V

P

=

J R

S

ab

2

ln

_

GMD

pad

GMD

P

r

Pp

a

P

_

+ JabR

pad

. (7)

Let us now generalize this result for N pads.

A. Multiple Pads

Imagine the same block A and N circular pads, PAD

1

,

PAD

2

, , PAD

N

, of radius a

P1

, a

P2

, , a

PN

, and equal

resistances R

pad

, distributed on an innite PDN. It is assumed

that the pads are widely separated, that is, the distances

between them are much greater than their radius, r

i j

>> (a

Pi

,

a

Pj

). Fig. 3 shows the involved geometry.

Each pad supplies a fraction

by A. Thus

I

PADi

=

i

Jab,

N

i=1

i

= 1. (8)

Now we can write

V

P

=

JabR

S

2

ln (GMD

P

)

1

JabR

S

2

ln (r

P1

)

2

JabR

S

2

ln (r

P2

)

N

JabR

S

2

ln (r

PN

) .

(9)

That is

V

P

=

JabR

S

2

ln

GMD

P

N

i=1

r

i

Pi

(10)

where GMD

P

is the GMD between point P and block A, and

r

Pi

is the distance between point P and pad i , which supplies

the fraction

i

of the total current.

By applying the above principle, we can nd the IR-drop

between point P and the pad voltage. To do so, we place

point P at a distance a

Pi

from the center of pad i , that is, at

its circumference. Thus, the following equalities hold:

V

P

= V

pad i

=

i

JabR

pad

GMD

P

= GMD

i

r

P1

= r

i1

, r

P2

= r

i2

, . . . ,

r

Pi

= a

Pi

, . . . , r

PN

= r

i N

. (11)

By grouping together all the terms in i , we obtain the

following set of N equations, one for each value of i , with N

unknowns (the values of )

ln GMD

i

N

j =i

j

ln r

i j

i

_

ln a

Pi

2

R

pad

R

S

_

= 0,

i = 1, 2, . . . , N. (12)

Such N equations are not linearly independent because

of (8). However, we can subtract each equation in (12) from

its predecessor and build N 1 equations. These, together

with (8) form a system of N linearly independent equations

with N unknowns, as shown in (13)

ln

GMD

i

GMD

i+1

=

i

_

ln

a

Pi

r

i+1,i

2

R

pad

R

S

_

+

i+1

_

ln

r

i,i+1

a

P,i+1

+2

R

pad

R

S

_

+

N

j = i

j = i +1

j

ln

r

i j

r

i+1, j

N

i=1

i

= 1. (13)

RIUS: IR-DROP IN ON-CHIP POWER DISTRIBUTION NETWORKS OF ICs 515

This system can be written in matrix form as

ln

a

P1

r

21

2

R

pad

R

S

ln

r

12

a

P2

+2

R

pad

R

S

ln

r

1,N1

r

2,N1

ln

r

1,N

r

2,N

ln

r

21

r

31

ln

a

P2

r

32

2

R

pad

R

S

ln

r

2,N1

r

3,N1

ln

r

2,N

r

3,N

ln

r

N1,1

r

N1

ln

r

N1,2

r

N2

ln

a

P,N1

r

N,N1

2

R

pad

R

S

ln

r

N1,N

a

PN

+2

R

pad

R

S

1 1 1 1

2

.

.

.

ln

GMD

2

GMD

1

ln

GMD

3

GMD

2

ln

GMD

N

GMD

N1

1

M = B (14)

where M is an N N matrix, and and B are column

vectors of N elements. Now, vector can be easily calculated

with (15)

= M

1

B (15)

and the N elements of are the coefcients we are looking

for. As a simple example, if N = 2, the explicit result is

1

=

1

2

+

1

2

ln

GMD

2

GMD

1

ln

r

12

a

P

+2

R

pad

R

S

2

=

1

2

1

2

ln

GMD

2

GMD

1

ln

r

12

a

P

+2

R

pad

R

S

. (16)

B. Completing the Solution

The total IR-drop, V

P

, between the power supply and

point P can be calculated as the sum of the voltage drop

at the R

pad

of a reference pad plus the IR-drop from this pad

to point P. As any pad can be selected as the reference, we

choose pad 1. Thus, the formula for V

P

becomes

V

P

=

JabR

S

2

ln

GMD

1

GMD

P

N

j =1

r

j

Pj

a

1

P1

N

j =1

r

j

1 j

+

1

JabR

pad

(17)

which reduces to (7) if N = 1.

As can be seen, the problem of nding the IR-drop at any

point of an innite PDN having one consuming block and N

pads is solved if the fraction of the current supplied by each

pad (coefcients ) is known.

Because of the linearity of the problem, it is easy to

generalize (17) for M blocks by applying superposition. Thus,

the previous procedure is repeated M times, one for each

block, to calculate vectors

1

,

2

, ,

M

. Then, the total

IR-drop at any point is found by summing the contribution of

each block: V

P(total)

=

M

j =1

V

Pj

.

C. Flexibility and Generality of (17)

Under the above assumptions, (17) gives the IR-drop at any

point of a PDN with a sheet resistance R

S

, a number N of

circular pads of radius a

P

and resistance to power supply R

pad

,

and one block of dimensions a b with a current density J.

XX

a

a

2a

a

P

Fig. 4. Calculation of the IR-drop at the center of a square with four pads

and one square consuming block and an innite resistive plane.

Note that under the assumption of innite dimension for the

PDN, (17) is fully exible, which allows deciding on the

size and location of the consuming block, and the number,

radius, and location of pads. As will be shown in Section V,

the IR-drop V

P

as calculated from (17) provides a very

good approximation of the real IR-drop of nite PDNs if the

consuming block is not very close to the external borders of

the pad array, that is, the IC sides.

Equation (17) can also be used to calculate the maximum

IR-drop under the same conditions as those analyzed by Shak-

eri and Meindl in [16]. In this paper, the maximum IR-drop

(which is placed at the center of the square formed by four

pads) is given by (2), where the numerical coefcient is known

after a long calculation of several double and triple Fourier

series and assuming several approximations. The interested

reader may read [16] for details. As will be shown here, (2)

can be derived from (17), when the latter is applied to this

particular case.

Let us consider the square consuming block in Fig. 4, which

is embedded in an innite PDN with a sheet resistance R

S

.

In this example, R

pad

= 0. The side length of the block is

2a, which is twice the distance between adjacent pads. It

has four circular pads with the same radius a

P

symmetrically

distributed in the block. Note that this geometry reproduces

the scenario studied by Shakeri and Meindl, except that in

this case the consuming block is nite. Let us now use (17)

to calculate V

P

at its center, that is, the point marked with

X in Fig. 4.

In these conditions, (17) becomes

V

X

=

4Ja

2

R

S

2

ln

GMD

1

r

1

X1

r

2

X2

r

3

X3

r

4

X4

GMD

X

a

1

P

r

2

12

r

3

13

r

4

14

=

Ja

2

R

S

2

ln

_

GMD

1

r

1

X1

r

2

X2

r

3

X3

r

4

X4

GMD

X

a

1

P

r

2

12

r

3

13

r

4

14

_

4

. (18)

Due to the particular symmetry of the gure, (18) becomes

V

X

=

Ja

2

R

S

2

ln

GMD

1

2

1

2

a

1

4

GMD

X

2 2

1

8

a

1

4

P

4

=

I

PAD

R

S

2

ln

0.3797a

a

P

(19)

516 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

4 pads

16 pads

36 pads

64 pads

X

4 pads

16 pads

36 pads

64 pads

X

Fig. 5. Shakeri and Meindls problem [16]: calculation of the IR-drop at the

center of a square. The number of pads and the area of the square consuming

block tend to innity.

where GMD

1

and GMD

X

are calculated as functions of a from

the solution of (4), according to [21]. This result is very close

to Shakeri and Meindls formula (2). Now, to reproduce the

case in [16], we increase the size of the block and the number

of pads, as shown in Fig. 5.

In this way, we obtain an asymptotic equation for V

X

by

generalizing (18)

V

X

=

I

PAD

R

S

2

ln

_

coef a

a

P

_

. (20)

We check the coefcient of (20) for different numbers N

of symmetrically distributed pads. The results are shown in

Table I.

As can be seen, when N increases, the numerical coefcient

coef tends to a denite value which is very close to that

reported by Shakeri and Meindl in [16].

It is worth pointing out that the method to obtain the

numerical coefcient of (2) presented in our paper is much

simpler than that in [16] and gives practically the same results

under the same conditions. In addition, it is much more exible

and can be applied to a variety of cases because it does not

impose any restriction on the number, size, or symmetry of

the distribution of the consuming blocks and pads.

IV. IR-DROP IN A FINITE PDN

In Section III, we made a strong assumption of a PDN of

innite extension. Here, we remove this assumption because

it gives erroneous results in the estimation of the IR-drop

when the consuming blocks are close to the IC sides. In

fact, on-chip PDNs are on top of dies of nite dimensions,

L units wide and H units high. Let us now extend the results

of Section III to obtain the IR-drop for such PDNs. This

extension is based on the conformal transformation of the

interior of a rectangle in a complex plane Z into the upper

TABLE I

COEFFICIENT coef OF (20) AS A FUNCTION OF NUMBER OF PAD IN FIG. 5

N Calculated coef

4 0.3797

16 0.3810

36 0.3813

64 0.3814

100 0.3814

half of another complex plane W. Conformal transformation

is a mathematical technique that uses the functions of com-

plex variables to map complicated boundaries into simpler,

more readily analyzed congurations [21]. After the problem

is solved in the transformed conguration, inverting these

functions allows coming back to the original geometry. This

technique is restricted to 2-D elds satisfying Laplace or

Poisson equation, as in our case, and has been successfully

applied to many engineering problems. A good summary of

the technique and its applications can be read, for instance, in

the rst chapter of [21].

It is well known [21] that the Jacobi elliptic function w =

sn(z,k) maps the interior of a rectangle with vertices K, K,

K + j K

, K + j K

half of the complex plane W. Here, j = sqrt(1) and K and

K

related to the dimensions of the rectangle; the modulus k of

the elliptic functions can be calculated as follows [22]:

k =

_

3

_

2

(21)

where

2

and

3

are elliptic theta functions of the second and

third kind with zero argument. These functions are calculated

as follows [22]:

2

=

n=0

2q

_

n+

1

2

_

2

3

= 1 +

n=0

2q

n

2

q = e

L

H

. (22)

With this transformation, the side L/2, L/2 of the rectangle

in plane Z becomes the segment 1, 1 of the real axis of

plane W. The side L/2, L/2+jH of the rectangle becomes the

segment 1, 1/k of the real axis of plane W, whereas the side

L/2, L/2+jH becomes the segment 1, 1/k, and the side

L/2+jH, L/2+jH becomes the rest of the real axis of plane

W [21]. A sketch of the transformation showing the lines of

constants x and y is shown in Fig. 6(a) and (b).

Fig. 6(a) shows a square PDN with L = 1 and H = 1.

This PDN has nine identical pads identied by black circles.

The top and bottom sides of the square are drawn in black

and the left and right sides in gray. This square is mapped in

plane Z with its origin at the center of the bottom side. The

transformation w = sn(z, k) maps points z = x + j y of the

interior of this square into points w = u + j v of the upper half

of W, as drawn in Fig. 6(b). Thus, the origin of plane W is

also the origin of plane Z, and point jK

in Z is transformed

RIUS: IR-DROP IN ON-CHIP POWER DISTRIBUTION NETWORKS OF ICs 517

-0.6 -0.4 -0.2 0 0.2 0.4 0.6

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

x

jy

-0.6 -0.4 -0.2 0 0.2 0.4 0.6

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

x

jy

(a)

-8 -6 -4 -2 0 2 4 6 8

0

2

4

6

8

10

12

14

16

jv

u

-8 -6 -4 -2 0 2 4 6 8

0

2

4

6

8

10

12

14

16

jv

u

(b)

Fig. 6. (a) Square PDN with L = 1, H = 1, nine pads (circles), and a rectangular block (thick line), represented in plane Z. (b) Same PDN, pads, and

block, represented in plane W. Dashed lines are the lines of constants x and y in plane Z (and constants u and v in plane W).

into the innity point in W. The size of pads is also modied,

being greater in W when they are far from the real axis and

smaller when they are close to the real axis. Notice that the

points of the real axis, v = 0 in W, are the transformed points

of the four sides of the rectangle in plane Z.

The current at the four sides of the PDN (the four sides of

the rectangle in Z) is zero. Therefore, the real axis of plane W

must have the same property, that is, the Neumann boundary

condition V/n = 0 must be satised in the real axis of W.

To force this condition, we need to add to W the image of the

upper half-plane [that is, the conjugate of plane W, conj(W)]

including the pads of the original W domain at their conjugate

coordinates.

After this step, we build the innite domain W

= WU

conj(W). By including the current sources in W and conj(W),

we can calculate the IR-drop in this innite domain using the

methods in Section III. However, caution must be taken when

including the current sources (rectangular blocks). Equation

(4) for GMD, as derived in [20], is valid only for rectangular

blocks. Therefore, this solution cannot be used directly in

W

nonrectangular gure in W

in Z, in W

To overcome these restrictions, we use two results from

the theory of conformal mapping [19], [21]. The rst one is

that the regions about the corresponding points z and w are

innitesimally similar. This means further that angles between

the intersecting lines in plane Z are preserved between the

corresponding lines in plane W [19]. That is, if the circles

or squares in Z are sufciently small, their transformed

images in W are also circles and squares. The second one

is the invariance of the Poisson equation under a conformal

transformation, in other words, a differential area dx dy at

a point z Z transforms into a differential area du dv at a

point w W with a change of scale equal to | f

(z)|

2

and a

rotation of angle equal to the argument of f

(z), with f

(z)

being the derivative of the transformation f at point z. In our

case, f

(z) = sn

are also Jacobi elliptic functions.

With these results, the application of the methods in

Section III to W

possible if the radius of pads are small with respect to L and

H and if the blocks are small. If the blocks are large, they must

be divided into small square sub-blocks, and each transformed

sub-block in W

square, which is the image of the original sub-block in Z.

Bearing the above in mind, the procedure to nd the IR-drop

V

P

at any point of a nite PDN is as follows.

1) Map the PDN in plane Z into the half-space W by the

transformation w = sn(z). This mapping must include

the pads with scaled radius.

2) If necessary, divide the consuming blocks in Z into small

sub-blocks, and map them into W, scaling and rotating

them as required.

3) Add to W the conjugate half-plane conj(W) including

the transformed pads and blocks (or sub-blocks) in

conjugate positions. We now have the innite domain

W

= WU conj(W).

4) Obtain the IR-drop V

P

at any point P

W

W

PDN considering all pads and all blocks (including the

conjugate ones).

5) Finally, come back to plane Z by using the inverse

function z = sn

1

(w,k) and nd the potential at point

P

Z

Z. The inversion requires calculating an incom-

plete elliptic integral of the rst kind, which is a standard

built-in function in any computer algebra system.

V. VALIDATION OF THE RESULTS

The above method was validated by comparing the calcu-

lated IR-drop with electrical simulations of PDNs of array-

bonded ICs with a range of values of their parameters.

The error metric is dened as the normalized difference

518 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

.

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.

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.

.

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.

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.

Fig. 7. IC with an array of 16 pads and a block within the array.

Fig. 8. IC with an array of four pads and a block at the IC side.

between the value of the maximum IR-drop obtained by

the method described here and the value obtained from the

simulations.

A. Innite PDN

First, we compare the IR-drop predicted from the results

of Section III (innite PDN) with the electrical simulation

results. Fig. 7 illustrates the following case: one consuming

block of 12.5 mm

2

inside a chip of 10 10 mm

2

and an

array of 16 regularly spaced pads of radius 100 m. Here,

R

pad

= 0.

In this case, the consuming block is fully inside the array

of pads. As expected, the error in the IR-drop at any place

(including the location of its maximum) is small, that is, less

than 0.5%.

However, when the consuming block is at the chip side (that

is, totally or partially outside the array of pads), the error is

much greater. This is the case, for example, of Fig. 8: one

consuming block of 8 mm

2

inside a chip of 10 10 mm

2

and

four regularly spaced pads of radius 200 m. Here, R

pad

= 0.

Now the error is as large as 25%, which is an unacceptable

value. Fig. 9(a) and (b) shows the IR-drop distribution in

the electrical simulation and the calculation, respectively. The

differences resulting from the assumption of an innite PDN

are clearly visible.

Fig. 9. Difference of IR-drop on the PDN surface between (a) electrical

simulation and (b) calculation when an innite PDN is assumed in the IC of

Fig. 8.

B. Finite Rectangular PDN

To compare our results with the simulations of nite PDNs,

we dened chips of different sizes and features, including a

number of pads of different sizes excited by consuming blocks

of different sizes at different places and drawing different

currents.

In the HSPICE simulations, the PDN was dened as an

array of cells modeling the regular grid of metal segments

with the same length in the X and Y directions and same

width. These interconnected cells form the whole PDN. The

length of each segment was 100 m, and in our simulations

the square pads had a side length D

pad

of 1, 2, or 3 segment

lengths. According to the approach described in Section II,

an appropriate coefcient multiplying D

pad

was calculated

to obtain the equivalent radius of the circular pads with

the same resistance to the PDN as the square pads used

in the simulations. This coefcient depends on the number

of segments connected to the square pads in horizontal and

vertical directions. For 1, 2, and 3 segments, its value is

0.7071, 0.6334, and 0.6049, respectively. If the number of

segments goes to innity, this coefcient tends asymptotically

to 0.5903, which is the value given in [18] and used in [16].

The simplest check of our formulas is the comparison of

the maximum IR-drop when the consuming block is the whole

chip. The results are summarized in Table II, where the rst

column gives the chip size, the second, the length of a side of

RIUS: IR-DROP IN ON-CHIP POWER DISTRIBUTION NETWORKS OF ICs 519

TABLE II

IR-DROP IN ICS WHERE THE CONSUMPTION IS CONSTANT IN THE WHOLE CHIP

Chip size (mm

2

) D

pad

(m) No. of pads r

segment

() R

S

() J(mA/mm

2

) V

calc

(mV) V

sim

(mV) Error (%)

7.2 7.2 200 9 4.4 2.2 25 100.0 99.3 +0.7

7.2 7.2 200 36 2.2 1.1 25 8.23 8.15 +0.98

2.6 2.6 100 4 4.4 2.2 25 28.81 28.73 +0.28

2.6 2.6 300 4 4.4 2.2 25 15.16 15.01 +1.0

10.4 10.4 100 64 2.2 1.1 25 14.40 14.36 +0.3

10.4 10.4 300 64 2.2 1.1 25 7.44 7.51 0.93

10.4 10.4 200 16 2.2 1.1 25 61.01 60.61 +0.66

A B C

D E F

J

1

J

2

J

1

J

2

J

1

J

2

J

1

J

2

J

1

J

2

J

1

J

2

J

3

J

4

A B C

D E F

J

1

J

2

J

1

J

2

J

1

J

2

J

1

J

2

J

1

J

2

J

1

J

2

J

3

J

4

Fig. 10. Six examples of ICs with nonuniform current distribution, and

different sheet resistance and number of pads.

the square pad, and the third, the number of pads. The fourth

and fth columns contain the resistance of a line segment, and

consequently the sheet resistance of our formulas. The sixth

column shows the current density, and the seventh and eighth

give the calculated and simulated maximum IR-drop for each

example, respectively. The last column contains the error as

dened before. In these examples, R

pad

= 0.

As can be seen in Table II, in all cases the maximum error

is 1%. Interestingly, by applying the result in [16] (2) to the

same examples, the error ranges from 2.8 to 10 %.

We also checked our results for a nonuniform current

distribution with two or more consuming blocks, each one

drawing a different amount of current. The six examples

simulated are illustrated in Fig. 10 and their main parameters

are described in Table III.

Here, examples AC illustrate a chip of 7.2 7.2 mm

2

with nine pads. Example D is of a chip of the same size but

with 36 pads, and examples E and F show a chip of 10.4

10.4 mm

2

with 16 pads. The dotted lines in Fig. 10 dene the

contour of the separation between the consuming blocks J

1

,

J

2

, and so on. Again, in these examples, R

pad

= 0.

Table III is divided into two parts. The second column in the

top part shows the size of the consuming block. The asterisk

(*) for examples C and E indicates that only the size of the

smaller consuming block is given, the other block is the rest

of the chip. The third and fourth columns contain the segment

resistance and sheet resistance, respectively. The fth and sixth

TABLE III

MAIN PARAMETERS OF THE SIX EXAMPLES OF THE PDN IN FIG. 10

Example

Block

size

(mm

2

)

r

segment

()

R

S

()

J

1

(mA/mm

2

)

J

2

(mA/mm

2

)

A 9.60 4.4 2.2 0 100

B 5.76 2.2 1.1 0 100

C 9.60 (*) 2.2 1.1 25 100

D 9.60 2.2 1.1 0 100

E 13.52 (*) 2.2 1.1 25 100

F

13.52,

27.04,

40.56,

27.04

2.2 1.1 100 25

Example

J

3

(mA/mm

2

)

J

4

(mA/mm

2

)

V

calc

(mV)

V

sim

(mV)

Error

(%)

A - - 195.89 194.80 +0.56

B - - 100.25 99.60 +0.65

C - - 120.74 120.3 +0.37

D - - 28.87 28.42 +1.58

E - - 146.50 145.64 +0.59

F 25 100 233.4 235.31 0.81

show the current density of blocks 1 and 2. The second and

third columns in the bottom part of Table III give the current

of blocks 3 and 4. The fourth and fth contain the calculated

and simulated maximum IR-drop in millivolts and nally, the

sixth column shows the error, which is below 1% in most

cases.

The inuence of R

pad

was investigated by repeating the

simulation of example D, but imposing R

pad

= 50 m. In this

case, the maximum IR-drop increases to 33.6 mV according

to our formulas, and to 33.08 mV in the simulations. Thus, the

error is again 1.57%. We also checked the calculated voltage

drop at each pad V

pad

. Table IV shows the results for all

36 pads. There, columns 2 and 6 contain the calculated voltage

in millivolts of each pad and, columns 3 and 7 the simulated

one. Columns 4 and 8 are the differences between both results

in microvolts.

Finally, Figs. 11 and 12 show a view of the IR-drop of

example F according to electrical simulations (Fig. 11) and

calculation (Fig. 12).

VI. DISCUSSION

A cardinal feature of our approach is that knowing the IR-

drop at a given point only requires knowing its coordinates,

chip size, and location of all pads and consuming blocks.

520 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

TABLE IV

VOLTAGE DROP ACROSS THE RESISTANCE R

pad

OF THE 36 PADS OF EXAMPLE D

No. of pad V

pad

(mV) (calc) V

pad

(mV) (sim) Diff. (V) No. of pad V

pad

(mV) (calc) V

pad

(mV) (sim) Diff. (V)

1 0.0494 0.0648 15.4 19 0.0338 0.0440 10.2

2 0.4851 0.4539 31.2 20 0.3523 0.3912 38.9

3 4.4046 4.3620 42.6 21 3.6979 3.6430 54.9

4 5.6705 5.5930 77.5 22 4.7674 4.6850 82.4

5 1.2613 1.2850 23.7 23 0.9624 0.9790 16.6

6 0.1269 0.1540 27.1 24 0.0882 0.1060 17.8

7 0.0488 0.0640 15.2 25 0.0156 0.0210 5.4

8 0.4832 0.5360 52.8 26 0.1326 0.1483 15.7

9 4.4003 4.3560 44.3 27 0.7089 0.7208 11.9

10 5.6656 5.5860 79.6 28 0.9065 0.9095 3.0

11 1.2582 1.2810 22.8 29 0.2987 0.3072 8.5

12 0.1257 0.1530 27.3 30 0.0386 0.0470 8.4

13 0.0457 0.0590 13.3 31 0.0043 0.0067 2.4

14 0.4660 0.5140 48.0 32 0.0210 0.0279 6.9

15 4.3474 4.2940 53.4 33 0.0630 0.0757 12.7

16 5.6020 5.5120 90.0 34 0.0757 0.0891 13.4

17 1.2274 1.2450 17.6 35 0.0371 0.0452 8.1

18 0.1189 0.1430 24.1 36 0.0091 0.0130 3.9

Fig. 11. IR-drop distribution on the surface of the PDN of example F

according to electrical simulations.

This is a great advantage over conventional approaches based

on the numerical solution of differential equations (that is,

nite element or nite difference methods), which require the

calculation of the IR-drop at all the points of the PDN surface

to know the IR-drop at a given point. Thus, our approach

makes it possible to obtain a faster response of IR-drop at

specic locations. In the case of searching the IR-drop at all

the points of the PDN surface, then both approaches have a

comparable execution time. Additionally, the execution time

is independent of the size of the consuming block. Let us

now sketch the computational complexity of the approach. At

this point, it is worth mentioning that no effort was made

to optimize the speed of our calculations, which are actually

written as MATLAB scripts.

Fig. 12. IR-drop distribution on the surface of the PDN of example F

according to calculation.

The algorithm can be roughly divided into three phases:

1) building plane W

the pads and blocks (or sub-blocks, when required), including

their images, on it; 2) executing the core of the algorithm,

which is in (15) and (17); and 3) coming back to plane Z,

performing the inverse transformation.

Phase 1) is extremely fast because it only requires the

conformal mapping of a small number of objects, like blocks

(or sub-blocks, when required) and pads, whose number is

limited. Its computational load depends on the product of the

number of pads and the number of blocks (or sub-blocks, when

required). In its turn, the computational load of phase 3) is

linearly proportional to the number of observation points

where the IR-drop must be known.

RIUS: IR-DROP IN ON-CHIP POWER DISTRIBUTION NETWORKS OF ICs 521

TABLE V

EXECUTION TIME IN SECONDS AS A FUNCTION OF NUMBER OF PAD

(1, 25, AND 100), NUMBER OF OBSERVATION POINTS (1, 100, AND 900),

AND NUMBER OF BLOCKS (16, 96, 480, AND 1056)

1 PAD

Points/blocks 16 96 480 1056

1 0.08 0.38 1.85 4.07

100 0.20 1.12 5.51 12.06

900 1.12 6.68 33.32 73.16

25 PADS

Points/blocks 16 96 480 1056

1 0.20 1.15 5.69 12.48

100 0.46 2.69 13.33 29.30

900 2.47 14.75 73.75 162.12

100 PADS

Points/blocks 16 96 480 1056

1 0.94 5.52 27.47 60.42

100 1.60 9.52 47.53 104.55

900 6.96 41.69 208.37 458.30

Phase 2) has the highest computational load. Equation (15)

involves: 1) building matrix M of N N elements (where

N is the number of pads), each one containing the logarithm

of the ratio of the distances between two pads, which must

be calculated previously; 2) building vector B of N elements,

each one containing the logarithm of the ratio of the GMD of

two pads to the block, which must be calculated previously;

3) inverting matrix M; and 4) multiplying the inverted matrix

by B. Actions 1) and 3) must be done only once, and actions

2) and 4) must be done only once per block (or sub-block).

Thus, computational load of phase 2) depends on the number

of pads only and is independent of the number of points where

the IR-drop must be known.

On the other hand, (17) involves the following actions:

1) calculating the ratio between the GMD of the reference

pad and the product of all the distances between the reference

pad and all the pads at the power calculated previously in

(15); 2) multiplying the distances between the observation

point and each pad at the power calculated previously in (15);

3) calculating the GMD between the observation point, for

which the IR-drop must be known, and the consuming block;

4) dividing the results of actions 2) and 3); and 5) multiplying

the results of actions 1) and 2) and taking the logarithm.

Action 1) can be precomputed and the result is reused every

time (17) is calculated, but actions 2) to 5) must be executed

for every observation point for which the IR-drop must be

known. The above are operations on scalars, and therefore

the computational load increases linearly with the number

of observation points. For each block (or sub-block, when

required), (17) is executed as many times as the observation

points we dene are executed Thus, the computational load

depends on the product of the number of blocks (or sub-

blocks) and the number of observation points.

To give an idea of the execution time, we executed the

MATLAB script on a standard PC with an Intel Q8200 CPU

with a clock frequency of 2.33 GHz and 3 GB of RAM. Only

a single core was used in the runs. It is worth mentioning

here that in the open literature devoted to PDNs and related

topics, complex ICs are divided into a few tens of functional

blocks (see [23][25]), of known location, size, and average

consumption. Therefore, it seems reasonable to analyze the

execution times for this number of blocks. However, we also

present the execution time for cases involving a much higher

number of blocks (1056). Thus, Table V shows the execution

time in seconds for several combinations of number of pads,

number of blocks, and number of observation points. In all

cases, the IC size is 10 10 mm

2

. All blocks are of size

100 100 m

2

in order to ensure accurate calculation of the

IR-drop, and because no division into sub-blocks is required.

Except for the cases of one observation point, a small

fraction of the execution time is spent in phases 1) and 2) of

the algorithm. As mentioned, no attempt was made to optimize

the execution time, which can be improved with little effort by

taking advantage of the parallelizable nature of the algorithm,

recoding it in a compiled language and adapting it for parallel

execution in multicore processors.

These execution times, as well as the results of Section IV,

showing a good agreement between the IR-drop calculated

with our approach and the results obtained by electrical

simulation, demonstrate that our method is useful in exploring

the tradeoffs to optimize the PDN in its early design phase.

Parameters like the number, size, and distribution of pads,

metal coverage, or distribution of functional blocks can be

explored in an interactive way to obtain a preliminary view of

the consequences of each decision.

In addition, it is worth pointing out that, although our

approach has been described for PDNs in ip-chip packages,

it can also be used for wire-bonded ICs by placing the pads at

the IC periphery instead of over the PDN surface. Moreover, in

spite of the fact that this paper assumes a PDN with symmetric

ground and supply grids, the described methodology to get IR-

drop can also be applied in nonsymmetrical PDNs with power

and ground grids with different properties and with a different

pad distribution.

VII. CONCLUSION

This paper analyzed the IR-drop in PDNs of array-bonded

ICs. The PDN is modeled as a conductive surface of

constant sheet resistance. Under this restriction, closed-form

expressions to nd the fraction of current supplied by

each pad, given a set of consuming blocks inside the IC,

were derived. The number, size, and location of pads and

consuming blocks and the current drawn by each block are

arbitrary. Closed-form expressions to nd the IR-drop at

any point of a nite PDN of array-bonded ICs having any

number of pads were also given. The IC power is consumed

by rectangular blocks of any size, placed in any location and

drawing an arbitrary DC current. The effect of the resistance

between the IC pads and the power supply was also included

in the model. As particular cases, the methodology proposed

for the calculation of pad current and IR-drop is also valid for

wire-bonded ICs and nonsymmetrical PDNs. The analytical

expressions were validated with electrical simulations. The

maximum error found is in the range of 1%. The execution

522 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 3, MARCH 2013

time using a single core of an Intel Q8200 CPU, running a

MATLAB script with a clock frequency of 2.33 GHz and 3 GB

of RAM, is of 0.46 s for the calculation of the IR-drop at 100

observation points of a PDN of 10 10 mm

2

, with 25 supply

pads, and 16 consuming blocks. For the same PDN, with

100 supply pads, 1056 consuming blocks, and 900 points for

which the IR-drop must be known, the execution time is 458 s.

REFERENCES

[1] M. Popovich, A. V. Mezhiba, and E. G. Friedman, Power Distribution

Networks with On-Chip Decoupling Capacitors. New York: Springer-

Verlag, 2008.

[2] A. Dubey, P/G pad placement optimization: Problem formulation for

best IR-drop, in Proc. 6th Int. Symp. Quality Electron. Design, May

2005, pp. 340345.

[3] M. Eireiner, S. Henzler, T. Missal, J. Berthold, and D. Schmitt-

Landsiedel, Power supply network design: A case study driven

approach, Adv. Radio Sci., vol. 5, pp. 279284, 2007.

[4] P. Gupta and A. B. Kahng, Efcient design and analysis of robust power

distribution meshes, in Proc. 19th Int. Conf. VLSI Design, 2006, pp.

337342.

[5] D. E. Khalil and Y. Ismail, Optimum sizing of power grids for

IR drop, in Proc. IEEE Circuits Syst. Int. Symp., Sep. 2006, pp.

481484.

[6] X. Wang, Y. Cai, X. Hong, and S. X.-D. Tan, Optimal wire sizing for

early stage power/ground grid planning, in Proc. Int. Conf. Commun.

Circuits Syst., Jun. 2006, pp. 24062410.

[7] R. Bhooshan, Novel and efcient IR-drop models for designing power

distribution network for sub-100 nm Integrated circuits, in Proc. 8th

Int. Symp. Quality Electron. Design, Mar. 2007, pp. 287292.

[8] R. Bhooshan and B. P. Rao, Optimum IR drop models for estimation

of metal resource requirements for power distribution network, in Proc.

Int. Conf. Very Large Scale Integr., Oct. 2007, pp. 292295.

[9] G. Huang, A. Naeemi, T. Zhou, D. OConnor, A. Muszynski, B. Singh,

D. Becker, J. Venuto, and J. D. Meindl, Compact physical models for

chip and package power and ground distribution networks for gigascale

integration (GSI), in Proc. Electron. Compon. Technol. Conf., May

2008, pp. 646651.

[10] J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, and Z. Pan, VLSI on-chip

power/ground network optimization considering decap leakage currents,

in Proc. Design Autom. Conf., 2005, pp. 735738.

[11] T. Sato, M. Hashimoto, and H. Onodera, Successive pad assignment

algorithm to optimize number and location of power supply pad using

incremental matrix inversion, in Proc. Design Autom. Conf., 2005, pp.

723728.

[12] Y. Zhong and M. D. F. Wong, Fast placement optimization of power

supply pads, in Proc. Asia South-Pacic Design Autom. Conf., Jan.

2007, pp. 763767.

[13] C.-H. Lu, H.-M. Chen, C.-N. J. Liu, and W.-Y. Shih, Package

routability- and IR-drop-aware nger/pad assignment in chip-package

co-design, in Proc. Design Autom. Test Eur. Conf. Exhibit., Apr. 2009,

pp. 845850.

[14] N. Srivastava, X. Qi, and K. Banerjee, Impact of on-chip inductance

on power distribution network design for nanometer scale integrated

circuits, in Proc. 6th Int. Symp. Quality Electron. Design, Mar. 2005,

pp. 346351.

[15] S. Pant, D. Blaauw, and E. Chiprout, Power grid physics and implica-

tions for CAD, IEEE Design Test Comput., vol. 24, no. 3, pp. 246254,

MayJun. 2007.

[16] K. Shakeri and J. D. Meindl, Compact physical IR-drop models for

chip/package co-design of gigascale integration (GSI), IEEE Trans.

Electron. Dev., vol. 52, no. 6, pp. 19871096, Jun. 2005.

[17] H. Chen, C.-K. Cheng, A. B. Khang, Q. Wang, and M. Mori, Optimal

planning for mesh-based power distribution, in Proc. Design Autom.

Conf., 2004, pp. 444449.

[18] Y. T. Lo, A note on the cylindrical antenna of non circular cross

section, J. Appl. Phys., vol. 24, no. 10, pp. 13381339, May 1953.

[19] E. Weber, Electromagnetic Fields Theory and Applications Vol. I Map-

ping of Fields. New York: Wiley, 1950.

[20] T. J. Higgins, Formulas for the geometric mean distances of rectangular

areas and of line segments, J. Appl. Phys., vol. 14, pp. 188195, Apr.

1943.

[21] R. Schinzinger and P. A. Laura, Conformal Mapping Methods and

Applications. New York: Dover, 2003.

[22] E. T. Whittaker and G. N. Watson, A Course of Modern Analysis, 4th

ed. Cambridge, U.K.: Cambridge Univ. Press, 1927.

[23] M. D. Pant, P. Pant, and D. S. Wills, On-chip decoupling capacitor

optimization using architectural level prediction, IEEE Trans. Very

Large Scale Integr. (VLSI) Syst., vol. 10, no. 3, pp. 319326, Jun. 2002.

[24] M. S. Gupta, J. L. Oatley, R. Joseph, G.-Y. Wei, and D. M. Brooks,

Understanding voltage variations in chip multiprocessors using a dis-

tributed power-delivery network, in Proc. Design Autom. Test Eur.

Conf., Apr. 2007, pp. 16.

[25] E. Chiprout, Fast ip-chip power grid analysis via locality and grid

shells, in Proc. Int. Conf. Comput. Aided Design, Nov. 2004, pp.

485488.

Josep Rius received the M.S. and Ph.D. degrees in

electrical engineering from the Universitat Politc-

nica de Catalunya (UPC), Barcelona, Spain.

He has been an Associate Professor with the Elec-

tronic Engineering Department, UPC, since 1991.

His current research interests include VLSI testing,

power estimation, and power/signal integrity.

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