Dynamic CMOS Circuits

Outline
In-depth discussion of CMOS logic families
Static and Dynamic Dynamic circuits Domino loigc Np Np- logic TspcTspc -logic NoraNora -logic Area, Speed, Energy or Robustness

High Performance circuit-design techniques

Nitin Chaturvedi

Dynamic logic

Dynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of N requires 2N devices

Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
requires only N + 2 transistors takes a sequence of precharge and conditional evaluation phases to realize logic functions
Nitin Chaturvedi

Dynamic logic

Dynamic Gate
CLK In1 In2 In3 CLK
Mp

CLK Out CL

Mp

on off

1 Out !((A&B)|C) C

PDN

A B

Me

CLK

Me

off on

Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

Nitin Chaturvedi

Dynamic logic

Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in high impedance state during and after evaluation (PDN off), state is stored on CL
This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails
Nitin Chaturvedi

Dynamic logic

Properties of Dynamic Gates

Number of transistors is N + 2 (versus 2N for static complementary CMOS)
Logic function is implemented by the PDN only Should be smaller in area than static complementary CMOS

Full swing outputs (VOL = GND and VOH = VDD) Nonratioed - sizing of the devices is not important for proper functioning (only for performance) Low noise margin (NML)
PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn
Nitin Chaturvedi

Dynamic logic

Properties of Dynamic Gates II

Faster switching speeds
Reduced load capacitance due to lower number of transistors per gate (Cint) so a reduced logical effort Reduced load capacitance due to smaller fan-out (Cext) No Isc, so all the current provided by PDN goes into discharging CL Ignoring the influence of precharge time on the switching speed of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL

Needs a precharge/evaluate clock

Nitin Chaturvedi

Dynamic logic

Properties of Dynamic Gates III

Power dissipation should be better than CMOS
Consumes only dynamic power no short circuit power consumption since the pull-up path is not on when evaluating Lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two) No glitches - By construction can have at most one transition per cycle

However overall power dissipation is usually higher than static CMOS due to
higher transition probabilities extra load on CLK
Nitin Chaturvedi

Dynamic logic

Dynamic Behavior
CLK Out In1 In2 In3 In4 CLK
0.5 1.5 2.5

Evaluate

In & CLK

Out

Precharge

-0.5 0 0.5 1

all data inputs set to 1

Time (ns) NML VTn tpHL 110ps tpLH 0ns tp 83ps

#Trs 6
Nitin Chaturvedi

VOH 2.5V

VOL 0V

VM VTn

NMH 2.5-VTn
Dynamic logic

Notes on Dynamic Behavior

The precharge time is determined by the time it takes to charge CL through the PMOS precharge transistor.
Often, the overall digital system can be designed in such a way that the precharge time coincides with other system functions (e.g., precharge of a FU can coincide with instruction decode).

The duration of the precharge cycle can be adjusted by changing the size of the PMOS precharge transistor. But making it too large increases the gates Cint as well as increasing the capacitive load on the clock.

Nitin Chaturvedi

Dynamic logic

Gate Parameters are Time Independent

The amount by which the output voltage drops is a strong function of the input voltage and the available evaluation time.
Noise needed to corrupt the signal has to be larger if the evaluation time is short i.e., the switching threshold is truly time independent.
2.5

CLK
Vout (VG=0.45 45) )

Voltage (V)

1.5

Vout (VG=0.5)
0.5

Vout (VG=0.55 55) )

-0.5 0 20 40 60 80 100

Time (ns)
Nitin Chaturvedi

Dynamic logic

Power Consumption of Dynamic Gate

CLK In1 In2 In3 CLK
Mp

Out CL PDN
Eliminates Static power Consumption

Me

Power only dissipated when previous Out = 0

But what about clock power impact?
Nitin Chaturvedi

Dynamic logic

Dynamic PC is Data Dependent

Dynamic 22-input NOR Gate
A 0 0 1 1 B 0 1 0 1 Out 1 0 0 0

Assume signal probabilities PA=1 = 1/2 PB=1 = 1/2 Then transition probability P01 = Pout=0 x Pout=1 = 3/4 x 1 = 3/4

Switching activity can be higher in dynamic gates! P01 = Pout= out=0 0

(static NOR gate P01 = 3/16)
Nitin Chaturvedi

Dynamic logic

Issues in Dynamic Design 1:

CLK
4

Charge Leakage

CLK

Mp

Out
1

A= A=0 0
2

CL
Me

CLK

VOut Precharge

Evaluate

Leakage sources

Minimum clock rate of a few kHz

Nitin Chaturvedi

Dynamic logic

Source of Charge Leakage

Charge stored on CL will leak away with time (input in low state during evaluation) Dominant leakage sources are reverse-biased diode (1) and the sub-threshold leakage (2) of the NMOS pulldown device. PMOS precharge device also contributes some leakage due to reverse bias diode (3) and subthreshold conduction (4) that, to some extent, offsets the leakage due to the pull down paths. Requires a minimum clock rate
Not good for low performance products such as watches (or when there are conditional clocks)
Nitin Chaturvedi

Dynamic logic

Impact of Charge Leakage

Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks
Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage.
CLK
2.5 Voltage (V)

Out
1.5 0.5 -0.5 0 20 40

Time (ms)
Nitin Chaturvedi

Dynamic logic

A Solution to Charge Leakage

Keeper compensates for the charge lost due to the pulldown leakage paths.
Keeper
CLK A B CLK Me Mp Mkp Out State Precharge Evaluate PDN Irr. OFF ON Out VDD VDD VDD 0 Mkp ON ON ON OFF

Same approach as level restorer logic CL

If PDN is on, there is a fight between the PDN and the PUN - circuit must be ratioed so that PDN wins, eventually
Nitin Chaturvedi

Dynamic logic

Issues in Dynamic Design 2:

CLK A B=0 CLK
Me Mp

Charge Sharing

Out CL Ca Cb

Charge stored originally on CL is redistributed (shared) over CL and CA leading to static power consumption by downstream gates and possible circuit malfunction.

When Vout = - VDD (Ca / (Ca + CL )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction.
Nitin Chaturvedi

Dynamic logic

Charge Sharing Example

What is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V.)
CLK A !A y=ABC

Load inverter

a
Ca=15 15fF fF B

Cy=50 50fF fF

!B !C

b
B C !B

Cb=15 15fF fF

Cc=15 15fF fF

Cd=10fF Vout = - VDD [(Ca + Cc)/((Ca + Cc) + Cy)] = - 2.5V*( V*(30 30/( /(30 30+ +50 50)) )) = -0.94 94V V

CLK

Nitin Chaturvedi

Dynamic logic

Notes on Charge Sharing Example

Output stays high for 4 out of 8 cases (!A B C, !A !B !C, A !B C, and A B !C) Worst case is obtained by exposing the maximum amount of internal capacitance to the output node during evaluation.
This happens when !A B C or A !B C

V = -0.94 V so the output drops to 2.5 - 0.94 = 1.56 V which is below the switching threshold of the Load inverter.
Nitin Chaturvedi

Dynamic logic

Solution to Charge Redistribution

CLK A B CLK
Me Mp Mkp

CLK Out

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
Nitin Chaturvedi

Dynamic logic

Issues in Dynamic Design 3:

Backgate Coupling

Susceptible to crosstalk due to 1) high impedance of the output node and 2) capacitive coupling
CLK
Mp M1 M2 Me

Out1 Out 1 =1 C L1

M6 M5

Out2 Out 2 =0 A= A=0 0 B=0

CLK
M4 M3

C L2 In

Static NAND

Dynamic NAND

Out2 capacitively couples with Out Out2 Out1 1 through the gate-source and gate-drain capacitances of M4
Nitin Chaturvedi

Dynamic logic

Backgate Coupling Effect

Capacitive coupling means Out Out1 1 drops significantly so Out2 Out 2 does not go all the way to ground
3

Out1
1

CLK

In
0 2

Out2

-1 4 6

Time (ns)
Nitin Chaturvedi

Dynamic logic

Notes on Backgate Coupling Effect

The high impedance of the output node makes the circuit very sensitive to crosstalk effects.
A wire routed over or next to a dynamic node may couple capacitively and destroy the state of the floating node.

Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage is reduced. Out1 overshoots VDD (2.5V) due to clock feedthrough
Nitin Chaturvedi

Dynamic logic

Issues in Dynamic Design 4:

Clock Feedthrough

A special case of capacitive coupling between the clock input of the precharge transistor and the dynamic output node
CLK
A B

Mp

Out CL

CLK

Me

Coupling between Out and CLK input of the precharge device due to the gate- drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

Nitin Chaturvedi

Dynamic logic

Clock Feedthrough Example

CLK

Clock feedthrough Out

2.5

In1 In2 In3 In4

CLK
-0.5 0 0.5 1 1.5

0.5

In & CLK Out

Clock feedthrough

Time (ns)

Signal levels can rise enough above VDD that the normally reversereversebiased junction diodes become forwardforward-biased causing electrons to be injected into the substrate.
Nitin Chaturvedi

Dynamic logic

Cascading Dynamic Gates

V
CLK
Mp CLK Mp

CLK

Out1

Out2 Out 2

In
CLK
Me CLK Me

In
Out1 Out 1

VTn V t

Out2 Out 2

Only a single 0 1 transition allowed at the inputs during the evaluation period!
Nitin Chaturvedi

Dynamic logic

Domino Logic
CLK In1 In2 In3 CLK
Mp
11 10

CLK
Out1 Out 1
00 01

Mp Mkp Out2 Out 2

PDN

In2 In3

PDN

Me

CLK

Me

Assume all inputs to the Domino gate are initially zero

Nitin Chaturvedi

Dynamic logic

Why Domino?
CLK

In1 Ini Inj

CLK

PDN

Ini Inj

PDN

Ini Inj

PDN

Ini Inj

PDN

Like falling dominos!

Dynamic logic

Nitin Chaturvedi

Notes on Dominic Logic

Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 to 1 Additional advantage is that the fan-out of the gate is driven by a static inverter with a low-impedance output that increases the noise immunity. The buffer also reduces the capacitance of the dynamic output node by separating internal and load capacitances. Finally, the inverter can be used to drive a bleeder to combat leakage and charge redistribution.
Nitin Chaturvedi

Dynamic logic

Domino Manchester Carry Chain

CLK

P0

P1 3

P2 2

P3 1

3 Ci, i,4 4 1 2

Ci,0
CLK

4 5 G0 6

4 G1 5

3 G2 4

2 G3 3

!(G0 + P0 Ci,0 i,0)

!(G1 + P1G0 + P1P0 Ci,0)

Automatically forms all the intermediate carries

Nitin Chaturvedi

Dynamic logic

Domino Comparator
CLK A3 A2 A1 A0

Out

B3

B2

B1

B0

Dont need isolation NMOS in the pullpull-down, since the PDN is forced off during precharge.
Nitin Chaturvedi

Dynamic logic

Properties of Domino Logic

Only non-inverting logic can be implemented, fixes include
can reorganize the logic using Boolean transformations use differential logic (dual rail) use np-CMOS (zipper)

Very high speed

tpHL = 0, only Low-High transitions allow static inverter can be optimized to match fan-out (separation of fan-in and fan-out capacitances) Input capacitances reduced - smaller logical effort
Nitin Chaturvedi

Dynamic logic

Differential (Dual Rail) Domino

Solve problem of non-inverting logic
off
CLK Out = AB 1 A !A B CLK
Me Mp Mkp

on
Mkp Mp

CLK

1
!B

0 !Out = !(AB)

AND/NAND Due to its highhigh-performance, differential domino is very popular and is used in several commercial microprocessors!
Nitin Chaturvedi

Dynamic logic

Notes on Differential Domino

The inputs and their complements come from other differential DR gates and thus all inputs are low during precharge and make a conditional transition from 0 to 1. Expensive - but can implement any arbitrary function. Use significant power since they have a guaranteed transition every single clock cycle (regardless of signal statistics, since either Out or !Out will transit from 0 to 1). Nonratioed (even though it has a cross-coupled PMOS pair)

Nitin Chaturvedi

Dynamic logic

npnp-CMOS (Zipper)
CLK In1 In2 In3 CLK
Mp 11 10

!CLK
Out1 Out 1

Me

PDN

In4 In5 !CLK

PUN
00 01

Me

Mp

Out2 Out2 (to PDN)

In4 and In5 must be from PDN

Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN
Nitin Chaturvedi

Dynamic logic

NORA (No Race)

CLK In1 In2 In3 CLK
Mp 11 10

!CLK
Out1

Me

PDN

In4 In5 !CLK to other PDNs

PUN
00 01

Me

Mp

Out2 Out2 (to PDN)

to other PUNs

Very sensitive to Noise!

Nitin Chaturvedi

Dynamic logic

Note on npnp-CMOS and NORA

DEC alpha uses np-CMOS logic (Dobberpuhl) Have to size the PUNs to equalize the delay to that of the PDNs Really dense layouts and very high speed (20% faster than domino with the correct sizing) Reduced noise margin (as with any dynamic gate)
More sensitive to noise

Increase complexity
Have two clock signals to generate and route - CLK and !CLK
Nitin Chaturvedi

Dynamic logic

npnp-CMOS Adder Circuit

!CLK
1x 0x

CLK !C1 !A1 !B1

1x

Sum1

!A1

!B1

!B1 !A1 !A1

0 xC
2

!B1

!C1 CLK !CLK

!CLK

CLK
0x

1 x !C1

A0 B0 CLK B0

A0

B0
1x

C0

A0 C0
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B0 A0 C0

!CLK
Dynamic logic

0x

!Sum0

ADVANTAGE1 ADVANTAGE 1 --MULTIPLE --MULTIPLE OUTPUT DOMINO

Example
Multiple precharge trans.

ADVANTAGE2 ADVANTAGE 2 COMPOUND DOMINO

How to Choose a Logic Style

Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing
4-input NAND

Style Comp Static CPL* domino DCVSL*

* Dual Rail

# Trans 8 12 + 2 6+2 10

Ease 1 2 4 3

Ratioed? Delay Power no no no yes 3 4 2 1 1 3 2 + clk 4

Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling.
Nitin Chaturvedi

Dynamic logic