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Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com Volume 2, Issue 5, May 2013 ISSN 2319 - 4847
Associate Professor, Department of Electronics Engineering, Pillai Institute of Information Technology, New Panvel, Mumbai University Lecturer, Department of Electronics Engineering, Pillai Institute of Information Technology, New Panvel, Mumbai University
ABSTRACT
Moores law states that the number of transistors in integrated circuits doubles every 18 months. Increasing complexity of digital system over the past decade has made it essential to increase the awareness of need of fault testing and diagnosis. With the increase in complexity of the digital system, a test simulation along with diagnosis has become an important issue in VLSI testing. In this paper, a signature analysis method is presented for testing of CMOS integrated circuits.
1. INTRODUCTION
There has been a continuous pressure on VLSI chip manufacturing industry to increase the manufacturing yield. Integrated circuit manufacturers are constantly trying to decrease the number of faulty parts they produce. The reliability of System-on-Chips must be ensured to a certain extent since a single fault is likely to make the whole chip useless. Therefore, fault diagnosis and fault repairing techniques are gaining importance these days. A manufacturer may be able to improve the circuit design or the manufacturing process by analyzing the parts that fail production tests and determining the cause of failure for each part. Detection of fault and the type of fault present in a circuit is known as fault diagnosis. With the growth of technology and advent of reconfigurable circuits like FPGAs, PLAs, PLDs etc. testing only for faulty chip is not adequate [1]. Fault location may be required to identify and then replace or discard the faulty sub-circuit. It can also be used to analyze the defect causing the faulty behavior. Fault diagnosis is executed upon manufactured chips, which are found to be faulty in order to identify the position and types of the faults present in them [2].
2.
HISTORICAL BACKGROUND
Current measurement based testing of electronics components has always been an integral part of the testing since the birth of semiconductor industry. It is used to detect gross shorts and is generally referred to as static IDD test. The present form of quiescent current (IDDQ) measurement based testing for CMOS VLSI, known as IDDQ testing, was first publicly proposed in 1981 [1] and then formulated in [2] and [4] for the detection of bridging faults. Around the same time, researchers at IBM also proposed the monitoring of switching current to detect transient failures (noise related failures) in memory devices [5].
CORRECT RESPONSE
COMPARATOR
TEST RESULT
Figure 1 Test set up for testing a circuit If the response does not match, the fault is considered detected by the given set of test patterns. Figure 1 illustrates the basic principle of digital testing. Input patterns called test vectors are applied to the inputs of the circuit. The response
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4. IDDQ TESTING
IDDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state powersupply current. IDDQ stands for quiescent power-supply current. Today, the majority of ICs are manufactured using complementary metaloxidesemiconductor (CMOS) technology. In steady state, when all switching transients are settled-down, a CMOS circuit dissipates almost zero static current. The leakage current in a defect-free CMOS circuit is negligible (on the order of few nano amperes). However, in case of a defect such as gate-oxide short or short between two metal lines, a conduction path from power-supply (VDD) to ground (GND) is formed and subsequently the circuit dissipates significantly high current. This faulty current is a few orders of magnitude higher than the fault-free leakage current. Thus, by monitoring the power-supply current, one may distinguish between faulty and fault-free circuit [3]. The steady state or quiescent current (IDDQ) testing of CMOS integrated circuits is known to be very efficient for improving test quality [8]. The test methodology based on the observation of the quiescent current on power supply lines allows a good coverage of physical defects such as gate-oxide shorts, floating gates and bridging faults. These defects are neither well modelled by the classical fault models, nor detectable by conventional logic tests. In addition, IDDQ testing can be used as a reliability predictor due to its ability to detect defects that do not yet involve faulty circuit behaviour, but could be transformed into functional failures at an early stage of circuit life. Thus, IDDQ testing became a powerful complement to the conventional logic testing. Under the fault conditions, the normal values of IDDQ may be increased, decreased or generally distorted. Thus, fault detection can be accomplished by monitoring the Iddq current fluctuations using a current sensing circuit. In report, a simple built-in current sensor (BICS) is presented, which provides a digital output for supply current monitoring and testing in circuits. BICS is inserted in series with the power supply or the ground of the Circuit under test (CUT) to detect abnormal IDDQ current in the integrated circuit [6] as shown in Figure 2.
Figure 2 Block diagram of IDDQ testing. Irrespective of all the advantages of IDDQ testing, there are some problems in using this method. Since the normal IDDQ is very low, measurements must be precise. Also, setting IDDQ threshold on bad devices can be hard. In case of open faults, the IDDQ becomes very small making it difficult to measure and compare with the threshold. To overcome all the problems occurring in the IDDQ testing a signature analysis method is used.
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Figure 3 Circuit to obtain the signature of integrated circuits Figure 3 shows the circuit diagram used to test any NMOS or PMOS combinational circuit. Initially no input is applied to the combinational circuit to be tested. NMOS is initially off & capacitor has no charge stored in it. Now input is given to the NMOS so it turns ON. Then the current direction is VDD-NMOS-C-VDD. Now capacitor is charged to value VDD. Then input to NMOS is made low & it turns OFF. Now capacitor is charged but it does not have any path to get discharged. When input is given to the combinational circuit, it turns ON & capacitor gets a path to discharge. The capacitor then discharges through the circuit. The time required for the capacitor depends on various parameters of the NMOS & PMOS in the circuit. This time period is then compared with the time period obtained in the simulation results. Using the circuit shown in fig.(4), we can find the signature of an inverter IC which is then compared with the simulated results of the fault free IC.
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Figure 6 Signature of the faulty inverter IC (Length of channel is less than the normal)
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Figure 7 Signature of the faulty inverter IC (Length of channel is larger than the normal)
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Figure 10 Signature of the faulty inverter IC (Stuck-at-0 fault at the gate of PMOS)
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Figure 11 Signature of the faulty inverter IC (Stuck-at-0 fault at the gate of NMOS)
Figure 12 Signature of the faulty inverter IC (Stuck-at-1 fault at the gate of PMOS)
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Figure 13 Signature of the faulty inverter IC (Stuck-at-1 fault at the gate of NMOS)
Figure 14 Circuit for comparing the signature of the fault free IC and IC under test Figure 5 shows the signature of the fault free inverter IC. In this signature, it can be seen that when the input is given to the inverter, the capacitor C starts discharging through it. In this figure, for fault free circuit voltage across capacitor and output of inverter is shown. Figure 6 to 13 show the responses of the inverter IC with different faults. These faults occur when the length or width of the channel of the transistors is varied or in the presence of stuck-at faults at various
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5. CONCLUSION
A new method for signature analysis has been described. This method provides a robust and flexible way to implement signature analysis. The most powerful aspect of this method is the ability to implement it for single failures, making it useful for field returns, qualification failures. Another important benefit of this method is the ability to use a low degree of belief with any number of signatures that are not well known or rely entirely on expert opinion. This method obviously requires a standard set of failure mechanisms as well as a standard set of terms and definitions for failure analysis. This SA method has the ability to be incorporated into an automated IC diagnosis process that uses defect models and classes for site localization in addition to failure mechanism determination. Improved models and diagnosis procedures will help reduce the amount of testing and physical failure analysis necessary to determine a signature for the failure mechanism and its location.
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