Switching Theory and Logic Design (April/May-2012, Set-3) JNTU-Anantapur

Code No: 9A04401/R09 II B.Tech. II Semester, Regular & Supplementary Examinations

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April/May - 2012 SWITCHING THEORY & LOGIC DESIGN

( Common to EEE, EIE, E.Con.E, ECE & ECC )

Set-3
Solutions
Max. Marks: 70

Time: 3 Hours Answer any FIVE Questions All Questions carry equal marks --1. (a) (b) List the binary, octal and hexa numbers for decimal 16 to 31. (Unit-I, Topic No. 1.1) Perform the following operations using 2s complement method: (i) 2. (a) (b) (c) 3. (a) (b) 48 23 (ii) 23 48 (Unit-I, Topic No. 1.2) State and prove Boolean laws related to OR, AND, NOT gates. (Unit-II, Topic No. 2.1) Give Boolean expression AB' + A'B = C. Show that AC' + A'C = B. (Unit-II, Topic No. 2.2) Prove that OR-AND network is equivalent to NOR-NOR network. (Unit-II, Topic No. 2.3)

Simplify the following Boolean function for minimal SOP form using K-map F(W, X, Y, Z) = (0, 1, 2, 3, 4, 6, 8, 9, 10, 11). (Unit-III, Topic No. 3.1) Simplify the following Boolean functions using K-map, (i) F(A, B, C) = A'B + B'C + A'B'C' (ii) F(A, B, C) = A'B' + AC' + B'C + A'B'C'. (Unit-III, Topic No. 3.1)

4. 5. 6.

(a) (b) (a) (b) (a) (b)

Implement full adder using 4*1 multiplexer. (Unit-IV, Topic No. 4.2) Design 4*16 decoder using two 3*8 decoders with block diagram. (Unit-IV, Topic No. 4.2) Explain the general combinational PLD configuration with suitable block diagram. (Unit-V, Topic No. 5.1) Give the logic implementation of a 32 4-bit and 8 4-bit ROM using suitable decoder. (Unit-V, Topic No. 5.1) Draw the circuit diagram of 4-bit ring counter using D flip flops and explain its operation with the help of bit pattern. (Unit-VI, Topic No. 6.3) Distinguish between transition table and excitation table. (Unit-VI, Topic No. 6.1)

7.

A clocked sequential circuit with simple input x and single output Z produce an output Z = 1 whenever the input x completes the sequence 1 0 1 1 and overlapping is allowed. (a) (b) Obtain its state-diagram. Obtain its minimal state-table and design the circuit with D-Flip-Flops. (Unit-VII, Topic No. 7.3) For the given control state diagram obtain its equivalent ASM chart. (Unit-VIII, Topic No. 8.2) Design control logic circuit using multiplexers for the given state diagram. (Unit-VIII, Topic No. 8.2)
X A3A4 S' T0 S T1 A3 A3A4 T2

8.

(a) (b)

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SOLUTIONS TO APRIL/MAY-2012, SET-3, QP

Q1. (a) List the binary, octal and hexa numbers for decimal 16 to 31 April/May-12, Set-3, Q1(a) Answer : The 2s complement of 010111 is obtained, as 2s complement of 010111 = 1s complement of 010111 + 1 = 101000 + 1 = 101001 Then, (110000)2 (010111)2 = (110000)2 + (101001)2

The list of binary, octal and hexadecimal numbers for decimal numbers 16 to 31 are shown in table, Decimal 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (b) Binary (base - 2) 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Octal 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 Hexa 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F (ii) (base - 8) (base - 16)

110000 101001 1 011001 Discard the carry

48 23 = (110000) 2 (010111) 2 = (011001) 2 = (25)10

(23 48) in 2s Complement Form Binary equivalent of 23 = (010111)2 Binary equivalent of 48 = (110000)2 23 48 = (010111)2 (110000)2 = (010111)2 + (2s complement of (110000)2) 2s complement of (110000)2 = 1s complement of (110000)2 + 1 = (001111)2 + 1

001111 1 010000
Now, (010111)2 (110000)2 = (010111)2 + (010000)2

Perform the following operations using 2s complement method: (i) 48 23 April/May-12, Set-3, Q1(b) (ii) 23 48.

010111 010000 100111

= 100111 Since, there is no carry, the result is in 2s complement form. To obtain the actual result, again performing 2s complement on the result, we get, [1s complement of (100111) + 1] = [011000 + 1] = (011001)2 = 25 The actual result is,
23 48 = (010111) 2 (110000) 2 = (011001) 2 = (25)10

Answer : (i)

(48 23) in 2s Complement Form Binary equivalent of 48 = (110000)2 Binary equivalent of 23 = (010111)2 In decimal form, 48 23 = 25

The subtraction operation of 48 23 using 2s complement form is the addition of binary equivalent of 48 to the 2s complement of binary equivalent of 23. i.e., 48 23 = (110000)2 (010111)2 = (110000)2 + (2s complement of (010111)2)

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Switching Theory and Logic Design (April/May-2012, Set-3) JNTU-Anantapur

Q2. State and prove Boolean laws related to OR, AND, NOT gates. Answer : April/May-12, Set-3, Q2(a) For answer refer Unit-II, Q3. (b) Give Boolean expression AB' + A'B = C. Show that AC' + A'C = B. Answer : April/May-12, Set-3, Q2(b) For answer refer Unit-II, Q12. (c) Prove that OR-AND network is equivalent to NOR-NOR network. Answer : April/May-12, Set-3, Q2(c) For answer refer Unit-II, Q22. Simplify the following Boolean function for minimal SOP form using K-map F(W, X, Y, Z) = (0, 1, 2, 3, 4, 6, 8, 9, 10, 11). Answer : April/May-12, Set-3, Q3(a) The given Boolean function is, F(W, X, Y, Z)= (0, 1, 2, 3, 4, 6, 8, 9, 10, 11) The above Boolean expression can be simplified by loading it into the four variable K-map as shown in figure below, Q3. (a) (a)

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By converting the given expression into a standard sum of products form, we get, F(A, B, C)= A'B(C + C')+ (A + A')B'C + A'B'C' = A'BC + A'BC' + AB'C + A'B'C + A'B'C' = 011 + 010 + 101 + 001 + 000 =3+2+5+1+0 F(A, B, C) = (0, 1, 2, 3, 5) Loading the above expression into a 3-variable K-map as shown in figure (1),
A 0 1
BC

BC 00
0

01
1

11
3

10
2

1
4

1
5

1
7

1
6

Figure (1): 3-variable K-map Therefore, the required simplified expression is,

F ( A, B, C ) = A + B C
(ii) F(A, B, C) = A'B' + AC' + B'C + A'BC' The given Boolean expression is, F(A, B, C)= A'B' + AC' + B'C + A'BC' By converting the above expression into a standard SOP form, we get, F(A, B, C) = A'B'(C + C') + A(B + B')C' + (A + A')B'C + A'BC' = A'B'C + A'B'C' + ABC' + AB'C' + AB'C + A'B'C + A'BC' = 001 + 000 + 110 + 100 + 101 + 001 + 010 =1+0+6+4+5+1+2 F(A, B, C) = (0, 1, 2, 4, 5, 6) Loading the above expression into a 3-variable K-map as shown in figure (2),

WX

YZ

00
0

01
1

11
3

10
2

00 01 11

1
4

1
5

1
7

1
6

1
12 13 15

1
14

WZ

11

10

10

Figure: 4-variable K-map Therefore, the simplified minimal SOP expression is,

F = X +W Z
Simplify the following Boolean functions using K-map. (i) F(A, B, C) = A'B + B'C + A'B'C' (ii) F(A, B, C) = A'B' + AC' + B'C + A'B'C' Answer : April/May-12, Set-3, Q3(b) (i) F(A, B, C) = A'B + B'C + A'B'C' The given Boolean expression is, F(A, B, C) = A'B + B'C + A'B'C' (b)

A 0 1

BC 00
0

01
1

11
3

10
2

1
4

1
5 7

1
6

Figure (2): 3-variable K-map Therefore, the required simplified expression is,

F ( A, B, C ) = B + C

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Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 April/May-12, Set-3, Q4(a)

Q4. (a) Implement full adder using 4*1 multiplexer. Answer : Full Adder Operation using 4 to 1 Multiplexer The block schematic representation of full adder is as shown in figure (1).
A B Cin Full Adder Cout S

Figure (1) The truth table of full adder is as shown in table (1),
Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 Output Cout 0 0 0 1 0 1 1 1

Table (1): Truth Table of Full Adder From the above table, the boolean functions of sum (S) and output carry (Cout) can be obtained as, S = {1, 2, 4, 7} Cout = {3, 5, 6, 7} In order to implement a full adder, a 8 1 multiplexer is required. To implement the same full adder using 4 1 multiplexers, one input is considered as common to both 4 1 MUXs. By considering A as input, B and C as selection lines, the implementation table of S and Cout is given as, For S = {1, 2, 4, 7}

I0 A' 0 A 4 MUX 1 Inputs

For Cout = {3, 5, 6, 7}

I1 1 5 A'

I2 2 6 A'

I3 3 7 A

I4 A' 0 A 4 MUX 2 Inputs

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I6 2 6 A

I7 3 7 1
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Switching Theory and Logic Design (April/May-2012, Set-3) JNTU-Anantapur

Then, the circuit arrangement of full adder using 4 1 mux is as shown in figure (2),
A I0 I1 I2 I3 41 MUX 1 S

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I4 I5 I6 41 MUX 2 Cout

I7

Cin

Figure (2): Full Adder using 4 1 MUX (b) Answer : Realization of 4 16 Decoder with Two 3 8 Decoders A 4 16 decoder can be constructed using two 3 8 decoders with enable input. This enable input acts as 4th input to a 4 16 decoder which is directly given as enable signal to the decoder that generates higher order bits and is inverted and given as an input to the other decoder.
D0 D1 D2 Lower D3 order D4 bits D5 D6 D7 16 output lines D8 D9 D10 Higher D11 D12 Order D13 bits D14 D15

Design 4*16 decoder using two 3*8 decoders with block diagram. April/May-12, Set-3, Q4(b)

I1 I2 Four inputs lines I3

38 Decoder 0 E0 Enable

I0 38 Decoder I

E1 Enable

Figure (2): Implementation of a 4 16 Decoder using Two 3 8 Decoders

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I0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inputs I1 I2 I3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 D1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

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Outputs D5 D6 D7 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 D8 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 D9 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 D10 D11 D12 D13 D14 D15 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Table: Truth Table of 4 16 Decoder When the input I0 = 0, first 3 8 decoder is enabled that generates 8 outputs D0-D7 and the other decoder is disabled. When the input I0 = 1 first 3 8 decoder is disabled whose outputs are all zero and the other decoder is enabled that generates the 8 outputs. D8-D15. Q5. (a) Explain the general combinational PLD configuration with suitable block diagram. Answer : April/May-12, Set-3, Q5(a) General PLD PLDs are logic devices, which can be programmed by the user. Some PLDS are reprogrammable. The general programmable devices depend on the disjunctive normal form i.e., sum of products form. The general structure of the combinational PLD consists of AND and OR gates to represent any individual function. The combinational PLD structure for a device with 2 inputs and 2 outputs is shown in figure.
A B

f1

f2

Figure (i): General Combinational PLD

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In the above figure, left part of the circuit containing only AND gates called as the AND matrix and a matrix of OR gates only is called as OR matrix. Depending on the architecture PLDs are classified into three basic structures. they are, (i) Programmable Read-only Memory (PROM) (ii) (iii) Programmable Logic Array (PLA) Programmable Array Logic (PAL).
I1 (A1)

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The truth table for 2-to-4 decoder with an output polarity control is same as that in table (1). Implementation of this decoder using discrete logic gates is as shown in figure (2),
I0 (A0) Q0 (X0)

For remaining answer refer Unit-V, Q3, Topics: (i), (ii), and (iii). (b) Give the logic implementation of a 32 4-bit and 8 4-bit ROM using suitable decoder. Answer : April/May-12, Set-3, Q5(b) The 32 4-bit ROM and 8 4-bit ROM can be implemented using 5 32 decoder and 2 4 decoder respectively. Logic Implementation of a 32 4-bit ROM using 5 32 Decoder For answer refer Unit-V, Q2. Logic Implementation of an 8 4-bit ROM using 2 to 4 Decoder An 8 4 ROM or 23 4 ROM consists of 3 inputs and 4 outputs. The basic structure of 8 4 ROM is as shown in figure (1).
X0 A0 A ddre ss in puts X1 A 1 2 3 4 R O M A2 X2 X3 D a ta outputs

Q1 (X1)

Q2 (X2)

Q3 (X3) POL (A2)

Figure (2): 2-to-4 Decoder with Output-Polarity Control Hence, a 2-to-4 decoder can be implemented in following two ways, (i) (ii) Using discrete logic gates and Using 8 4 ROM.

The connections required to implement the 2-to-4 decoder using 8 4 ROM is as shown in figure (3).
X0 I0 I1 POL A0 X1 A1 8 4 ROM A2 X2 X3 Y1 Y2 Y3 Y0

Figure (1): Basic Structure of 8 4 ROM The truth table of 23 4 ROM is as shown in table (1). A2 0 0 0 0 1 1 1 1 Inputs A1 A0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 X3 1 1 1 0 0 0 0 1 Table (1) X2 1 1 0 1 0 0 1 0 Outputs X1 1 0 1 1 0 1 0 0 X0 0 1 1 1 1 0 0 0

Figure (3): Connections required to Implement the 2-to-4 Decoder Using 8 4 ROM By altering the order of either rows or columns of the truth table (provided in table (1)), different physical ROMs are obtained. These new ROMs can be used to perform the similar logic function. This can be accomplished by assigning the signals of decoder to the inputs and outputs of different ROM. Alternately, it can also be achieved by changing the names of each address inputs and data outputs of ROM. For instance, consider the swapping of the bits in the columns X0 and X3 in table (1). This results in a different physical ROM. The new ROM obtained still can be used in implementing 2-to-4 decoder by just swapping the outputs X0 and X3 labels in figure (3).

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Also, the ROM can be still used to implement 2-to-4 decoder if the data rows are shuffled completely as shown in table (2). The operation of this 3-input, 4-output combinational logic function (ROM) can be easily understood by truth table as shown in below table. Inputs X A2 0 0 0 0 1 1 1 1 Y A1 0 0 1 1 0 0 1 1 Z A0 0 1 0 1 0 1 0 1 A X3 1 0 1 0 1 0 0 1 Table (2) It just requires the rearrangement of the address inputs such as, (i) (i) Q6. (a) A0 = POL A1 = I0 Draw the circuit diagram of 4-bit ring counter using D-flip-flops and explain its operation with the help of bit pattern. April/May-12, Set-3, Q6(a) Distinguish between transition table and excitation table. April/May-12, Set-3, Q6(b) Transition Table 1. 2. Transition table is a tabular representation of the transition and ouptut equations. It consists of three sections, (i) Present-state section (ii) Next-state section (iii) Output section. 3. 4. 5. Present state of transition table consists of all the 3. possible combinations of values for the state variables. Transition expressions are used to form the next-state section of the transition table. The entries in this section are p-tuples for each combination of present state and external input. 4. 5. 1. 2. Excitation Table Excitation table is a tabular representation of the excitation and output equations. It consists of three sections, (i) Present state section (ii) Excitation section (iii) Output section. Present state of excitation table provides all the possible combinations for the state variables. Excitation expressions are used to form the excitation section of the excitation table. The entries in this section are r-tuples for the respective combination evaluate the r-excitation equations. Outputs B X2 1 0 1 0 0 1 1 0 C X1 1 0 0 1 1 0 1 0 D X0 0 1 1 0 1 0 1 0

(iii) A2 = I1.

Answer : For answer refer Unit-VI, Q18. (b) Answer : Difference between transition table and excitation table.

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6. Example for transition table.
Present State Q1 Q2 00 00 01 01 10 10 11 11 Next state X 0 1 0 1 0 1 0 1 + + Q1 Q2 10 01 11 11 10 00 00 00 Output Z 0 1 0 0 1 0 1 0

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6.

Example for excitation table.

Present State Q1 Q2 00 00 01 01 10 10 11 11 Next state X 0 1 0 1 0 1 0 1 + + Q1 Q2 10 01 11 11 10 00 00 00 Flip flop Inputs D1 D2 10 01 11 11 10 00 00 00 Output Z 0 1 0 0 1 0 1 0

7. Q7.

The length of the present state section determines 7. the length of the transition table.

The length of the present state section determines the length of the excitation table.

A clocked sequential circuit with simple input x and single output Z produce an output Z = 1 whenever the input x completes the sequence 1 0 1 1 and overlapping is allowed. (a) (b) Obtain its state-diagram. Obtain its minimal state-table and design the circuit with D-Flip-Flops. April/May-12, Set-3, Q7

Answer :

The given clocked sequential circuit with input X and output Z produces output, Z = 1 when X completes the sequence 1011. (a) Let the four states of the sequential circuit be A, B, C and D. Then the state diagram of the sequence 1011 by considering the machine in state A initially is shown in figure (1).
0/0 A 1/0 0/0 1/1 1/0 D 0/0 0/0

1/0

Figure (1): State Diagram At A When the machine is in state A if the input is 0, the detection will not start and the machine remains in the same state giving an output 0. On the other hand, when the input is 1, it shifts to the state B by producing output as 0. At B When the input is 0, the sequence will be 10, which is a part of the required sequence. Hence, it shifts to next state by producing output as 0. On the other hand, when the input is 1, the sequence will be 11 which is not a part of the required sequence. Hence, it remains in the same state B as the overlapping is allowed (to use last 1-bit), by producing an output as 0.

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At C

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When the input is 0, the sequence will be 100 which is not a part of the required sequence. Hence, it shifts to state A by producing 0 output to start a new detection. On the other hand, when the input is 1, the sequence will be 101 which is a part of the required sequence. Hence, it shifts to the state D, by producing output 0. At D When the input is 0, the sequence will be 1010 which is not a required sequence. Hence, it shifts to state C, by producing 0 output as overlapping is allowed. At state C, it uses the bits 10. On the other hand, when the input is 1, the sequence is 1011, which is a valid sequence. As the sequence is getting completed here, it produces the output as 1 and shifts to state B to make use of last bit i.e., 1. The minimal state table of the state diagram is shown in table (1). Present State Next State, Z X=0 X=1 A A, 0 B, 0 B C,0 B, 0 C A, 0 D, 0 D C, 0 B, 1 Table (1): State Table Let, A = 00, B = 01, C = 10, D = 11 Then the transition table is obtained as shown in table (2). Present State Next State (Y1, Y2) Output (Z) y1 y2 X=0 X=1 X=0 X=1 A00 00 01 0 0 B01 10 01 0 0 C10 00 11 0 0 D11 10 01 0 1 Table (2): Transition Table The truth table of a D-flipflop is shown in table (3). Qn Qn+1 D 0 0 0 0 1 1 1 0 0 1 1 1 Table (3) The excitation table with the memory elements as D-flip flops is shown in table (4). Present State Input Next State Flip-flop Inputs Output Y1 Y2 X Y1 Y2 D1 D2 Z 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 Table (4)

(b)

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Simplification of D flip-flop inputs and output using K-map is shown in figure (2). K-map for D1

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y1 0 1

y2x 00 0 4

01 1 1 5

11 3 7

10 1 1 2 6

D1 = y1 y 2 x + y 2 x

K-map for D2

y2x 01 y1 00 0 1 0 1 1 4 1 5

11 3 1 1 7

10 2 6

D2 = x
K-map for Z

y1

y2x 00 0 4

01 1

0 1

11 3

10 2 6

5 1 7 Z = y1y2x

Figure (2) The implementation of the above expressions using D-flip-flops is shown in figure (2).
y1 y3 x D1 1 CLK
y1

y1

Z x D2 2 CLK
y2

y2

CLK

Figure (3): Circuit using D-Flip-flop

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Q8. (a) (b)

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 For the given control state diagram obtain its equivalent ASM chart. Design control logic circuit using multiplexers for the given state diagram.
X A3A4 S' T0 S T1 A3 A3A4 T2

Answer : The given state diagram of a control unit is shown in figure (1).
X A3A4 S' T0 S T1 A3 A3A4 T2

April/May-12, Set-3, Q8

Figure (1): State Diagram (a) Equivalent ASM Chart There are three states in the above state diagram. They are T0, T1 and T2. Let these states be represented in binary code as follows, T0 = 00 T1 = 01 T2 = 10 The equivalent ASM chart for the given state diagram is obtained as shown in figure (2).
T0 00

S T1 1

0 01

A3 1 A4 T2 1

0 10

X 1

Figure (2): ASM Chart

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(b) Design of Control Logic Circuit using Multiplexers The state table of the given state diagram is shown in table (1).
Present State S.No Binary Assignment 0 1 00 01 Name T0 T1 Binary Assignment 00 01 01 01 10 00 Name T0 T1 T1 T1 T2 T0 Next State Condition for Transition S(0) S(1) A3A4(10) A3(0) A3A4(11) X(1)

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10

T2

Table (1): State Table To design the control logic circuit for the given state diagram, two flip-flops say A and B and two 4 1 multiplexers say 1 and 2 are required. The bit positions of the next state are considered as the inputs for multiplexers which generates the flip-flop inputs as shown in table (2).
MUX 1 (Next state 1st bits) MUX 2 (Next state 2nd bits)

0 0 0 0

0 1 (S) Condition of transition S

0 0

1 (A3 A4) 1 (A3)

1 (A3 A4) Condition of transition A3 A4 2 0

0 Condition of transition A3 A4 + A3 2 0

Table (2)
MUX 1 0 1 2 3 0 A3A4 0 MUX 2 S A3A4 + A3 0

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The realization of ASM chart using multiplexers D-flip-flops and 2 4 decoder is shown in figure (3).
A3 A4 0 0 Y 1 41 2 MUX 1 3 A B 24 Decoder T0 T1 T2 T3 DA FF-A clk QA A

QA A

A3 A4 A3

0A B Y 41 2 MUX 2 3 1 DB clk FF-B QB B

QB B

Clock

Figure (3): Circuit Realization of ASM Chart

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