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Chapter 15: Design Examples

Chapter 15: Design Examples


Prof. Ming-Bo Lin

Department of Electronic Engineering National Taiwan University of Science and Technology

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

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Chapter 15: Design Examples

Objectives
After completing this chapter, you will be able to: Describe basic structures of P systems Understand the basic operations of bus structures Understand the essential operations of data transfer Understand the design principles of GPIOs Understand the design principles of timers Understand the design principles of UARTs Describe the design principles of CPUs

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Chapter 15: Design Examples

Syllabus
Objectives Bus
A p system architecture Bus structures Bus arbitration

Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples

A Basic P System

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Chapter 15: Design Examples

Syllabus
Objectives Bus
A p system architecture Bus structures Bus arbitration

Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples

Bus Structures
Tristate bus
using tristate buffers often called bus for short

Multiplexer-based bus
using multiplexers

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Chapter 15: Design Examples

A Tristate Bus

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Chapter 15: Design Examples

A Tristate Bus Example


// a tristate bus example module tristate_bus (data, enable, qout); parameter N = 2; // define bus width input enable; input [N-1:0] data; output [N-1:0] qout; wire [N-1:0] qout; // the body of tristate bus assign qout = enable ? data : {N{1'bz}}; endmodule

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Chapter 15: Design Examples

A Bidirectional Bus Example

// a bidirectional bus example module bidirectional_bus (data_to_bus, send, receive, data_from_bus, qout); parameter N = 2; // define bus width input send, receive; input [N-1:0] data_to_bus; output [N-1:0] data_from_bus; inout [N-1:0] qout; // bidirectional bus wire [N-1:0] qout, data_from_bus; // the body of tristate bus assign data_from_bus = receive ? qout : {N{1'bz}}; assign qout = send ? data_to_bus : {N{1'bz}}; endmodule
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Chapter 15: Design Examples

A Multiplexer-Based Bus

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Chapter 15: Design Examples

Syllabus
Objectives Bus
A p system architecture Bus structures Bus arbitration

Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples

Daisy-Chain Arbitration
Types of bus arbitration schemes
daisy-chain arbitration radial arbitration

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer
Synchronous transfer mode Asynchronous transfer mode

General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples

Data Transfer Modes


Data transfer modes
synchronous mode asynchronous mode

The actual data can be transferred in


parallel: a bundle of signals in parallel serial: a stream of bits

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Chapter 15: Design Examples

Synchronously Parallel Data Transfers


Each data transfer is synchronous with clock signal
Bus master Bus slave

Two types
Single-clock bus cycle Multiple-clock bus cycle

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Chapter 15: Design Examples

Synchronously Parallel Data Transfers

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Chapter 15: Design Examples

Synchronously Serial Data Transfers


Explicitly clocking scheme Implicitly clocking scheme

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Chapter 15: Design Examples

Synchronously Serial Data Transfers


Examples

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer
Synchronous transfer mode Asynchronous transfer mode

General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples

Asynchronous Data Transfers


Each data transfer occurs at random Control approaches
strobe scheme handshaking scheme

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Chapter 15: Design Examples

Strobe

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Chapter 15: Design Examples

Handshaking
Four events are proceeded in a cycle order
ready (request) data valid data acceptance acknowledge

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Chapter 15: Design Examples

Handshaking
Two types
source-initiated transfer destination-initiated transfer

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Chapter 15: Design Examples

Asynchronously Serial Data Transfers


Transmitter Receiver

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Chapter 15: Design Examples

Asynchronously Serial Data Transfers

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

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Chapter 15: Design Examples

General-Purpose Input and Output Devices


The general-purpose input and output (GPIO)
input output bidirectional

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Chapter 15: Design Examples

General-Purpose Input and Output Devices


An example of 8-bit GPIO

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Chapter 15: Design Examples

Design Issues of GPIO Devices


Readback capability of PORT register Group or individual bit control Selection the value of DDR Handshaking control Readback capability of DDR Input latch Input/Output pull-up Drive capability

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Chapter 15: Design Examples

General-Purpose Input and Output Devices


The ith-bit of two GPIO examples

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers
Interface Basic operation modes Advanced operation modes

Universal asynchronous receiver and transmitter A simple CPU design


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Chapter 15: Design Examples

Timers
Important applications
time-delay creation event counting time measurement period measurement pulse-width measurement time-of-day tracking waveform generation periodic interrupt generation

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Chapter 15: Design Examples

Timers

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers
Interface Basic operation modes

Universal asynchronous receiver and transmitter A simple CPU design


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Chapter 15: Design Examples

Basic Timer Operations


Timers
What is a timer? What is a counter? What is a programmable counter? What is a programmable timer? terminal count (binary/BCD event counter) rate generation (digital) monostable (or called one-shot) square-wave generation
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Basic operation modes

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Chapter 15: Design Examples

Terminal Count

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Chapter 15: Design Examples

Rate Generation

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Chapter 15: Design Examples

Retriggerable Monostable (One-Shot) Operation

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Chapter 15: Design Examples

Square-Wave Generation
clk 4 out 3 2 1 0(4) 3 2 1 0(4)

Latch register = 4 (a) A waveform example of square-wave mode Data bus wr latch_load Latch rd

timer_load timer_load generator clk gate

Shift plus LSB

D Q CK timer is 1 out logic

out

timer timer_enable (b) Block diagram of square-wave mode

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter
Interface Basic transmitter structure Basic receiver structure Baud-rate generators

A simple CPU design


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Chapter 15: Design Examples

UARTs
Hardware model
the CPU interface the I/O interface

Software model
receiver data register (RDR) transmitter data register (TDR) status register (SR) control register (CR)

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Chapter 15: Design Examples

UARTs

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter
Interface Basic transmitter structure Basic receiver structure Baud-rate generators

A simple CPU design


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Chapter 15: Design Examples

Design Issues of UARTs


Baud rate Sampling clock frequency Stop bits Parity check

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Chapter 15: Design Examples

A Transmitter of UARTs
The transmitter
a transmitter shift data register (TSDR) a TDR empty flag (TE) a transmitter control circuit a TDR parity generator

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 15: Design Examples

A Transmitter of UARTs

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter
Interface Basic transmitter structure Basic receiver structure Baud-rate generators

A simple CPU design


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Chapter 15: Design Examples

A Receiver of UARTs
The receiver
a RDR a receiver shift data register (RSDR) a status register a receiver control circuit

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 15: Design Examples

A Receiver of UARTs

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter
Interface Basic transmitter structure Basic receiver structure Baud-rate generators

A simple CPU design


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Chapter 15: Design Examples

Baud-Rate Generators
The baud-rate generator
provides TxC and RxC

Design approaches
Multiplexer-based approach Timer-based approach Others

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Chapter 15: Design Examples

Baud-Rate Generators

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Programming model Datapath design Control unit design
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Chapter 15: Design Examples

CPU Basic Operations

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Chapter 15: Design Examples

The Software Model of CPU


The programming model Instruction formats Addressing modes Instruction set

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Chapter 15: Design Examples

The Programming Mode

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Chapter 15: Design Examples

Instruction Formats
Two major parts
Opcode Operand

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Chapter 15: Design Examples

Addressing Modes
The ways that operands are fetched
register indexed register indirect immediate

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Chapter 15: Design Examples

The Instruction Set


Double-operand instruction set

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Chapter 15: Design Examples

The Instruction Set


Single-operand instruction set

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Chapter 15: Design Examples

The Instruction Set


Jump instruction set

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Programming model Datapath design Control unit design
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Chapter 15: Design Examples

A Datapath Design

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Chapter 15: Design Examples

ALU Functions

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Chapter 15: Design Examples

Syllabus
Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design
Programming model Datapath design Control unit design
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Chapter 15: Design Examples

A Control Unit
The decoder-based approach

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Chapter 15: Design Examples

A Control Unit
A better approach

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Chapter 15: Design Examples

A Control Unit
The operations of T3 and T4 are determined separately by each instruction

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