EE 483/EE 580 Course Syllabus Spring 2001

Instructor: Office: Phone: E-mail: WWW:

Dr. George Engel EB3043 (618) 650-2806 gengel@ee.siue.edu http://www.ee.siue.edu/~mentor http://www.ee.siue.edu/~mentor

Lectures:

T R

6:00 pm - 7:15 pm

Course Description: Principles of computer design and performance evaluation. Implementation of data and control units. Memory, I/O, bus, and operating system issues. Introduction to hardware description languages (VHDL). Review of current processor architectures. Prerequisites: EE382 or consent of instructor.

Grading: Semester grades will be computed as follows: Exam #1 Exam #2 Exam #3 Lab Exercises and Homework Final Project ............ ............ ............ ............ .............. 20% 20% 20% 20% 20%

Text: Computer System Architecture: Third Edition Morris Mano Prentice Hall, 1993 Optional (Many VHDL Made Easy David Pellerin Prentice Hall, VHDL tutorials exist on the WEB so the book is not mandatory) (I personally like the book!) and Douglas Taylor 1997

EE483/EE580 Lecture Schedule For Spring 2001

Jan 09 (T)

Ch 1: Review: Combinational and Sequential Logic Design -- Schematic Driven Design --- Introduction to VHDL -Ch 2: Review: Digital Components -- A First Look at VHDL -Ch 3: Review: Number Representations and Systems -- VHDL: Exploring Objects and Data Types -- VHDL: Using Standard Logic Ch 4: Register Transfer and Micro-operations -- VHDL: Understanding Concurrent Statements -- VHDL: Understanding Sequential Statements -- VHDL: Creating Modular Designs -- VHDL: Partitioning Your Design -- VHDL: Writing Test Benches Ch 5: Basic Computer Organization and Design 5.1 Instruction Codes 5.2 Computer Registers Ch 5 5.3 Computer Instructions 5.6 Memory Reference Instructions

Jan 11 (R) Jan 16 (T)

Jan 18 (R)

Jan 23 (T)

Jan 25 (R)

Jan 30 (T) Feb 01 (R)

Ch 5: Basic Computer Organization and Design 5.4 Timing and Control 5.5 Instruction Cycle Ch 5: Basic Computer Organization and Design 5.9 Hardwired Control 5.10 Design of Accumulator Logic Ch 6: Programming the Basic Computer -- EXAM # 1 -Behavioral Level VHDL Model of SEP Ch 7: Microprogrammed Control 7.1 Control Memory 7.2 Address Sequencing Design of Control Unit Ch 7: Microprogrammed Control Nanoprogramming Minimizing the width of control memory Ch 8: CPU 8.2 Register Organization 8.3 Stack Organization Ch 8: CPU 8.4 Instruction Formats 8.5 Addressing Modes Ch 8: CPU 8.6 Data Transfer and Manipulation

Feb 06 (T)

Feb 08 (R) Feb 13 (T) Feb 15 (R) Feb 20 (T)

Feb 22 (R)

Feb 27 (T)

Mar 01 (R)

Mar 06 (T)

Mar 08 (R)

Ch 8:

CPU 8.7 Program Control 8.8 CISC versus RISC

Mar 13 (T) Mar 15 (R) Mar 20 (T)

*** SPRING BREAK *** *** SPRING BREAK *** Ch 9: Pipelining 9.1 Parallel Processing 9.2 Pipeline Concept Ch 9: Pipelining 9.3 Arithmetic Pipeline 9.4 Instruction Pipeline Ch 10: Computer Arithmetic 10.2 Addition and Subtraction 10.3 Multiplication

Mar 22 (R)

Mar 27 (T)

Mar 29 (R) Apr 03 (T) Apr 05 (R)

--

EXAM # 2 -Computer Arithmetic 10.3 Multiplication Computer Arithmetic 10.4 Division 10.5 Floating-point Organization Peripheral Devices I/O Interface Asynchronous Data Transfer

Ch 10: Ch 10:

Apr 10 (T)

Ch 11: I/O 11.1 11.2 11.3

Apr 12 (R)

Ch 11: I/O Organization 11.4 Modes of Transfer 11.5 Priority Interrupt Ch 11: I/O 11.6 11.7 11.8 Organization DMA I/O Processor Serial Communications

Apr 17 (T)

Apr 19 (R)

Ch 12: Memory Organization 12.2 Main Memory 12.3 Auxiliary Memory 12.4 Associative Memory Ch 12: Memory Organization 12.5 Cache Memory 12.6 Virtual Memory Ch 12: Memory Organization 12.6 Virtual Memory 12.7 Memory Management Hardware

Apr 24 (T)

Apr 26 (R)

EE483/EE580 Lab Schedule For Spring 2001

Jan 08 Jan 15 Jan 22

--- NO LABS --Lab #1: Schematic Driven Design: Design Architect and QuickSIM Tutorial Example Lab #2: More Schematic Driven Design: Design Architect and QuickSIM Design ALU described in Mano textbook. Lab #1 should be submitted for grading. Lab #2: More Schematic Driven Design: Design Architect and QuickSIM Continue design of ALU described in Mano textbook. Lab #3: VHDL Design: Qvcom and Qvsim Tutorial Example: 4-bit counter Lab #2 should be submitted for grading. Lab #4: More VHDL Design: Design ALU using VHDL Submit lab #3 for grading. Qvcom and Qvsim

Jan 29 Feb 05

Feb 12

Feb 19 Feb 26 Mar 05

Lab #4: More VHDL Design: Qvcom and Qvsim Finish design of ALU using VHDL Lab # 5: Synthesis using Leonardo circuit synthesizer Submit lab #4 for grading. Lab #6 Exploring SEP operation Modifying the SEP Submit lab #5 for grading. *** SPRING BREAK *** Continue Lab #6 Exploring SEP operation Work on Final Project. Submit lab #6 for grading. Work on Final Project Work on Final Project Work on Final Project Work on Final Project

Mar 12 Mar 19 Mar 26 Apr 02 Apr 09 Apr 16 Apr 23