Compact Modeling and Simulation of Pd-Soi Mosfets: Current Status and Challenges

Compact Modeling and Simulation of PD-SOI MOSFETs: Current Status and Challenges
Jung-Suk Goo1, Richard Q. Williams2, Glenn O. Workman3, Qiang Chen4, Sungjae Lee2, and Edward J. Nowak2
1Technology 2SOI
Development Group, Advanced Micro Devices Inc. Compact Modeling Group, IBM Corporation 3CMOS Next Generation Design Foundations, Freescale Semiconductor Inc. 4Was with AMD Inc., now with Synopsys Inc.
Outline
Overview of the PD-SOI CMOS Technology Self-heating Model Parameter Calibration Flow Challenges in Measurement and Calibration Floating-Body Effects Modeling: History-Effect Body-Contacted Device Modeling Floating-Body Effects Simulation Issues Model Standardization Conclusion
2 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
History of Manufacturing PD-SOI

Successfully manufactured in ULSI from the 225 nm through the 45 nm nodes 0.2um 64b PowerPC Processor
Inverter +15% 2-input NAND +20% 4-input NAND +28% 2-input NOR 4-input NOR XOR +40% +21% +26%
45 nm 2GHz eDRAM
PD-SOI Performance Improvement compared to bulk
Domino AND +15% Domino MUX +25% SRAM 0%(bulk) +20% 20% 40%
1999 ISSCC by D. H. Allen et al.
2008 VLSI Symp. by P. Klim et al.
Benefits of PD-SOI CMOS

Higher performance and lower power
Dynamic threshold (Vt) lowering Reduced capacitive loading Reduced body effects in stack transistor circuits
Better control
Reduced Vt versus Lgate sensitivity Elimination of well-implant proximity effects (WPE) Natural isolation of auxiliary device elements (embedded DRAM, passives, high-voltage, and RF devices)
Better reliability
Reduced soft-error rates Elimination of latch-up
Bulk CMOS vs. PD-SOI CMOS

Bulk CMOS PD-SOI CMOS
Identical body potential
Independent body potential
The chief difference of the PD-SOI is that the body of each SOI transistor is an independent 4th terminal for the device When absolutely needed, the body can be fixed to a chosen potential with a body tie
Transistor with body tie
Floating Body Transistor
However, in 99.9% of the chip, transistors will be operating as floating body devices
Self-Heating: DC Rth Measurement

TD Cth Rth Ith=Power
IR
+ VR Drain
T0
Gate Source
Rth =
dRGate dT dT = dPower dRGate dPower

700
600
Device Turned Off

RGate []
600 500 400 0
Device Turned On
RGate []
500 400 300 -50
50
100
o
150
Chuck Temperature [ C]
Device Power [mW]
Self-Heating Removal
Channel Current
3.0 2.5
As Measured Self-Heating Removed
Parasitic Current
4.0
As Measured Self-Heating Removed
Drain Current [mA]
2.0 1.5 1.0 0.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2
Body Current [nA]
3.0
2.0
1.0
0.0 0.0
-0.5
-1.0
-1.5
Drain Voltage [V]
Gate Voltage [V]
Based on measured temperature dependence of the current

Linear Quadratic Exponential
Self-Heating during Simulation
Addition of temperature node leads to simulation time increase, and, possibly, convergence issue Can disable self-heating mode for many high-performance logic products
Switching time is much faster than the thermal time constant Most analog blocks are operating at low enough bias range
PD-SOI Model Parameter Calibration

method 1
Self -Heating R th , C th fitting
method 2
Self -Heating Removal from IV
DC Body Currents Fitting (Idiode , Igb , Iii, I GIDL ) Body Effect & CV Fitting First -pass BC IV Fitting First -pass FB IV Fitting Refine Calibration
Check Circuit Response
Body Contacted Fitting
Floating Body Fitting
Recenter Model
Done
Do History-Effect Modeling First!

Intrinsic MOSFET Characteristics IDsat, Ioff, Vt, Parasitic Characteristics Idiode, Igb,
History Effect
Intrinsic MOSFET characteristics have only small impact on history effect
Except for the body-effect
Adjusting parasitic characteristics have huge impact on history effect and cause noticeable change in channel current
Challenges in Measurement & Calibration

Active Gate Poly P+ I/I
Parasitic OppositeType Gate

STI P+
P+ P-
N+ P w/ halo
Bridge-Region Easily Gets FullyDepleted

Parasitic Opposite-Type Gate

1x10 1x10 1x10 1x10 1x10 10 10 10 10
-6 -7 -8 -9
nMOS
Bulk BT/SOI IGG IGB
1x10 1x10 1x10 1x10 1x10 10 10 10 10
-6 -7 -8 -9
pMOS
Bulk BT/SOI IGG IGB
Gate Current [A]
-10 -11 -12 -13 -14
Gate Current [A]

-1.0 -0.5 0.0 0.5 1.0 1.5
-10 -11 -12 -13 -14
-1.5
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
VG [V]
VG [V]
Big discrepancy in Igb characteristic due to the parasitic

Especially in inversion region
Solutions:
Selectively use specific regions Use bulk wafer
Fully Depleted Body

Body-Effect
0.5 0.4 0.3
VDS=0.1V
Junction Capacitance
1.5
0.2 0.1 0.0 -0.6
VDS=1.2V
CJunction [pF]
0.0 0.2 0.4 0.6
1.0
VT [V]
0.5
nMOSFET 2/0.0875m
0.0 -1.0 -0.5 0.0 0.5
-0.4
-0.2
Vbs [V]
Vbias [V]
Body bias can cause a fully-depleted body DBS1 Low-doped bridge region can introduce artifacts in measured data Solutions:
Selectively use specific regions Emphasize intrinsic response
Slide 13 DBS1 I cannot change this graphic image, but it should not be hyphenated because the ly in fully = the hyphen in this use
David B. Schlosser, 9/13/2008
Implicit Calibration using RF Data

90
Transconductance (Gm)
88 86 84 82 80 3 10
Impact Ionization Self-heating
Floating-Body
Body Resistance
Body-Contacted
10
10
10
10
10
10
10
10
Frequency [Hz]
RF measurement offers much implicit information:

Self-heating response time Impact ionization Body-contact time constant
What Causes Floating-Body Effect?

Body potential is a function of:
Capacitive coupling to
Source Drain Gate Substrate (small)
Source
Drain
Diode leakages to
Source Drain Buried Oxide
Gate leakage Impact ionization
Substrate
Also subject to the previous switching history
CMOS Inverter Operation
Definition of History-Effect
Definition of History-Effect
2nd
1st
History-effect H = ( 1st 2nd) / 2nd
1st switch : input transition after being held constant for a long time 2nd switch: input transition short time after the 1st switch
Typical History-Effect
Evolution of Switching Delay
15 14 Delay/Stage [ps] 13 12
tr=tf =0.8ns
Input Clock Shape
1st SW
2nd SW
11 t =40ns (50% duty) per 10 -10 10

step=100ps
Dynamic Steady State

-7 -6
10
-9
10
-8
10 10 Time [s]
10
-5
10
-4
Delay is subject to switching history of the logic gate
Pulse Compression vs. Expansion
Positive H ( 1st > 2nd)
Compression
Negative H ( 1st < 2nd)
Expansion
Impact of Loading on History-Effect

Unloaded
6.5 6 5.5 5
t =t =0.8ns
Heavily Loaded
100
IBM 9S 2 Mode l (1.2V 25C)
95
Delay/Stage [ps]
Delay/Stage [ps]
90 85 80 75 t =t =0.8ns r f 70
t
per
12.3%
1st t
rr
14.9%
1s t t
rr
2nd t
2nd t
ff
ff
4.5
per
=40ns (50% duty)
=40ns (50% duty)
step=100ps
s te p=100ps
4 -10 10
10
-9
10
-8
10 10 Time [s]
-7
-6
10
-5
10
-4
65 -10 10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
Time [s]
Very limited impact of loading capacitance

Extremely large loading (100fF) -- changing switching delay by ~15X Only changes ~2% in history-effect
Combined Capacitive/Resistive Network
C1
R1
C-Divider
C2
R2
Voltage
RC Decay
R-Divider
Time
Time for Actual Contribution to Speed
Initial DC Conditions
Capacitive Coupling
1st SW : Initial DC 2nd SW : Initial DC + Capacitive Coupling

Capacitive Coupling
Gate Coupling
Drain Coupling
Gate Coupling
Drain Coupling
Capacitive coupling is stronger to drain than to gate
Key Components
(Initial DC Condition)
1st SW
Igb,acc Idio,rev IGIDL II/I Idio,for
1st SW Initial
2nd SW
Igb,inv
Idio,for
KCL balance between forward and (reverse Idiode+IGIDL+II/I) Accumulation Igb is much smaller than forward Idiode
2nd SW Initial
KCL balance between forward Idiode*2 and inversion Igb
Key Components
VDD
(Capacitive Coupling)
Cj,rev
+
Cgb,acc
Vbs = VDD
Cj,for
C j , rev C gb , acc + C j , for + C j , rev
Vb -
Basically a voltage-divider that consists of

Gate-body capacitance, and Junction capacitance
Key Components
(Body-Effect)
Vt vs. Vbody
Diode current Gate current Gate capacitance Junction capacitance
Vbody
Vt & speed
Body potential is established mostly by diode and gate characteristics (DC and AC) This body potential is translated into the actual switching performance by the body-effect (the main transfer function)
Impact of Gate Capacitance & Current

30 25 20
Inversion Cgb Impact
30 25 20
Inversion Igb Impact
(1 -2 )/2 [%]
(1 -2 )/2 [%]
15 10 5 0 -5 -10 0.8
15 10 5 0 -5 -10
nd
nd
nd
nd
Increasing accumulation Cgb 2nd Vb

1.0 1.2 1.4 1.6
Increasing inversion Igb 2nd Vb

0.8 1.0 1.2 1.4 1.6
st
st
VDD [V]
VDD [V]
Cgb is critical for VDD dependence slope Igb became a major factor from 90 nm technology onward
Vb , 2 nd = VDD
Cdb C gb + Csb + Cdb
Impact of Diode Current

30 25 20
Forward Idiode Level Impact
30 25 20
Reverse Idiode Impact
(1 -2 )/2 [%]
15 10 5 0 -5 -10 0.8
(1 -2 )/2 [%]
15 10 5 0 -5 -10
nd
nd
Increasing forward Idiode 1st Vb 2nd Vb

1.0 1.2 1.4 1.6
nd
nd
Increasing reverse Idiode 1st Vb

0.8 1.0 1.2 1.4 1.6
st
VDD [V]
st
VDD [V]
The diode current characteristic is the key characteristic dominating the VDD and temperature dependences of the history-effect
Proportional to forward Idiode Inversely proportional to reverse Idiode
Final Reproduction of History-Effect

15
1000-stage Delay Chain o INV FO=1 @25 C Technology-A
History Effect [%]
10
5
Data Model
0 0.6 0.8 1.0
25 C o 100 C
1.2
1.4
1.6
VDD [V]
The measured history-effect can be successfully reproduced across a wide range of conditions when all the key components are properly modeled
Other Floating Body Effects: Parasitic BJT

C
IN
OUT
2007 CICC by W. Wu et al.
Challenges: Statistical Modeling

15 10 5 0 -5
Data Typical Corner
History Effect [%]
1000-stage Delay Chain o INV FO=1 @25 C 46-Sites in Total Technology-B
0.8V
1.0V
1.2V
1.5V
VDD [V]
Single-stage logic gate measurement Delay chain measurement In-line characterization
Requires very high-accuracy test equipment Extremely low throughput Averaged over all stages, loosing variation details Large area Approximate precision
Back-Bias Range of Interest

Body-Contacted and Bulk
0.5
Floating Body
Reverse
VDS=0.1V
0.4 0.3
VT [V]
0.2 0.1 0.0 -0.6
VDS=1.2V
Forward
nMOSFET 2/0.0875m
-0.4
-0.2
0.0
0.2
0.4
0.6
Vbs [V]
Sometimes the body effect is not able to fit for the entire range Then some range should be compromised Separating body-contacted and floating-body models maybe more desirable
Can Body Be Really Tied?

Gate 0.3
0.2 0.1
Body Potential Fluctuation
12
History Effect of BC CMOS

WN=WP/2=1m
Coupling
(1 -2 )/2 [%]
Vbody [V]
0.0 -0.1 -0.2 -0.3 0.0 0.1
nd
nd
Body RC Decay
st
Drain 0.3 Coupling Time [nsec]

0.2
0.4
0.5
10
10
10
10
Frequency [Hz]
Body-contacted PD-SOI circuit experiences the coupling effects exactly same as floating-body one Thus, it also exhibits history effect
Body-Contact: Gate Capacitance

Active Gate Poly P+ I/I Drain Drain
Physical
BSIMPD ~ BSIMSOI 4.0
Ap+
Body
An+
Body
Agbcp
Source
Source
p+/p-
n+/p-
n+/p
n+/p
n+/p
n+/p
Rbodyext
Rbp
Rbodyext
Rbp

Gate Capacitance
Active Gate Poly P+ I/I
CGG
P+ gate P body N+ gate P body
P+ STI P+ P-
N+ P w/ halo
-3
-2
-1
VG [V]
OverEstimated
QGB CG dVGS
QGC
VFB VDD
VT
VT
CG dVGS

40
Charge Ratio
Qp+ Qn+ Qp+/Qn+ Ratio
Impact on Switching Delay

0.8
30
0.6
Delay (1 +2 )/2 [ps/stage]
QGC
nd
20
0.4
Qp+/Qn+
~4.5%
10
0.2
7
Physical Agbcp=An++Ap+ W N=W P/2=1m 10 FET Segments
9
st
0.0
6 8 10
Agbcp=An+
10
10
10
VG [V]
Frequency [Hz]
The charge ratio is 0.2 ~ 0.5 within practical range

2 ~ 5x overestimation
Its impact of switching delay is not negligible


Active Gate Poly P+ I/I Drain Drain
Physical
BSIMSOI 4.1
Ap+
Body
An+
Agbcp2
Body
Agbcp
Source
Source
p+/p-
n+/p-
n+/p
p+/p
n+/p n+/p
Rbodyext
Rbp
Rbodyext
Rbp
Bias Dependence of Body Resistance
Courtesy of Alvin Loke et al.
Body resistance is determined by majority carriers in the neutral region
Bias Dependence of Body Resistance

Body Bias Dependence Gate Bias Dependence
2007 CICC by W. Wu et al.
Bias significantly modulates the depletion region; in turn, body resistance

Not captured in BSIMSOI Well captured in PSP-SOI
Body-Contact: Distributed Body R

Distributed
N segments p+/pcap n+/pcap n+/p FET n+/p FET
Single Lumped
Rbodyext
RbpH/N
RbpH/N
Rbodyext
Rbp
Measurement
Model
DC Values
AC Values?
Body-Contact: Distributed Body R

Rule of Thumb
Factor of 1/3 for single-side contact; 1/12 for double-side contact Mathematically derived for gate resistance noise
A. B. Philips, BJT Base Resistance (McGraw-Hill, 1962) R. P. Jinal, MOSFET Gate Resistance (IEEE T-ED, pp. 1505-1509, October 1984)
Applicable for other distributed resistance associated with active gain

10 8
10-seg T-gate 10-seg H-gate 1-Lump 1/3 1-Lump 1/12
History Effect [%]
6 4 2 0 10
8
Technology-C WN=WP/2=5m
10
10
10
Frequency [Hz]
PD-SOI Circuit Simulation: Accuracy

8 7 6 5 4
1 SW nd 2 SW
st
Delay/Stage [ps]
10
-9
10
-8
10
-7
10
-6
1x10
-5
1x10
-4
vntol in HSPICE [V]
Accuracy options
Vbody << VDD needs higher accuracy in voltage convergence criteria (vntol, etc.) Ibody << IDS needs tighter control on off-conductance of capacitors (gmindc) Stronger sensitivity of diode currents at low temperature needs special attention on numerical convergence criteria
PD-SOI Circuit Simulation: Time

60
Technology-D
Harmonic balance
Solves Fourier series in f-domain Requires over-sampling and sufficient harmonics
Switching Delay [ps]
st 55 1 SW
50
2 SW
nd
Periodic steady state

Projects the evolution of the net body charges using the Newton method
Transient Transient HB
45 40 -9 10
Indirect body initialization technique Transient HB

.ic v(n)=VDD/2 Speed up by orders in magnitude
10
-7
1x10
-5
10
-3
10
-1
Time [sec]
Charging/discharging
Circuits in sleep and wake-up modes
Steady-state
Critical for larger multi-input circuits, SRAMs, clock drivers, I/O, PLL, etc. Takes s~ms impractically long
Model Standardization
Compact Modeling Council (CMC)
Hosted by the Government Electronics and Information Association (GEIA) Evaluates fundamental physics and numerical properties
Symmetry, continuity, convergence, and runtime
Publishes requirements and procedure
Benefits
Consistency in implementation on user side Recognition and funding to model developers Improved model accuracy and features
Through detailed review during the standardization process
CMC-Standard SOI Model

BSIMPD BSIMSOI (University of California, Berkeley) Next-generation SOI standardization was kicked off in 2006 Candidates
PD DD (FD) PSP-SOI PD, XSIM PD PSP-SOI DD, HiSIM-SOI, ULTRA-SOI, XSIM DD
Conclusion
Reviewed the current and future challenges in compact modeling, characterization, and circuit simulation of PD-SOI CMOS Floating-body effects
One of the main performance boosters Main complexity in PD-SOI compact modeling Measuring key components is challenging Nevertheless, mechanisms are well understood; thus, can be reproduced
Body-contacted device modeling

Parasitic gate capacitance and body resistance need to be accurate Distributed effect of the body resistance can be simplified
PD-SOI simulation requires tighter convergence criteria and novel simulation techniques, mainly due to the floating-body effects Model standardization promotes implementation consistency and improved accuracy and features.
Acknowledgments
Advanced Semiconductor Technology Alliance (ASTA)
Technical contributions
K. Bernstein (IBM) B. Rice (Freescale)
Management support
A. Icel and N. Kepler (AMD) S. Springer and R. Wachnik (IBM) S. Jallepalli and M. Zunino (Freescale)
Academic SOI Compact Modeling Research Groups

BSIMSOI PSP-SOI UFSOI HiSIM-SOI XSIM ULTRA-SOI Prof. Chenming Hu (University of California, Berkeley) Prof. Gennady Gildenblat (Arizona State University) Prof. Jerry G. Fossum (University of Florida, Gainesville) Prof. Mitiko Miura-Mattausch (Hiroshima University) Prof. Xing Zhou (Nanyang Technological University) Prof. Jin He (Peking University)

Compact Modeling and Simulation of Pd-Soi Mosfets: Current Status and Challenges

Încărcat de

Informații document

Descriere originală:

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Compact Modeling and Simulation of Pd-Soi Mosfets: Current Status and Challenges

Încărcat de

Drepturi de autor:

Formate disponibile

Compact Modeling and Simulation of PD-SOI MOSFETs: Current Status and Challenges

2 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008

History of Manufacturing PD-SOI

PD-SOI Performance Improvement compared to bulk

1999 ISSCC by D. H. Allen et al.

2008 VLSI Symp. by P. Klim et al.

3 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008

Benefits of PD-SOI CMOS

4 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008

Bulk CMOS vs. PD-SOI CMOS

Identical body potential

Independent body potential

Floating Body Transistor

Self-Heating: DC Rth Measurement

dRGate dT dT = dPower dRGate dPower

Device Turned Off

500 400 300 -50

Device Power [mW]

Drain Current [mA]

Body Current [nA]

Drain Voltage [V]

Gate Voltage [V]

Based on measured temperature dependence of the current

7 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008

Self-Heating during Simulation

PD-SOI Model Parameter Calibration

Self -Heating R th , C th fitting

Self -Heating Removal from IV

Body Contacted Fitting

Floating Body Fitting

Do History-Effect Modeling First!

Challenges in Measurement & Calibration

Parasitic OppositeType Gate

Bridge-Region Easily Gets FullyDepleted

Parasitic Opposite-Type Gate

1x10 1x10 1x10 1x10 1x10 10 10 10 10

Gate Current [A]

-10 -11 -12 -13 -14

Gate Current [A]

-10 -11 -12 -13 -14

Big discrepancy in Igb characteristic due to the parasitic

Fully Depleted Body

0.2 0.1 0.0 -0.6

0.0 -1.0 -0.5 0.0 0.5

Implicit Calibration using RF Data

Impact Ionization Self-heating

RF measurement offers much implicit information:

What Causes Floating-Body Effect?

Gate leakage Impact ionization

Also subject to the previous switching history

15 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008

CMOS Inverter Operation

16 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008

17 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008

History-effect H = ( 1st 2nd) / 2nd

Input Clock Shape

11 t =40ns (50% duty) per 10 -10 10

Dynamic Steady State

Delay is subject to switching history of the logic gate

19 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008

Pulse Compression vs. Expansion

Positive H ( 1st > 2nd)